Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/14—Picture signal circuitry for video frequency region
  • H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
  • H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
  • H04N5/185—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit for the black level
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
  • H04N23/50—Constructional details
  • H04N23/51—Housings
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
  • H04N25/633—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current by using optical black pixels
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

• This invention relates to the field of electronic cameras, and in particular to analog and digital electronic circuitry to improve cameras using charge- coupled devices (CCDs) in digital-output machine-vision applications.
• CCDs charge- coupled devices
• a circuit for converting an analog image-bearing signal from an electronic imaging device.
• the image-bearing signal provides both an pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device.
• the circuit includes a voltage clamp that adjusts a level ofthe image-bearing signal based on a black reference level to produce a clamped image-bearing signal.
• An analog-to-digital converter (ADC) is coupled to digitize the clamped image-bearing signal and operated to produce a first digital value representative ofthe pixel-reference signal for a pixel, and operated to produce a second digital value representative ofthe pixel- image signal.
• the above circuit further includes a first digital register having an input connected to the ADC to receive and temporarily store the first digital value, and a second digital register having an input connected to the ADC to receive and temporarily store the second digital value, wherein the first digital subtractor has an input connected to the first register and second registers.
• the method steps (a) through (d) are performed on a plurality of imaging pixels within a row of pixels ofthe imaging device. In another such embodiment, the method steps (a) through (d) are performed on a plurality of non-imaging pixels ofthe imaging device.
• FIG. 4B is a stylized timing diagram showing the relationship of sampling clock 205 and signal V out 119 (as represented by idealized signal 440).
• FIG. 4C is a flow chart showing one method for adjusting sampling clock 205 relative to signal V out 119.
• FIG. 8 A is a drawing ofthe mounting mechanism of one embodiment of a machine- vision camera.
• FIGs. 8B, 8C, 8D, 8E are drawings ofthe mounting mechanism of another embodiment of a machine- vision camera.
• FIG. 9 is a drawing of a system 900 that uses machine- vision camera 100 in an automated manufacturing situation.
• FIG. 10 shows a multiple-dovetail unit 8100, dovetail-slot guiderail 890, and a dovetail slot 512 formed onto strobe 940.
• the reference voltage for a pixel is stored in a sample-and-hold circuit, and this reference voltage and the image voltage for that pixel are fed to a differential amplifier to generate a difference voltage representing the true image for that pixel. If a source of noise or error affects both the reference and image voltages, generating this difference will remove the effect ofthe noise from the image signal.
• Some CCD circuits also provide one or more "black pixels" at the beginning and/or end of each row and/or column. In some embodiments, these black pixels have opaque coverings but are otherwise identical in signal characteristics as imaging pixels, and thus the signal from those pixels is representative ofthe signals of other pixels were those pixels to receive a black image (i.e., a pixel having no light).
• Packetizer, serializer, & transmitter block 140 outputs the serial digital image 149 from machine- vision camera 100, as well as other information necessary for the operation of machine- vision camera 100 onto user interface 190.
• Receiver, deserializer, & depacketizer block 150 receives data into camera 100, such as operational commands, frame timing signals, and aperture control from user interface 190.
• Block 150 deserializes the information and passes the information onto command processing circuit 160.
• Command processing circuit 160 controls the aperture speed and timing, and clock circuitry 180.
• the control output of clock circuitry 180 provides clocks for the output timing of CCD sensor 110, timing for digitizing & digital-signal-conditioning 130, and output timing for output onto user interface 190 by block 140.
• Figure 2 A shows a more detailed block diagram of one embodiment of machine-vision camera 100 ofthe present invention.
• Image sensor 110 includes an array 112 of CCD pixels and output circuitry 114.
• image sensor 110 includes a full-frame 640-by-480 pixel CCD image sensor, Model KAI-0310 (available from Eastman Kodak Company - Microelectronics Division, Rochester, New York 14650-2010).
• image sensor 110 includes a full-frame 1024-by-1024 CCD image sensor, Model KAI 1001 series CCD sensor (also available from Eastman Kodak Company - Microelectronics Division, Rochester, New York 14650-2010).
• Output circuitry 114 serially outputs an analog image-bearing signal, V out 119, to analog-signal-conditioning circuit 120.
• V ou ⁇ 119 is supplied as a 300 millivolt image-bearing signal on top of, for example, an 8-volt DC component.
• V out 119 is applied through DC-blocking capacitor 122 (which removes the DC component just mentioned) to the input of amplifier 124, which is also coupled to "clamp" or integrator/offset-level adjustor 126 (which provides a replacement adjustable "DC” or “offset-level” component for the signal from the CCD 110 that can be varied, as described below).
• the output of amplifier 124 is applied to the input of analog-to-digital converter (ADC) 132.
• ADC analog-to-digital converter
• amplifier 124 is omitted, and the clamped signal is coupled directly to ADC 132.
• Clock generator 180 includes circuitry that generates clocks, including clocks 171 and 205, and clock-enables 207 and 209.
• clock generator 180 includes phase-locked loop circuitry to generate control clocks for output circuitry 114 (clocks 171) and ADC 132 (clock 205) which are synchronized to one another and are automatically varied in edge timing (and/or frequency) as outside stimuli, e.g., ambient temperature, affects the timing ofthe output signal 119 ofthe CCD image sensor.
• a tapped delay line 281 coupled to multiplexors for example, multiplexors 283 and 284 in a suitable programmed field-programmable gate array (FPGA) 282, programmable array logic (PAL) or application-specific integrated circuit (ASIC) chip are used to implement suitable multiplexors
• FPGA field-programmable gate array
• PAL programmable array logic
• ASIC application-specific integrated circuit
• oscillator 280 drives FPGA 282, which in turn drives tapped delay line 281, and receives the N tapped, delay signals from delay line 281.
• tapped delay line 281 provides ten taps at one nanosecond (ns) intervals, i.e., each delayed one nanosecond more than the one before.
• Multiplexor (mux) 283 and mux 284 each select one (either the same or different ones) ofthe delayed signals under the control of clock control logic 286, thus allowing selection at an output such as 287 of a clock that is delayed by the same amount on both its rising and falling edges.
• both the rising-edge delay and the falling edge delay can be separately specified at output 288, where latch 285 is set by the output of mux 283 and reset by the output of mux 284.
• divider 289 provides the ability to divide the frequency ofthe clock from oscillator 280 as required for various clock requirements.
• the ADC would not output the correct value for the condition of maximum difference between the reference level and the image level since the ADC cannot output negative values.
• the dynamic range of the system would then be limited to 800 values.
• the V ⁇ mg for a pixel n is measured; at block 472, the delay of P ⁇ mg for a subsequent pixel n+1 is increased slightly, and at block 474, the V ⁇ mg for the subsequent pixel n+1 is measured; at block 476 the V ⁇ mg(n+1) is compared to V ⁇ mg(n) and if it has changed significantly, control drops to block 478 where the delay is shortened by an empirically determined (or predetermined) amount to ensure operability ofthe system, and at block 480, this delay is saved for later use; and if at block 476 the measured V ref had not changed significantly, control is passed back in the loop to block 472 and the process is iterated until the "correct" timing edge is determined.

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Transforming Light Signals Into Electric Signals (AREA)

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• 1998
  • 1998-07-30 WO PCT/US1998/015848 patent/WO1999007138A1/en not_active Application Discontinuation
  • 1998-07-30 EP EP98938145A patent/EP1000506A1/de not_active Withdrawn

Non-Patent Citations (1)

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