EP0978852A1 - Inductance de puce multicouche - Google Patents
Inductance de puce multicouche Download PDFInfo
- Publication number
- EP0978852A1 EP0978852A1 EP99114703A EP99114703A EP0978852A1 EP 0978852 A1 EP0978852 A1 EP 0978852A1 EP 99114703 A EP99114703 A EP 99114703A EP 99114703 A EP99114703 A EP 99114703A EP 0978852 A1 EP0978852 A1 EP 0978852A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- sheets
- outermost
- terminal
- sheet
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004020 conductor Substances 0.000 claims abstract description 53
- 239000003989 dielectric material Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910000859 α-Fe Inorganic materials 0.000 description 6
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
Definitions
- the present invention relates to a chip inductor; and, more particularly, to a multilayer type chip inductor employing a pair of outermost sheets having an identical terminal pattern in shape, respectively, the terminal pattern being capable of providing various positions for a via hole for electrically connecting the terminal pattern with conductor patterns of intermediate sheets.
- a multilayer type chip inductor is comprised of a stack of sheets made of a plurality of ferrite or dielectric materials, having respective coil patterned conductors formed thereon and connected electrically by the via holes in series with each other in substantially zigzag fashion.
- Such a multilayer type chip inductor is used, for example, for suppressing noise or making a LC resonance circuit.
- Fig. 1 shows an exploded view of the conventional multilayer type chip inductor disclosed in Japanese Laid-open Utility Model Publication No. 57-100209.
- the conventional multilayer type chip inductor includes a pair of generally rectangular outermost sheets 1, 1' made of the ferrite or the dielectric material and a plurality of intermediate sheets 2 made of the ferrite and dielectric material stacked one above the other and firmly sandwiched between the outermost sheets 1, 1'.
- the outermost sheet 1 has a front surface formed with a generally L-shaped electric terminal pattern 6.
- the electric terminal pattern 6 has a lengthwise strip 6a extending along and adjacent to a longer side of the outermost sheet 1 and terminating at a generally intermediate portion of the longer side of the outermost sheet 1, and a lateral strip 6b continued to the lengthwise strip 6a and extending along a shorter side of the outermost sheet 1 for electric connection with an end cap or like terminal member (not shown).
- the outermost sheet 1' has at its front surface a generally L-shaped electric terminal pattern 6' composed of a lengthwise strip 6'a and a lateral strip 6'b, wherein, the terminal pattern 6' thereof is offset 180° with respect to the terminal pattern 6 on the outermost sheet 1 about an imaginary plane passing intermediately between the outermost sheets 1, 1' in a widthwise direction of the stack, and the lengthwise strip 6'a has at its end a via hole 4'.
- the via hole 4' is formed by perforating the outermost sheet 1' across the thickness thereof so as to leave a cylindrical wall (not shown).
- Each of the intermediate sheets 2 has a front and a reverse surfaces opposite to each other.
- the front surface of each of the intermediate sheets 2 is, respectively, formed with a generally U-shaped electric conductor pattern 3.
- Each of the conductor patterns 3 has a perforated end 3a formed with a via hole 4 and a non-perforated end 3b. Similar to the above-mentioned via hole 4', the via hole 4 is formed by perforating the respective intermediate sheet 2 across the thickness thereof so as to leave a cylindrical wall (not shown).
- the above-mentioned cylindrical walls are plated with the conductive material.
- the intermediate sheets 2 are stacked one above the other in such a way that, when one intermediate sheet 2 is turned 180° on an imaginary plane parallel thereto, the perforated end 3a and the non-perforated end 3b thereof are, respectively, contacted with the non-perforated end 3b and the perforated end 3a of the neighboring intermediate sheet 2 thereabove or therebelow, whereby the intermediate sheets 2 can be electrically connected with each other through the via holes 4.
- the outermost sheet 1 is positioned below the lowermost intermediate sheet 2 in such a way that the lengthwise strip 6a thereof comes into contact with the perforated end 3a of the lowermost intermediate sheet 2 through the via hole 4, and the outermost sheet 1' is positioned above the uppermost intermediate sheet 2 in such a way that the lengthwise strip 6'a thereof comes into contact with the non-perforated end 3b of the uppermost intermediate sheet 2 through the via hole 4' thereof, whereby the conductor patterns 3 on the intermediate sheets 2 and the terminal patterns 6, 6' on the outermost sheets 1, 1' are electrically connected with each other through the via holes 4, 4'.
- a pair of sheets having an identical terminal pattern, respectively, the terminal patterns being identical in shape, one of the terminal patterns being formed with a via hole filled with a conductive material for an electrical connection with the other thereof, wherein the sheets are arranged in such a way that when one of the sheets are turned 180° on an imaginary plane parallel thereto the terminal patterns of the sheets are allowed to be overlapped with each other, and the terminal patterns of the sheets are allowed to be electrically connected with each other through the via hole.
- a multilayer type chip inductor having at least one intermediate sheet formed with a conductor pattern thereon, comprising a pair of outermost sheets having a terminal pattern, respectively, wherein each of the terminal patterns includes a via hole for electrically connecting the terminal pattern to the conductor pattern of the intermediate sheet and is capable of providing various positions for the via hole so as to accommodate various conductor patterns of the intermediate sheet.
- FIGs. 2 to 6 a exploded perspective view of a multilayer type chip inductor in accordance with the present invention, respectively.
- a multilayer type chip inductor in accordance with a first preferred embodiment of the present invention includes a pair of sheets 10, 10' made of a ferrite and a dielectric material.
- Each of the sheets 10, 10' has a rectangular shape and a terminal pattern 12 having a substantially "T" shape thereon.
- Each of the terminal patterns 12 has a lateral strip 12a extending along a shorter side of the sheet 10 or 10', and a lengthwise strip 12b extending from a substantially intermediate portion of the length of the lateral strips 12a, along a longer side of the sheet 10 or 10', and terminating at a generally intermediate portion of the length of the sheet 10 or 10'.
- the sheet 10' has at its the lengthwise strip 12b a via hole 14 filled with a conductive material for an electrical connection with the sheet 10.
- the sheets 10, 10' are assembled in such a way that, when one of the sheets 10, 10' are turned 180° on an imaginary plane parallel thereto, the terminal patterns 12 of the sheets 10, 10' are overlapped with each other. This allows the terminal patterns 12 of the sheets 10, 10' to be electrically connected with each other through the via hole 14.
- a multilayer type chip inductor in accordance with a second preferred embodiment of the present invention includes a pair of outermost sheets 20, 20' made of the ferrite and the dielectric material, and at least one intermediate sheets 30 made of the ferrite and the dielectric material and interposed between the outermost sheets 20, 20'.
- Each of the outermost sheets 20, 20' has a rectangular shape and a terminal pattern 22 having a substantially "T" shape thereon. Similar to the terminal pattern 12 accordance with a first preferred embodiment of the present invention, the terminal pattern 22 of each of the outermost sheets 20, 20' has a lateral strip 22a and a lengthwise strip 22b. The outermost sheet 20' has at its the lengthwise strip 22b a via hole 24 filled with a conductive material for an electrical connection with the intermediate sheet 30 therebelow, as will be described in later.
- the intermediate sheets 30 have a conductor pattern 32, respectively.
- the conductor patterns 32 are identical in shape, for example, ⁇ -shape, respectively.
- the conductor pattern 32 of each of the intermediate sheets 30 has a perforated end 32a formed with a via hole 34 and a non-perforated end 32b.
- the via hole 34 is formed by perforating the respective intermediate sheet 30 across the thickness thereof and filled with a conductive material for an electrical connection with neighboring patterns, for example, the terminal pattern of the outermost sheet thereabove and the conductor pattern of the intermediate sheet therebelow, or the conductor patterns of the intermediate sheets thereabove and therebelow.
- the outermost sheets 20, 20' are arranged in such a way that, when one of the outermost sheets 20, 20' is turned 180° on an imaginary plane parallel thereto, the terminal patterns 22 thereof are allowed to be overlapped with each other; and the intermediate sheets 30 are stacked one above the other and sandwiched between the outermost sheets 20, 20' in such a way that, when one of the intermediate sheets 30 is turned 180° on the imaginary plane, the conductor pattern 32 thereof is allowed to be overlapped with the conductor patterns of the neighboring intermediate sheets 30.
- the intermediate sheets 30 are stacked in such a way that their perforated ends 32a and the non-perforated ends 32b are, respectively, contacted with the non-perforated ends 32b and the perforated ends 32a of the neighboring intermediate sheets 30 through the via holes 34. This allows the conductive patterns 32 of the intermediate sheets 30 to be electrically connected with each other.
- the outermost sheet 20 is positioned below the lowermost intermediate sheet 30 in such a way that the lengthwise strip 22b thereof comes into contact with the perforated end 32a of the lowermost intermediate sheet 30 through the via hole 34 of the lowermost intermediate sheet 30, and the outermost sheet 20' is positioned above the uppermost intermediate sheet 30 in such a way that the lengthwise strip 22b thereof comes into contact with the non-perforated end 32b of the uppermost intermediate sheet 30 through the via hole 24 thereof.
- the terminal pattern of the outermost sheet has the substantially "T" shape and the conductor pattern of the intermediate sheet has a ⁇ -shape
- their shapes and/or sizes can be changed depending on the desired inductance.
- the terminal patterns 22 of the outermost sheets 20, 20' may have a rectangular shape.
- the conductor pattern of the intermediate sheet When a different inductance is required, the conductor pattern of the intermediate sheet must also change in the shape and/or the size. Unlike the prior art multilayer type chip inductor, the inventive multilayer type chip inductor can easily accommodate such a change. For example, as shown in Figs. 5 and 6, when the conductor pattern 32 of the intermediate sheet 30 increases in size in order to obtain an increased inductance, the location of the via hole 24 of the terminal pattern 22 can be changed suitably in such a way that the terminal pattern 22 of the outermost sheet 20' is electrically connected with the changed conductor pattern in the inventive multilayer type chip inductor.
- the terminal pattern of the outermost sheet can be electrically connected to various conductor patterns of an intermediate sheet by simply changing the position of the via hole, eliminating the need to change the shape and/or the size of the terminal pattern of the outermost sheet. Furthermore, in the inventive multilayer type chip inductor, since the outermost sheets include an identical terminal pattern in shape, respectively, it is possible to reduce a production cost and to facilitate manufacturing processes thereof.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Coils Or Transformers For Communication (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980031688A KR20000013039A (ko) | 1998-08-04 | 1998-08-04 | 적층형 칩 인덕터 |
KR9831688 | 1998-08-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0978852A1 true EP0978852A1 (fr) | 2000-02-09 |
Family
ID=19546363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99114703A Withdrawn EP0978852A1 (fr) | 1998-08-04 | 1999-07-27 | Inductance de puce multicouche |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0978852A1 (fr) |
KR (1) | KR20000013039A (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR200483483Y1 (ko) * | 2017-02-16 | 2017-05-22 | 정진구 | 바닥 청소기 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2379229A1 (fr) * | 1977-01-26 | 1978-08-25 | Eurofarad | Composants electroniques multi-couches inductifs et leur procede de fabrication |
JPH0669057A (ja) * | 1992-08-19 | 1994-03-11 | Taiyo Yuden Co Ltd | 積層チップインダクタの製造方法 |
JPH0669040A (ja) * | 1992-08-19 | 1994-03-11 | Taiyo Yuden Co Ltd | 積層チップインダクタおよびその製造方法 |
JPH06215947A (ja) * | 1993-01-21 | 1994-08-05 | Hitachi Metals Ltd | 積層インダクタ |
JPH06232004A (ja) * | 1993-01-29 | 1994-08-19 | Murata Mfg Co Ltd | 積層型lcフィルタ |
JPH0963848A (ja) * | 1995-08-29 | 1997-03-07 | Soshin Denki Kk | 積層インダクタ |
JPH09186019A (ja) * | 1995-12-28 | 1997-07-15 | Kawasaki Steel Corp | 積層型磁気素子 |
US5655287A (en) * | 1992-01-31 | 1997-08-12 | Murata Manufacturing Co., Ltd. | Laminated transformer |
-
1998
- 1998-08-04 KR KR1019980031688A patent/KR20000013039A/ko not_active Application Discontinuation
-
1999
- 1999-07-27 EP EP99114703A patent/EP0978852A1/fr not_active Withdrawn
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2379229A1 (fr) * | 1977-01-26 | 1978-08-25 | Eurofarad | Composants electroniques multi-couches inductifs et leur procede de fabrication |
US5655287A (en) * | 1992-01-31 | 1997-08-12 | Murata Manufacturing Co., Ltd. | Laminated transformer |
JPH0669057A (ja) * | 1992-08-19 | 1994-03-11 | Taiyo Yuden Co Ltd | 積層チップインダクタの製造方法 |
JPH0669040A (ja) * | 1992-08-19 | 1994-03-11 | Taiyo Yuden Co Ltd | 積層チップインダクタおよびその製造方法 |
JPH06215947A (ja) * | 1993-01-21 | 1994-08-05 | Hitachi Metals Ltd | 積層インダクタ |
JPH06232004A (ja) * | 1993-01-29 | 1994-08-19 | Murata Mfg Co Ltd | 積層型lcフィルタ |
JPH0963848A (ja) * | 1995-08-29 | 1997-03-07 | Soshin Denki Kk | 積層インダクタ |
JPH09186019A (ja) * | 1995-12-28 | 1997-07-15 | Kawasaki Steel Corp | 積層型磁気素子 |
Non-Patent Citations (5)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 018, no. 311 (E - 1561) 14 June 1994 (1994-06-14) * |
PATENT ABSTRACTS OF JAPAN vol. 018, no. 573 (E - 1624) 2 November 1994 (1994-11-02) * |
PATENT ABSTRACTS OF JAPAN vol. 018, no. 599 (E - 1631) 15 November 1994 (1994-11-15) * |
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 07 31 July 1997 (1997-07-31) * |
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 11 28 November 1997 (1997-11-28) * |
Also Published As
Publication number | Publication date |
---|---|
KR20000013039A (ko) | 2000-03-06 |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB |
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AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: KIM, SANG CHEOL Inventor name: KO, HYUN JONG Inventor name: KIM, JONG DAE Inventor name: YOO, CHAN SEI Inventor name: LIM, WOOK Inventor name: PARK, IN SHIG Inventor name: KANG, NAM KEE |
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17P | Request for examination filed |
Effective date: 20000808 |
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AKX | Designation fees paid |
Free format text: DE FR GB |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
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18W | Application withdrawn |
Withdrawal date: 20021122 |