EP0977404A2 - Commutateur planifié de cellules, à échelle variable, et méthode de commutation - Google Patents

Commutateur planifié de cellules, à échelle variable, et méthode de commutation Download PDF

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Publication number
EP0977404A2
EP0977404A2 EP99306009A EP99306009A EP0977404A2 EP 0977404 A2 EP0977404 A2 EP 0977404A2 EP 99306009 A EP99306009 A EP 99306009A EP 99306009 A EP99306009 A EP 99306009A EP 0977404 A2 EP0977404 A2 EP 0977404A2
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EP
European Patent Office
Prior art keywords
port mechanism
input port
session
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99306009A
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German (de)
English (en)
Other versions
EP0977404A3 (fr
Inventor
Donpaul C. Stephens
Jon C.R. Bennett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marconi Communications Inc
Original Assignee
Fore Systems Inc
Marconi Intellectual Property Ringfence Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fore Systems Inc, Marconi Intellectual Property Ringfence Inc filed Critical Fore Systems Inc
Publication of EP0977404A2 publication Critical patent/EP0977404A2/fr
Publication of EP0977404A3 publication Critical patent/EP0977404A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/106—ATM switching elements using space switching, e.g. crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections

Definitions

  • the present invention is related to a scheduler. More specifically, the present invention is related to the design of a scheduler for a number of outputs in a distributed fashion.
  • ATM is currently viewed as the technology behind future integrated services networks.
  • VCs individual flows
  • ATM switches are primarily constructed as output buffered or shared memory based systems due to the simplicity in making non-blocking devices.
  • Larger scale (10 Gbps) ATM switches are presently constructed using a layered set output buffers, one that accepts traffic at the aggregate rate of the device, another that accepts a slower rate and attempts to divide the bandwidth among a set of ports managed by the controller for this secondary memory.
  • schedulers are used to order when connections are serviced for a given port. These schedulers are generally placed on the aforementioned secondary memory. The schedulers on these secondary memories attempt to provide service guarantees for egress traffic on the ports managed by it. These service guarantees are based largely on the assumption that the main point of contention among egress flows is at the secondary memory. In actuality, only a fraction of the system bandwidth is supplied to the secondary buffering point. This and the fact that multiple ports are commonly associated with these units leads to them often being referenced as multiplexors/demuliplexors in the literature.
  • the physical area, power, cooling, and cost of output buffered switches is well known to be an N 2 problem, i.e., as the number of ports grow, the sum of the input bandwidth for N ports must be able to be buffered at each of N outputs.
  • the cost/performance of memory technology exists as a step function. That is, for a desired amount of bandwidth, the cost remains relatively stable or increases with some rate during some periods with significant jumps in some locations. While increased width may be used to decrease the bandwidth required per-part, the systems are no longer able to pipeline accesses internally.
  • the present invention pertains to a telecommunications switch.
  • the switch comprises a first output port mechanism through which sessions having cells are sent at a total session rate to a network.
  • the switch comprises a first input port mechanism through which sessions are received from the network.
  • the first input port mechanism is connected to the first output port mechanism.
  • the first Input port mechanism has a first guaranteed session rate.
  • the switch comprises a second input port mechanism through which sessions are received from the network.
  • the second input port mechanism is connected to the first output port mechanism.
  • the second input port mechanism has a second guaranteed session rate, the sum of all guaranteed session rates are less than or equal to the total session rate.
  • the switch comprises a first scheduler connected to the first and second input port mechanisms and to the first output port mechanism for scheduling sessions of the input port mechanisms for service.
  • the switch comprises a server for providing service to sessions of the input port mechanisms.
  • the server is connected to the first and second input port mechanisms and the first output port mechanism.
  • the present invention pertains to a method for switching sessions having cells.
  • the method comprises the steps of receiving a first session having cells at a first input port mechanism of a switch. Then there is the step of storing the first session in a first input queue of the first input port mechanism. Next there is the step of receiving a second session at a second input port mechanism of the switch. Then there is the step of storing the second session in a second input queue of the second input port mechanism. Next there is the step of providing service from a server to the first session at a first guaranteed session rate. Then there is the step of transferring cells of the first session to a first output queue of a first output queue mechanism.
  • the present invention pertains to a method for building a scheduler for a large scale switch.
  • this invention describes how to provide bandwidth and delay bounds in a buffered crossbar switch.
  • buffers are maintained internal to the switch for each pair of input-output nodes.
  • a credit is returned to the input that had sent the cell into the switch core.
  • An input may send a cell to any output for which it has a credit.
  • prior art mechanisms have employed these techniques to reduce the complexity of switch design, they were unable to provide bandwidth or delay guarantees.
  • This invention utilizes a scheduled hierarchy within the crossbar switch and at the input nodes to select the order in which cells may pass through the switch core.
  • Separate matrix buffer pairs are maintained at each node for all source nodes within its section for destinations at itself and images in adjoining sections. These buffers enable scheduling decisions to be made with minimal local information, are small enough to fit onchip, and utilize a credit mechanism to denote when buffers are available. Credits are eventually returned to the source section of the nodes (which provide data into the matrix).
  • the source section contains a per connection input queue which buffers all traffic arriving on its input port(s). Cells are scheduled for destination nodes (the output port interface section) within the switch that have buffer credits based on the relative needs of these destination nodes. This enables a very large switch to be constructed that provides per-flow guarantees in a distributed manner. Prior art schedulers are assumed to be output buffered, prior art large scale switches only provide connectivity.
  • Figure 1a is a schematic representation of a switch of the present invention.
  • Figure 1b is a schematic representation of a switch of the present invention.
  • Figure 2 is a schematic representation of a hierarchical distribution regarding the switch.
  • Figure 3 is a schematic representation of credit-flow in the switch.
  • the switch 10 comprises a first output port mechanism 12 through which sessions having cells are sent at a total session rate to a network 36.
  • the switch 10 comprises a first input port mechanism 14 through which sessions are received from the network 36.
  • the first input port mechanism 14 is connected to the first output port mechanism 12.
  • the first input port mechanism 14 has a first guaranteed session rate.
  • the switch 10 comprises a second input port mechanism 16 through which sessions are received from the network 36.
  • the second input port mechanism 16 is connected to the first output port mechanism 12.
  • the second input port mechanism 16 has a second guaranteed session rate, the sum of all guaranteed session rates are less than or equal to the total session rate.
  • the switch 10 comprises a first scheduler 18 connected to the first and second input port mechanisms and to the first output port mechanism 12 for scheduling sessions of the input port mechanisms for service.
  • the switch 10 comprises a server 20 for providing service to sessions of the input port mechanisms.
  • the server 20 is connected to the first and second input port mechanisms and the first output port mechanism 12.
  • the switch 10 includes a flow control mechanism 22 for ensuring cells are not lost after they are received at an input port mechanism and until they are sent out an output port mechanism.
  • the flow control mechanism 22 is connected to the input port mechanisms and the output port mechanism.
  • the switch 10 preferably includes a second output port mechanism 24 connected to the server 20 and the first and second input port mechanisms.
  • the switch 10 includes a second scheduler 26 connected to the first and second input port mechanisms and the second output port mechanism 24 for scheduling sessions of the input port mechanisms for service from the server 20.
  • Each output port mechanism preferably has a virtual time associated with it.
  • the server 20 maintains the virtual time for each output port mechanism.
  • Each input port mechanism preferably assigns a start time and a service interval to each cell that arrives at the respective input port mechanism.
  • the start time is the virtual time when a cell first requests service from the server 20 from the respective input port mechanism and the service interval is the number of the cells that may be read by the server 20 for every cell the server 20 reads from the respective input port mechanism.
  • Each input port mechanism preferably has a finishing time equal to the start time plus the service interval.
  • the server 20 provides service to the input port mechanism having the smallest eligible finishing time.
  • Each input port mechanism preferably comprises an input card 28 which receives cells and an input queue 30 in which cells that are received by the input card 28 are stored, said input queue 30 connected to the input card 28 and the server 20.
  • each output port mechanism includes an output card 32 which sends cells to the network 36 and an output queue 34 in which cells are stored for the output card 32, said output queue 34 connected to the output card 32 and to the server 20.
  • the server 20 preferably reads a cell from the input queue 30 of the first input port mechanism 14 for an output queue 34 of the first output port mechanism 12, and the server 20 causes the finish time of the first input port mechanism 14 to become the start time of the input queue 30 of the first input port mechanism 14.
  • the server 20 compares the start time of a cell that arrives at an empty input queue 30 with the virtual time of the queue the cell is to be transferred to and sets the start time to the virtual time if the start time is less than a virtual time, or sets the start time of the input port mechanism to the virtual time of an output port mechanism which sends a credit to the input port mechanism.
  • the server 20 preferably only resets the start time of an input queue 30 when a cell is stored in an input queue 30 or read out of an input queue 30, or a credit from an output port mechanism is received by an input queue 30.
  • the input card 28 may elect to send a cell to any output port mechanism to which the input card 28 has a credit.
  • the present invention pertains to a method for switching sessions having cells.
  • the method comprises the steps of receiving a first session having cells at a first input port mechanism 14 of a switch 10. Then there is the step of storing the first session in a first input queue 30 of the first input port mechanism 14. Next there is the step of receiving a second session at a second input port mechanism 16 of the switch 10. Then there is the step of storing the second session in a second input queue 30 of the second input port mechanism 16. Next there is the step of providing service from a server 20 to the first session at a first guaranteed session rate. Then there is the step of transferring cells of the first session to a first output queue 34 of a first output queue 34 mechanism.
  • the transferring cells of the first session includes the steps of producing a credit by the output port mechanism which was transferred a cell from the first session; and returning the credit to the first input port mechanism 14 which transferred the cell to the first output port mechanism 12.
  • the receiving the first session step preferably includes the step of assigning a start time to the first input port mechanism 14 equal to the virtual time when the first session first requests service from the server 20, and a service interval to the first input port mechanism 14, where the service interval is the number of cells that may be read by the server 20 for every cell the server 20 reads from the first input port mechanism 14.
  • the assigning step there is the step of determining a finishing time of the first input port mechanism 14 equal to the starting time and the service interval.
  • the receiving the second session step preferably includes the step of determining the finishing time of the second input port mechanism 16.
  • the providing service step there is preferably the step of providing service by the server 20 to the input port mechanism having the smallest eligible finishing time for the second output port mechanism 24 based on a second scheduler 26 associated with the second output port mechanism.
  • the second scheduler 26 is independent and separate from the first scheduler 18.
  • the receiving the first session step preferably includes the step of receiving a second cell at the first input port mechanism 14 while the first cell is in the first input port mechanism 14 without changing the virtual time.
  • the serving the first session step includes the steps of receiving the first cell of the first session at the first input port mechanism 14, comparing the start time of the first input port mechanism 14 with virtual time of the output port mechanism which the first cell is to be sent out of, and setting the start time to the virtual time if the start time is less than virtual time.
  • a switch 10 core of an ATM switch in an ATM network 36 such as that described in [F.M. Chiussi, Y. Xia, and V.P. Kumar. "Backpressure in Shared-Memory-Based ATM Switches under Multiplexed Bursty Sources", In Proceedings of IEEE INFOCOM '96], incorporated by reference herein, may be extended to provide bandwidth guarantees to sessions, such as VCs, passing through it by the application of two overlaid hierarchical fair queuing servers 20. As was shown in [T. Anderson, S. Owicki, J. Saxe, and C. Thacker.
  • the delay bounds of a session in a hierarchical fair queuing server 20 depends on W.I. of the schedulers forming the scheduling tree. While this is described in the context of hierarchical resource allocation at an output node, these principles can be utilized to enable bandwidth guarantees to be made in an input buffered switch 10 as described herein. See figure 2 which shows a hierarchical distribution from an output port mechanism to input port mechanisms which are having sessions passing through them.
  • a hierarchy is constructed comprised of all of the input cards 28 of the input port mechanisms, with their sessions beneath them.
  • the input cards 28 need to be allocated a rate that is at least the sum of the rates of the sessions passing from that input card 28 to the chosen output card 32. So long as the input card 28 is served by the output card 32 at least as fast as its sum of guaranteed session rates, the rates of the sessions may be met.
  • the contention at the input card 28 among output cards 32 can be broken based on the demands of the users, with essentially any contention breaking scheme acceptable. Since an input card 28 may have cells simultaneously offered for multiple output cards 32, multiplexing can occur when an input card 28 schedules a cell for each output. Then, the multicast cell is provided, in turn, to each output card 32 to which it is to be transferred. Output buffering and a small level of speedup is required to insure high throughput under diverse traffic conditions.
  • a crossbar internal to the switch 10 implements the separate scheduler for each output card 32.
  • each input card 28 is assigned to items, a start time, and a service interval.
  • a third item, the finish time of the input queue 30 may be calculated by adding the start time and the service interval.
  • the server 20 maintains a separate output virtual time, V (t), for each output card 32.
  • the service interval is the number of cells that may be read by the server 20 for every cell of the session it reads from the given input queue 30.
  • the server 20 provides service to the cell having the smallest eligible finish time first.
  • the start time, service interval and finish time can be stored in any memory associated with the input queue 30 or at the input port mechanism or at the server 20.
  • a pointer mechanism can be used to link the finish time to the cell to possibly minimize storage usage.
  • the finish time of the input queue 30 is written to the start time location so the start time is reset to the finish line of the cell receiving service from the server 20. If additional cells remain in the input queue 30 from which the cell receiving service by the server 20 is read, the finish time which has been reset to the start time, is the start time for the cell to receive service next in the input queue 30. Otherwise, if there are no additional cells remaining in the input queue 30, the queue is marked as empty and is thus not considered by any of the schedulers of the output port mechanisms. Thus, the start times of the input queues 30 are updated or reset only when a cell is physically stored in the respective input queue 30, or the input queue 30 receives a credit from an output port mechanism which just receives a cell from the input queue 30.
  • the input card 28 selects among all the outputs for which it has credits using the SEFF policy.
  • the start time of an input card 28 may be reset whenever an input card 28 that previously had no cells enqueued in its input queue 30 are to receive an arrival of a cell, or a credit arrives from an output port mechanism where there were no outstanding credits.
  • the flow control mechanism is aware, as is well known in the art, of the service the server and the output port mechanisms can provide.
  • the flow control mechanism reduces the service to the already present input cards 28 so service is available for the new input card 28. In this way, cards can be added (or removed - service is then increased to the remaining input cards 28).
  • the switch 10 may be designed in a pipelined fashion. This may be performed by having multiple successive chips that implement the credit-flow response mechanism where each mode contains a scheduler for each output port mechanism. Scalability is enabled by latency tolerance.
  • the cross bar units for each output port mechanism need not be co-located on a single device, and well known techniques for deciding fault tolerant cross point systems may be used if those aspects are desired.
  • each output port mechanism stands independent and capable of immediate operation, it only requires recognition by the server 20 that there is another output port mechanism which is to receive service.
  • the server 20 can provide service to each of the output port mechanisms in a round robin fashion or any other queuing fashion so that each output port mechanism, which has already determined the cell that is to receive service next, can readily provide the next cell for service when that output port mechanisms turn arrives.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP99306009A 1998-07-30 1999-07-28 Commutateur planifié de cellules, à échelle variable, et méthode de commutation Withdrawn EP0977404A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/126,475 US6345040B1 (en) 1998-07-30 1998-07-30 Scalable scheduled cell switch and method for switching
US126475 1998-07-30

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EP0977404A2 true EP0977404A2 (fr) 2000-02-02
EP0977404A3 EP0977404A3 (fr) 2003-11-19

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US6345040B1 (en) 2002-02-05
JP2000059366A (ja) 2000-02-25

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