EP0964345A3 - Funktion-Entwurfsgerät in einem automatisierten Entwurfssytem für Lsi - Google Patents
Funktion-Entwurfsgerät in einem automatisierten Entwurfssytem für Lsi Download PDFInfo
- Publication number
- EP0964345A3 EP0964345A3 EP99118696A EP99118696A EP0964345A3 EP 0964345 A3 EP0964345 A3 EP 0964345A3 EP 99118696 A EP99118696 A EP 99118696A EP 99118696 A EP99118696 A EP 99118696A EP 0964345 A3 EP0964345 A3 EP 0964345A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- design data
- design
- specializing
- function
- synthesizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22687992 | 1992-08-26 | ||
JP22687992 | 1992-08-26 | ||
JP6162793 | 1993-03-22 | ||
JP6162793 | 1993-03-22 | ||
EP93113694A EP0584828B1 (de) | 1992-08-26 | 1993-08-26 | Automatisiertes LSI-Entwurfsystem und Verfahren |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93113694A Division EP0584828B1 (de) | 1992-08-26 | 1993-08-26 | Automatisiertes LSI-Entwurfsystem und Verfahren |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0964345A2 EP0964345A2 (de) | 1999-12-15 |
EP0964345A3 true EP0964345A3 (de) | 2006-05-03 |
Family
ID=26402675
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93113694A Expired - Lifetime EP0584828B1 (de) | 1992-08-26 | 1993-08-26 | Automatisiertes LSI-Entwurfsystem und Verfahren |
EP99118696A Withdrawn EP0964345A3 (de) | 1992-08-26 | 1993-08-26 | Funktion-Entwurfsgerät in einem automatisierten Entwurfssytem für Lsi |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93113694A Expired - Lifetime EP0584828B1 (de) | 1992-08-26 | 1993-08-26 | Automatisiertes LSI-Entwurfsystem und Verfahren |
Country Status (3)
Country | Link |
---|---|
US (1) | US5754441A (de) |
EP (2) | EP0584828B1 (de) |
DE (1) | DE69331085T2 (de) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69327389T2 (de) * | 1992-10-29 | 2000-06-15 | Altera Corp., San Jose | Verfahren zum Prüfen von Entwürfen für programmierbare Logikschaltungen |
JP2972540B2 (ja) * | 1994-03-24 | 1999-11-08 | 松下電器産業株式会社 | Lsi自動設計システム及びlsi自動設計方法 |
US6120550A (en) * | 1996-10-28 | 2000-09-19 | Altera Corporation | Design file templates for implementation of logic designs |
US6080204A (en) * | 1997-10-27 | 2000-06-27 | Altera Corporation | Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing |
US6430732B1 (en) | 1998-03-27 | 2002-08-06 | Xilinx, Inc. | Method for structured layout in a hardware description language |
US6292925B1 (en) | 1998-03-27 | 2001-09-18 | Xilinx, Inc. | Context-sensitive self implementing modules |
US6237129B1 (en) | 1998-03-27 | 2001-05-22 | Xilinx, Inc. | Method for constraining circuit element positions in structured layouts |
US6243851B1 (en) | 1998-03-27 | 2001-06-05 | Xilinx, Inc. | Heterogeneous method for determining module placement in FPGAs |
US6260182B1 (en) * | 1998-03-27 | 2001-07-10 | Xilinx, Inc. | Method for specifying routing in a logic module by direct module communication |
US6367056B1 (en) | 1998-04-23 | 2002-04-02 | Altera Corporation | Method for incremental timing analysis |
DE10066098B4 (de) * | 1999-07-06 | 2006-03-09 | Fujitsu Ltd., Kawasaki | Halbleiterchip-Entwurfssystem |
JP3974300B2 (ja) * | 1999-11-18 | 2007-09-12 | 松下電器産業株式会社 | Ipベースlsi設計システムおよび設計方法 |
US6904436B1 (en) * | 2000-10-04 | 2005-06-07 | Cypress Semiconductor Corporation | Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy |
DE10138142B4 (de) * | 2001-08-09 | 2006-08-31 | Infineon Technologies Ag | Verfahren zur Analyse einer integrierten elektrischen Schaltung |
US6931573B2 (en) | 2001-08-13 | 2005-08-16 | International Business Machines Corporation | Automated audit methodology for design |
US7024639B2 (en) * | 2002-01-31 | 2006-04-04 | Cadence Design Systems, Inc. | Method and apparatus for specifying encoded sub-networks |
US7076760B2 (en) | 2002-01-31 | 2006-07-11 | Cadence Design Systems, Inc. | Method and apparatus for specifying encoded sub-networks |
US6854097B2 (en) | 2002-01-31 | 2005-02-08 | Cadence Design Systems, Inc. | Method and apparatus for performing technology mapping |
US7383524B2 (en) | 2002-01-31 | 2008-06-03 | Cadence Design Systems, Inc | Structure for storing a plurality of sub-networks |
US6990650B2 (en) | 2002-01-31 | 2006-01-24 | Cadence Design Systems, Inc. | Method and apparatus for performing technology mapping |
US7398503B2 (en) * | 2002-01-31 | 2008-07-08 | Cadence Design Systems, Inc | Method and apparatus for pre-tabulating sub-networks |
JP2004199347A (ja) * | 2002-12-18 | 2004-07-15 | Matsushita Electric Ind Co Ltd | Lsi開発支援システム |
US20050144575A1 (en) * | 2003-03-04 | 2005-06-30 | Fujitsu Limited | Circuit arrangement design method and circuit arrangement design program |
JP2004302932A (ja) * | 2003-03-31 | 2004-10-28 | Fujitsu Ltd | 電子回路設計装置および方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4964056A (en) * | 1987-03-25 | 1990-10-16 | Hitachi, Ltd. | Automatic design system of logic circuit |
WO1992007333A1 (en) * | 1990-10-18 | 1992-04-30 | Hewlett-Packard Company | Logic synthesis |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60114968A (ja) * | 1983-11-28 | 1985-06-21 | Hitachi Ltd | 推論システム |
US4813013A (en) * | 1984-03-01 | 1989-03-14 | The Cadware Group, Ltd. | Schematic diagram generating system using library of general purpose interactively selectable graphic primitives to create special applications icons |
US4635208A (en) * | 1985-01-18 | 1987-01-06 | Hewlett-Packard Company | Computer-aided design of systems |
US4701860A (en) * | 1985-03-07 | 1987-10-20 | Harris Corporation | Integrated circuit architecture formed of parametric macro-cells |
US4918440A (en) * | 1986-11-07 | 1990-04-17 | Furtek Frederick C | Programmable logic cell and array |
US5197016A (en) * | 1988-01-13 | 1993-03-23 | International Chip Corporation | Integrated silicon-software compiler |
US4922432A (en) * | 1988-01-13 | 1990-05-01 | International Chip Corporation | Knowledge based method and apparatus for designing integrated circuits using functional specifications |
US4965741A (en) * | 1988-10-17 | 1990-10-23 | Ncr Corporation | Method for providing an improved human user interface to a knowledge based system |
US5016204A (en) * | 1989-02-28 | 1991-05-14 | Digital Equipment Corporation | Expert system for performing diagnostic and redesign operations incorporating multiple levels of simulation detail |
US5278769A (en) * | 1991-04-12 | 1994-01-11 | Lsi Logic Corporation | Automatic logic model generation from schematic data base |
JP2760682B2 (ja) * | 1991-09-30 | 1998-06-04 | 株式会社東芝 | ハードウェアの設計支援システム |
US5519630A (en) * | 1993-03-22 | 1996-05-21 | Matsushita Electric Industrial Co., Ltd. | LSI automated design system |
-
1993
- 1993-08-26 DE DE69331085T patent/DE69331085T2/de not_active Expired - Fee Related
- 1993-08-26 EP EP93113694A patent/EP0584828B1/de not_active Expired - Lifetime
- 1993-08-26 EP EP99118696A patent/EP0964345A3/de not_active Withdrawn
-
1996
- 1996-07-03 US US08/674,939 patent/US5754441A/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4964056A (en) * | 1987-03-25 | 1990-10-16 | Hitachi, Ltd. | Automatic design system of logic circuit |
WO1992007333A1 (en) * | 1990-10-18 | 1992-04-30 | Hewlett-Packard Company | Logic synthesis |
Non-Patent Citations (2)
Title |
---|
HEKMATPOUR ET AL: "hierarchical modeling of the vlsi design process", IEEE EXPERT, vol. 6, no. 2, April 1991 (1991-04-01), LOS ALAMITOS CA US, pages 56 - 70, XP000243608 * |
LANNEER D ET AL: "An object-oriented framework supporting the full high-level synthesis trajectory", COMPUTER HARDWARE DESCRIPTION LANGUAGES & THEIR APPLICATIONS, 10TH IFIP, 22-24 APRIL, MARSEILLE, FR, AMSTERDAM, NL, 1991, pages 301 - 320, XP002114731 * |
Also Published As
Publication number | Publication date |
---|---|
EP0584828A2 (de) | 1994-03-02 |
EP0964345A2 (de) | 1999-12-15 |
EP0584828B1 (de) | 2001-11-07 |
EP0584828A3 (de) | 1995-05-10 |
DE69331085T2 (de) | 2002-03-14 |
US5754441A (en) | 1998-05-19 |
DE69331085D1 (de) | 2001-12-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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17P | Request for examination filed |
Effective date: 19990922 |
|
AC | Divisional application: reference to earlier application |
Ref document number: 584828 Country of ref document: EP |
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AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LI LU MC NL PT SE |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: TSUBATA, SHINTARO Inventor name: NISHIYAMA, TAMOTSU Inventor name: TOKUNOH, SEIJ |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
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AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LI LU MC NL PT SE |
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AKX | Designation fees paid |
Designated state(s): DE FR GB NL |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 20061104 |