EP0780908B1 - Transistor à effet de champ à grille isolée et à canal diffusé - Google Patents

Transistor à effet de champ à grille isolée et à canal diffusé Download PDF

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Publication number
EP0780908B1
EP0780908B1 EP96410124A EP96410124A EP0780908B1 EP 0780908 B1 EP0780908 B1 EP 0780908B1 EP 96410124 A EP96410124 A EP 96410124A EP 96410124 A EP96410124 A EP 96410124A EP 0780908 B1 EP0780908 B1 EP 0780908B1
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EP
European Patent Office
Prior art keywords
dopant
region
gate electrode
anneal
dmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP96410124A
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German (de)
English (en)
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EP0780908A1 (fr
Inventor
Jean Jimenez
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STMicroelectronics SA
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STMicroelectronics SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Definitions

  • the present invention relates to the manufacture of semiconductor integrated circuits, in particular to the manufacture of integrated circuits including diffused channel insulated gate field effect (DMOS) transistors.
  • DMOS diffused channel insulated gate field effect
  • CMOS complementary metal-oxide-semiconductor
  • Figures 1A to 1D show steps in the manufacture of one cell of a vertical DMOS transistor according to the prior art.
  • a first step begins with a highly n doped semiconductor layer 10 covered with a lightly doped n type layer 12 on its upper surface.
  • Layer 12 is generally an epitaxied layer.
  • the highly n doped region 10 may be a substrate or a buried layer within a p type substrate.
  • a gate insulator region 14 and a gate electrode 16 are formed on the upper surface of the epitaxied layer 12.
  • a p type body region 18 is introduced on both sides of the gate electrode 16. Typically, this region is formed by photolithographic masking followed by a p type implantation and a first thermal anneal step, at a very high temperature and over a long period of time. Subsequent to the thermal anneal step, each body region 18 extends under the gate electrode by a distance d.
  • highly n doped source regions 20 and highly p doped body contact regions 22 are introduced into the body regions 18, adjacent to each end of the gate electrode 16.
  • these regions 20, 22 are introduced by photolithographic masking followed by ion implantation and a second thermal anneal step. This second anneal step is performed for a shorter time and at a lower temperature than the first anneal step.
  • the length L of the body region remaining at the upper surface of the epitaxied layer 12 is the channel length of the DMOS transistor.
  • the highly doped layer 10 corresponds to the drain region of the DMOS transistor.
  • the process continues in a known manner, with the formation of interconnect layers, and contacts to gate, source, body and drain. Electrical contact to the drain region 10 is made either by a metallisation of the lower surface of drain region 10 when the drain region is a substrate, or at the upper surface of an n type well contacting the drain region 10, when this is a buried layer.
  • the formation of the p body region is typically done by implanting boron ions at an energy of 25 to 35keV and an intensity of 2x10 13 to 4x10 13 atoms.cm -2 .
  • a severe thermal anneal step is then required to achieve a sufficient distance d of diffusion of this p body implant under the gate electrode.
  • a thermal anneal step may typically involve heating the circuit to 1160°C for a period of 1 to 2 hours.
  • Use of a dopant with a lower diffusion coefficient would require even more severe diffusion conditions, or may not even be possible.
  • a horizontal DMOS structure may be formed where the p body dopant is introduced on only one side of the gate electrode 16. A highly n doped drain contact region is then introduced on the other side of the gate electrode.
  • DMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • bipolar circuitry is required for treating analogue signals, CMOS transistors for control logic circuitry, and DMOS transistors for a high power interface to control the disc drive motors.
  • CMOS transistors are incompatible with known processes for producing CMOS integrated circuits having transistor gate lengths of approximately 1,5 ⁇ m or less.
  • a threshold adjust region must be included under the gates of CMOS transistors to achieve a desired threshold voltage. Subjecting such a transistor to a severe anneal step as described above would suppress the threshold adjust region by diffusion effects, and the threshold voltages would no longer be controllable.
  • the severe first thermal anneal step described above would weaken the gate insulator layer, and reduce its breakdown voltage to an unacceptable level.
  • the severe thermal anneal step cannot simply be eliminated, as the high doping density of the source region 20 compared to the p body region 18, would preclude the choice of a pair of dopants allowing an optimised channel region to be formed.
  • An object of the present invention is to provide a method of fabricating DMOS transistors which are suitable for inclusion in manufacturing processes for CMOS integrated circuits with a transistor gate length of 1,5 ⁇ m and less.
  • a second object of the present invention is to provide such a process which does not require a high temperature, long duration anneal step.
  • a third object of the present invention is to provide such a method which introduces as few new steps as possible into the manufacturing process for CMOS integrated circuits.
  • the invention also provides a method of manufacture of a diffused channel insulated gate field effect transistor, as claimed in claim 1.
  • FIGS 2A to 2D illustrate a preferred process for the manufacture of DMOS transistors in integrated circuits containing both DMOS and CMOS transistors, according to the present invention.
  • Features common with those shown in figures 1A to 1D carry identical reference labels.
  • a highly n doped semiconductor layer 10 is provided with a lightly n doped epitaxial layer 12, a gate insulator layer 14 and gate electrode 16 as described with reference to figures 1A and 1B.
  • the device shown in figure 2A is created through the performance of a number of manufacturing steps.
  • the semiconductor layer 10 is covered with the lightly doped n type layer on its upper surface.
  • layer 12 is an epitaxied layer.
  • the gate insulator layer 14 and the gate electrode 16 are formed on the upper surface of layer 12.
  • P type body implants 24 are formed adjacent to both ends of the gate electrode 16.
  • no thermal anneal step is applied. Accordingly, the p type dopant does not diffuse into the semiconductor, neither vertically nor under the gate electrode.
  • Figure 2B shows the structure at a later step in the process of the present invention.
  • a light n type implant 26 has been formed in the same regions as the p body implants 24. No anneal is performed at this stage, so this implant also does not diffuse into the semiconductor.
  • spacers 28 are produced adjacent to each end of the gate electrode. Spacers 28 may correspond to those currently used in the manufacturing of CMOS transistors.
  • spacers such as spacers 28 allow the formation of lightly doped drain (LDD) regions between highly doped source and drain regions and the channel region. Without these LDD regions, the peak of the electric field would be at the edge of the drain region, just under the gate electrode 16. Such high electric fields could cause hot carrier injection into the gate insulation layer 14 and gate electrode 16.
  • LDD regions displace the point of maximum field strength to a location under the spacers 28, so that no damage to the gate insulation layer 14 can occur.
  • Vertical DMOS transistors do not experience the problem of hot carrier injection. The presence of spacers does not appear to bring similar advantages to these structures. Accordingly, the step for forming spacers 28 is not performed in conventional DMOS manufacturing processes.
  • the highly n doped source regions 30 are formed, along with highly p doped body contact regions 32.
  • the DMOS channel region is formed.
  • the DMOS channel region is not defined by the difference between a p type diffusion 18 and a highly doped n type diffusion 20 as in conventional devices. Instead, the DMOS channel region is defined by the difference between a p type diffusion 24 and an intermediately doped n diffusion 26. It is this arrangement which makes possible the realisation of the DMOS channel in a single thermal anneal step.
  • the dopant which forms the p body region 24 is boron, implanted at an energy of 40keV, at a dose of 4x10 13 atoms.cm -2 .
  • the dopant which forms the lightly doped n regions 26 is preferably arsenic implanted at an energy of 40keV, at a dose of 3x10 13 atoms.cm -2 .
  • This light n implant is preferably the same as that used to produce lightly doped drain (LDD) regions in n channel MOS transistors of the integrated circuit.
  • the dopant which forms the highly n doped source regions 30 is preferably arsenic, implanted at an energy of 40keV, at a dose of 4x10 15 atoms.cm -2 .
  • This n type implant is preferably the same as that used to produce drain and source regions in n channel MOS transistors of the integrated circuit.
  • the p body contact regions 32 are also doped with boron. However, to ensure that they have a depth after the thermal anneal step less than that of the p body 24, an implant species such as BF 2 is preferably used, which penetrates less deeply into the semiconductor than boron, and so produces a shallower region after anneal. This same dopant implant may be used to produce source and drain regions for p channel MOS transistors.
  • the structure may be heated to 980°C for 30 minutes, which corresponds to normal conditions for CMOS circuit manufacture.
  • This allows the production of a 0.25 ⁇ m channel length, and the following diffusion profiles: Cs (atoms.cm -3 ) xj ( ⁇ m) p body 24 2x10 18 0.5 lightly doped n 26 4x10 18 0.15 n source 30 3x10 20 0.25 p body contact 32 1x10 20 0.5 where Cs represents a surface concentration, and xj a corresponding junction depth of a particular region.
  • the dimensions of the DMOS transistor should be fixed to withstand a voltage of 20V, both to withstand voltage peaks caused by the inductance of the motor, and to allow for variation of the breakdown voltage with temperature.
  • This may be achieved with the vertical DMOS structure of figure 2D, having a 2.5 ⁇ m long gate electrode 16, a 3 ⁇ m thick epitaxial layer 12, with a resistivity of 1 ⁇ .cm.
  • Such a structure could have a breakdown voltage as high as 35V. Lower resistivity and greater thickness of the epitaxial layer 12 would give a higher breakdown voltage.
  • a DMOS transistor is provided that may be incorporated into a standard CMOS logic or bipolar circuit manufacturing process, with only the addition of a single p body region implant.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Claims (5)

  1. Procédé de fabrication d'un transistor à effet de champ à grille isolée à canal diffusé comprenant les étapes suivantes :
    prévoir un substrat semiconducteur (10, 12) d'un premier type de conductivité ayant une surface supérieure ;
    définir une couche d'isolement de grille (14) et une électrode de grille (16) sur la surface supérieure du substrat ;
    implanter un premier dopant (24) d'un second type de conductivité dans une première région du substrat, au voisinage d'une première extrémité de l'électrode de grille, et ne pas suivre cette implantation d'un recuit ;
    implanter un deuxième dopant (26) du premier type de conductivité à faible dose dans la première région du substrat ;
    former des espaceurs (28) au voisinage d'au moins la première extrémité de la grille ;
    implanter un troisième dopant (30), de source, du premier type de conductivité à haut niveau de dopage dans une partie de la première région adjacente à l'espaceur (28) ;
    procéder à un recuit thermique,
    dans lequel le premier dopant est choisi pour diffuser plus vite lors de l'étape de recuit que les deuxième et troisième dopants.
  2. Procédé selon la revendication 1, dans lequel le recuit thermique est réalisé à une température inférieure à 1000°C.
  3. Procédé selon la revendication 2, caractérisé en ce que le recuit est effectué pendant une durée de l'ordre de 30 minutes.
  4. Procédé selon la revendication 3, caractérisé en ce qu'il comprend en outre l'étape consistant à :
    implanter un quatrième dopant (32) du deuxième type de conductivité dans des deuxièmes régions du substrat aux endroits où l'on souhaite réaliser des contacts de caisson et en ce que cette implantation est réalisée de sorte que, après recuit, la profondeur de diffusion du quatrième dopant soit inférieure à celle du premier dopant.
  5. Procédé selon la revendication 4, caractérisé en ce que le premier dopant est du bore, les deuxième et troisième dopants sont de l'arsenic, et le quatrième dopant est du bore implanté sous forme de fluorure de bore.
EP96410124A 1995-12-18 1996-12-17 Transistor à effet de champ à grille isolée et à canal diffusé Expired - Lifetime EP0780908B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9515446A FR2742583B1 (fr) 1995-12-18 1995-12-18 Transistor a effet de champ a grille isolee et a canal diffuse
FR9515446 1995-12-18

Publications (2)

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EP0780908A1 EP0780908A1 (fr) 1997-06-25
EP0780908B1 true EP0780908B1 (fr) 2002-02-27

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EP96410124A Expired - Lifetime EP0780908B1 (fr) 1995-12-18 1996-12-17 Transistor à effet de champ à grille isolée et à canal diffusé

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US (1) US5801078A (fr)
EP (1) EP0780908B1 (fr)
DE (1) DE69619487T2 (fr)
FR (1) FR2742583B1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035678A (zh) * 2012-06-08 2013-04-10 上海华虹Nec电子有限公司 Rf ldmos器件及制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6455385B1 (en) * 1998-01-07 2002-09-24 Advanced Micro Devices, Inc. Semiconductor fabrication with multiple low dose implant
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
US20090159896A1 (en) * 2007-12-20 2009-06-25 General Electric Company Silicon carbide mosfet devices and methods of making
DE102008046734A1 (de) * 2008-09-11 2010-03-18 Osram Gesellschaft mit beschränkter Haftung Verfahren und Schaltungsanordnung zur Erhöhung der Spannungsfestigkeit von Metalloxidtransistoren bei niedrigen Temperaturen
KR101578931B1 (ko) * 2008-12-05 2015-12-21 주식회사 동부하이텍 반도체 소자 및 반도체 소자의 제조 방법
CN102664161B (zh) * 2012-05-25 2016-11-16 杭州士兰集成电路有限公司 高压bcd工艺中高压器件的隔离结构及其制造方法
CN113113487A (zh) * 2020-01-13 2021-07-13 张清纯 半导体器件及其制备方法

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DE3016749A1 (de) * 1980-04-30 1981-11-05 Siemens AG, 1000 Berlin und 8000 München Kontakt fuer mis-halbleiterbauelement und verfahren zu seiner herstellung
GB2150348A (en) * 1983-11-29 1985-06-26 Philips Electronic Associated Insulated-gate field-effect transistors and their manufacture
JP2700025B2 (ja) * 1985-12-24 1998-01-19 富士電機株式会社 バイポーラたて形ｍｏｓｆｅｔ
JPS6384164A (ja) * 1986-09-29 1988-04-14 Nissan Motor Co Ltd 縦形ｍｏｓｆｅｔ
JPH0687504B2 (ja) * 1988-04-05 1994-11-02 株式会社東芝 半導体装置
US5187117A (en) * 1991-03-04 1993-02-16 Ixys Corporation Single diffusion process for fabricating semiconductor devices
US5182222A (en) * 1991-06-26 1993-01-26 Texas Instruments Incorporated Process for manufacturing a DMOS transistor
US5178370A (en) * 1991-08-05 1993-01-12 Motorola Inc. Conductivity modulated insulated gate semiconductor device
EP0658940A1 (fr) * 1993-11-23 1995-06-21 Siemens Aktiengesellschaft Elément semi-conducteur commandé par effet de champ
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035678A (zh) * 2012-06-08 2013-04-10 上海华虹Nec电子有限公司 Rf ldmos器件及制造方法
CN103035678B (zh) * 2012-06-08 2015-04-08 上海华虹宏力半导体制造有限公司 Rf ldmos器件及制造方法

Also Published As

Publication number Publication date
DE69619487D1 (de) 2002-04-04
DE69619487T2 (de) 2002-10-10
US5801078A (en) 1998-09-01
FR2742583A1 (fr) 1997-06-20
EP0780908A1 (fr) 1997-06-25
FR2742583B1 (fr) 1998-04-24

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