EP0735459B1 - Architecture de processeur flou - Google Patents

Architecture de processeur flou Download PDF

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Publication number
EP0735459B1
EP0735459B1 EP95830117A EP95830117A EP0735459B1 EP 0735459 B1 EP0735459 B1 EP 0735459B1 EP 95830117 A EP95830117 A EP 95830117A EP 95830117 A EP95830117 A EP 95830117A EP 0735459 B1 EP0735459 B1 EP 0735459B1
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EP
European Patent Office
Prior art keywords
fuzzy
memory
internal
processor according
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95830117A
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German (de)
English (en)
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EP0735459A1 (fr
Inventor
Biagio Giacalone
Francesco Pappalardo
Enrico Pelos
Vincenzo Catania
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
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Priority to DE69531772T priority Critical patent/DE69531772D1/de
Priority to EP95830117A priority patent/EP0735459B1/fr
Priority to JP8074074A priority patent/JPH08286921A/ja
Priority to US08/623,617 priority patent/US6385598B1/en
Publication of EP0735459A1 publication Critical patent/EP0735459A1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/02—Computing arrangements based on specific mathematical models using fuzzy logic
    • G06N7/04—Physical realisation

Definitions

  • the present invention relates to a fuzzy processor with improved architecture.
  • fuzzy processors there are various kinds of fuzzy processors.
  • An example of a classic fuzzy processor is the MB94110 processor by Fujitsu, comprising a block that performs fuzzy instructions.
  • Another example is the SAE81C99 processor by Siemens, which can also load various knowledge bases from an external memory, although this is not possible conditionally or concurrently with normal fuzzy processing.
  • known fuzzy processors only process fuzzy instructions and cannot integrate fuzzy control with the processing of classic instructions such as shift, rotate, compare, or arithmetic/logic instructions, and also have no signals such as interrupt, stack, etcetera. Accordingly, it is not possible to perform any kind of arithmetic/logic processing on the inputs and on the outputs of the fuzzy controller.
  • All known fuzzy control units furthermore perform control by processing the fuzzy instructions sequentially, with no possibility of jumping from one instruction to another.
  • fuzzy processors process a fixed number of inputs and of fuzzy rules. A certain number of membership functions is associated with each fuzzy input, and the set of these functions is termed knowledge base. Both the set of fuzzy rules and the knowledge base remain unchanged throughout processing.
  • fuzzy inference and fuzzy inference processor discloses a fuzzy processor comprising a fuzzy rule processor with an arithmetic-logic unit, and a control unit adapted to execute non-fuzzy instructions.
  • the aim of the present invention is to provide a fuzzy processor with improved architecture that is more versatile than known fuzzy processors.
  • an object of the present invention is to provide a fuzzy .processor with improved architecture that is capable of handling inputs and outputs.
  • Another object of the present invention is to provide a fuzzy processor with improved architecture capable of loading various knowledge bases or sets of fuzzy rules from outside during normal operation.
  • Another object of the present invention is to provide a fuzzy processor with improved architecture capable of changing the knowledge base or the set of fuzzy rules to be processed during normal processing, conditionally or unconditionally, the conditions occurring on the inputs or on the outputs.
  • Another object of the present invention is to provide a fuzzy processor with improved architecture capable of performing arithmetic/logic processing of the inputs and outputs of the fuzzy controller, of processing non-fuzzy instructions, and of handling interrupt signals.
  • Another object of the present invention is to provide a fuzzy processor with improved architecture capable of performing conditional or unconditional jumps within fuzzy instructions.
  • Another object of the present invention is to provide a processor that is highly reliable, relatively easy to manufacture, and at competitive costs.
  • fuzzy processors Since known fuzzy processors only process fuzzy instructions and cannot integrate fuzzy control with the processing of classic instructions such as shift, rotate, compare, or of arithmetic-logic instructions, and also have no signals such as interrupt, stack, etcetera.
  • the fuzzy processor according to the present invention is provided with an arithmetic/logic unit (ALU), with a direct memory access control unit (DMA), with a timer, with an interrupt handler, with interfaces for the buses, and other components.
  • the fuzzy instructions are integrated with non-fuzzy instructions, such as arithmetic/logic instructions, shift, rotate, etcetera, according to a definable hierarchy, that is to say, all the instructions that also allow non-fuzzy processing of input and/or output data.
  • the fuzzy control unit according to the present invention can use internal registers of the chip as inputs of the fuzzy section and can also use them as buffer registers for the output of the fuzzy section, and preprocessings on the inputs and postprocessings on the outputs can be performed in these registers.
  • adders, subtracters, multipliers, and dividers are already present in the classic architecture of a fuzzy control unit and are used for fuzzification and defuzzification, the present invention proposes the concept of arithmetic/logic processing of the inputs and of the outputs, the execution of non-fuzzy instructions, and the handling of interrupt signals; these functions can be performed by using appropriately modified existing blocks or specifically designed circuitry. In particular, input and output processing can be performed almost entirely by existing blocks.
  • interrupt control By means of the interrupt signals it is possible, if required, to interrupt control to perform emergency, control, or system management operations by means of non-fuzzy instructions.
  • fuzzy control units perform control by processing the fuzzy instructions sequentially, without being able to jump from one fuzzy instruction to another.
  • the fuzzy processor proposes the insertion, among fuzzy rules, of the conditional or unconditional jump instructions, in which the optional condition will have to occur on the inputs or on the outputs.
  • fuzzy control units process a fixed number of inputs and of fuzzy rules. A certain number of membership functions is associated with each input.
  • the set of membership functions is termed knowledge base. Both the set of rules and the knowledge base are invariant throughout processing.
  • the processor according to the present invention is able to change the knowledge base and/or the set of fuzzy rules during normal processing. This is performed by means of a buffer memory, where the next knowledge base and/or set of fuzzy rules to be processed is loaded during normal operation, so that the base or set can be swapped by virtue of an instruction for conditional or unconditional swapping of the rule set or of the knowledge base.
  • the conditions can be imposed on the inputs or on the outputs.
  • the characteristics that are innovative with respect to known fuzzy processors are the possibility of loading from outside the fuzzy rule memory and the knowledge base memory (the membership functions) concurrently (and transparently) with respect to instruction processing; the possibility of processing both fuzzy rules and non-fuzzy instructions (shift, rotate, arithmetic/logic operations, etcetera); the possibility of conditional or unconditional jumps within the set of fuzzy rules that is being processed; and finally, the possibility of conditionally or unconditionally swapping the knowledge base or the set of rules to be processed.
  • the reference numeral 1 designates the classic fuzzy rule processor, which executes fuzzy rules.
  • An arithmetic/logic unit (ALU) 2 has been included in the processor according to the present invention to perform the arithmetic/logic processing of the inputs and of the outputs.
  • a control unit 3 is furthermore connected to the ALU 2 and is adapted to perform non-fuzzy instructions.
  • An interrupt handler 4 is located inside the control unit 3.
  • the control unit 3 is furthermore connected directly to the fuzzy rule processor 1.
  • control unit 3 and the ALU 2 are connected to internal registers 17, which are in turn connected to a data memory 18 that acts as a buffer for the internal registers 17.
  • the control unit 3 is also connected to the data memory 18.
  • the internal registers 17, the data memory 18, the ALU 2, and the fuzzy rule processor 1 are connected to a data bus 19.
  • the data bus 19 is connected to the ALU 2 by means of two lines, a direct one and a line that passes through a multiplexer 20 which performs a selection so that the second input of the ALU 2 arrives from the data bus or from the control unit 3.
  • An external control line IF/MC 21 is connected to the control unit 3 and sends a signal externally if the processor is executing fuzzy or non-fuzzy instructions.
  • a conventional timer 22 is furthermore connected to the control unit 3 and has its own output line 23.
  • the interrupt signals are sent to the control unit 3 and to the interrupt handler 4 located therein by means of an interrupt line 24.
  • the reset signals are sent to the control unit by means of a reset line 25.
  • the clock signal is sent to the control unit 3 by means of a clock line 26.
  • a data input control unit 27 is furthermore connected to the data bus 19 and to the control unit 3.
  • the control unit 27 is connected to the outside by means of a handshake line 28, an input data line 29, and an input number selection line 30 for selecting an input among the multiple available inputs.
  • a data output control unit 31 is furthermore likewise connected to the data bus 19 and to the control unit 3. Said control unit is connected to the outside by means of a handshake line 32, an output data line 33, and an output number selection line 34 for externally indicating which among the plurality of available outputs is on the output data line 33.
  • the processor according to the present invention is furthermore provided with an internal RAM memory 5 directly connected to the fuzzy rule processor 1 and to the control unit 3.
  • the RAM memory 5 furthermore internally comprises, besides other components, a microcode memory (MCM) 6.
  • MCM microcode memory
  • Said microcode memory 6 stores all the non-fuzzy instructions and is directly connected to the control unit 3, so that said instructions are executed by said control unit.
  • the internal RAM memory 5 furthermore includes a fuzzy instruction memory 7 (IFM) that is conveniently divided into two parts, IFM 1 and IFM2.
  • FIM fuzzy instruction memory 7
  • Said fuzzy instruction memory 7 comprises all the fuzzy instructions that must be executed by the fuzzy rule processor 1 to which the memory 7 is directly connected.
  • the internal RAM memory 5 furthermore comprises a knowledge base memory 8 that is conveniently divided into two parts ADM1 and AMD2 (Antecedent Data Memory) and is directly connected to the fuzzy rule processor 1.
  • An external memory 9 is furthermore associated with the processor according to the present invention and can advantageously be an internal one; it comprises an external knowledge base memory 10, an external fuzzy rule memory 11, and an external microcode memory 12.
  • the external knowledge base memory 10 is divided into multiple banks, each of which contains a knowledge base, from bank 1 to bank i, and the external fuzzy rule memory 11 is also divided into multiple banks, each bank containing a different set of rules, from bank 1 to bank n.
  • the external memory 9, with its respective internal memories 10, 11, and 12, is connected to the internal RAM memory 5 by means of a direct memory access control unit (DMA) 13 and a demultiplexer 14.
  • the memories 10, 11, and 12 are connected to the DMA 13 by means of a data line 15, whereas the DMA 13 is connected to the external memory by means of a memory address line 16.
  • DMA direct memory access control unit
  • the DMA allows us to load knowledge bases and sets of fuzzy instructions in the corresponding buffer memories concurrently with normal processing.
  • the arithmetic/logic unit 2 performs the arithmetic/logic processing, whereas the non-fuzzy instructions are performed by the control unit 3.
  • the non-fuzzy instructions reside in the microcode memory 6 and are performed directly by the control unit 3, whereas the fuzzy rules are stored in the fuzzy instruction memory 7, and the task of processing the fuzzy rules is assigned to the fuzzy rule processor 1.
  • the control unit 3 can order the execution of a certain number n of fuzzy instructions processed by the fuzzy processor 1 and then resume control.
  • Interrupts are requested by means of the interrupt line 24 and performed by the interrupt handler 4 located inside the control unit 3.
  • the non-fuzzy instructions also include the instruction ordering processing of the fuzzy instructions in a continuous cycle (as in classic fuzzy control units) and can be interrupted only by an intervening interrupt.
  • the fuzzy rules can process the inputs taken directly from the outside by means of the data input control unit 27 or the inputs residing in the internal registers 17, which in this case may have been preprocessed by the control unit 3.
  • the outputs of the fuzzy rule processor 1 can furthermore be sent immediately outside by means of the data output control unit 31 or placed in the internal registers 17, so that they can be postprocessed by the control unit 3 before being sent outside the processor.
  • a jump instruction has been inserted among the fuzzy instructions contained in the fuzzy instruction memory 7; as an alternative, this can be done by means of the fuzzy control unit.
  • the possibility of changing the knowledge base or the set of fuzzy rules to be processed during normal processing is provided by means of the DMA 13, which transparently loads from the external memory 9 the new knowledge base and/or the set of rules to be processed.
  • the internal knowledge base memory 8 and the internal fuzzy instruction memory 7 inside the internal RAM memory 5 are duplicated in memories ADM1-ADM2 and IFM1-IFM2 respectively, since while the fuzzy rule processor 1 processes rules residing in one of the fuzzy instruction memories IFM by using the knowledge base that resides in a knowledge base memory ADM, the DMA 13 can load the other memories (by taking the data from the external memory 9), and therefore the instruction for swapping the knowledge base or the set of fuzzy rules to be processed simply swaps the internal memories to be processed.
  • This last instruction can be conditional or unconditional, and the conditions to be verified may occur on the inputs and on the outputs of the fuzzy rule processor 1 or also on the non-fuzzy processing value.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Molecular Biology (AREA)
  • Fuzzy Systems (AREA)
  • Biomedical Technology (AREA)
  • Algebra (AREA)
  • Artificial Intelligence (AREA)
  • Health & Medical Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • General Health & Medical Sciences (AREA)
  • Automation & Control Theory (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
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Claims (12)

  1. Processeur en logique floue comprenant un processeur de règle floue (1), une mémoire interne (5) comprenant une mémoire d'instructions floues (7) et une mémoire interne de base de connaissance (8), un module arithmétique et logique (2), un module de commande (3) adapté à exécuter des instructions non floues qui sont typiques de microprocesseurs classiques et d'instructions floues, caractérisé en ce que la mémoire interne (5) comprend en outre une mémoire interne de microcode (6) pour mémoriser des instructions non floues, et en ce qu'il comprend en outre une mémoire externe (9) comprenant une mémoire externe de base de connaissance (10), une mémoire externe d'instructions floues (11) et une mémoire externe d'instructions non floues (12), le module de commande comprenant un accès direct en mémoire et étant adapté à basculer de façon transparente des données entre les mémoire externes (10, 11, 12) et les mémoires internes (6, 7, 8).
  2. Processeur en logique floue selon la revendication 1, caractérisé en ce que le module de commande (3) comprend de façon interne un dispositif de traitement d'interruption (4).
  3. Processeur en logique floue selon la revendication 1, caractérisé en ce que la mémoire interne de base de connaissance (8) et la mémoire interne d'instructions floues (7) sont toutes deux composées de première et seconde parties (ADM1, ADM2 ; IFM1, IFM2).
  4. Processeur en logique floue selon la revendication 1, caractérisé en ce qu'il comprend des registres internes (17) associés au module de commande (3) et au module arithmétique et logique (2).
  5. Processeur en logique floue selon la revendication 4, caractérisé en ce qu'il comprend une mémoire de données (18) associée aux registres internes (17).
  6. Processeur en logique floue selon la revendication 1, caractérisé en ce qu'il comprend un module d'entrée de données (27) et un module de sortie de données (31).
  7. Processeur en logique floue selon la revendication 1, caractérisé en ce que la mémoire interne d'instructions floues (7) contient au moins une instruction de saut.
  8. Processeur en logique floue selon la revendication 7, caractérisé en ce que ladite au moins une instruction de saut est une instruction de saut conditionnel.
  9. Processeur en logique floue selon la revendication 1, caractérisé en ce qu'il comprend une horloge associée au module de commande (3).
  10. Processeur en logique floue selon une ou plusieurs des revendications précédentes, caractérisé en ce qu'il comprend un bus de données (19) connecté au module de commande (3), au processeur de règle floue (1), au module arithmétique et logique (2), au module d'entrée de données (27), au module de sortie de données (31) et aux registres internes (17).
  11. Processeur en logique floue selon une ou plusieurs des revendications précédentes, caractérisé en ce qu'il traite un nombre illimité d'entrées et/ou de règles floues et/ou réalise une commande en temps partagé de plusieurs processus et/ou une commande adaptative.
  12. Processeur selon la revendication 7, caractérisé en ce que ladite au moins une instruction de saut est une instruction de saut non conditionnel.
EP95830117A 1995-03-30 1995-03-30 Architecture de processeur flou Expired - Lifetime EP0735459B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE69531772T DE69531772D1 (de) 1995-03-30 1995-03-30 Fuzzy-Prozessor-Architektur
EP95830117A EP0735459B1 (fr) 1995-03-30 1995-03-30 Architecture de processeur flou
JP8074074A JPH08286921A (ja) 1995-03-30 1996-03-28 ファジィプロセッサおよびファジィ論理処理を行なう方法
US08/623,617 US6385598B1 (en) 1995-03-30 1996-03-29 Fuzzy processor with architecture for non-fuzzy processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830117A EP0735459B1 (fr) 1995-03-30 1995-03-30 Architecture de processeur flou

Publications (2)

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EP0735459A1 EP0735459A1 (fr) 1996-10-02
EP0735459B1 true EP0735459B1 (fr) 2003-09-17

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EP (1) EP0735459B1 (fr)
JP (1) JPH08286921A (fr)
DE (1) DE69531772D1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1310756B1 (it) * 1999-11-30 2002-02-22 St Microelectronics Srl Circuito del calcolo delle operazioni logiche di unione edintersezione fuzzy.
US7185192B1 (en) * 2000-07-07 2007-02-27 Emc Corporation Methods and apparatus for controlling access to a resource
EP1352496A2 (fr) * 2000-10-26 2003-10-15 General Instrument Corporation Previsualisation gratuite initiale destinee a un contenu multimedia multidiffusion
US9542651B2 (en) 2014-01-23 2017-01-10 Healthtrust Purchasing Group, Lp Fuzzy inference deduction using rules and hierarchy-based item assignments

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261036A (en) * 1989-10-24 1993-11-09 Mitsubishi Denki K.K. Programmable controller with fuzzy control function, fuzzy control process and fuzzy control monitoring process
US5305424A (en) * 1990-07-26 1994-04-19 Apt Instruments (N.A.) Inc. Data forming method for a multi-stage fuzzy processing system
EP0516161A3 (en) * 1991-05-31 1993-10-13 Kabushiki Kaisha Toshiba Fuzzy rule-based system formed in a chip
US5285376A (en) * 1991-10-24 1994-02-08 Allen-Bradley Company, Inc. Fuzzy logic ladder diagram program for a machine or process controller
US5263125A (en) * 1992-06-17 1993-11-16 Motorola, Inc. Circuit and method for evaluating fuzzy logic rules
US5430828A (en) * 1992-06-26 1995-07-04 Matsushita Electric Industrial Co., Ltd. Arithmetic and logic unit, storage unit and computer system for fuzzy set processing
US5524174A (en) * 1993-04-14 1996-06-04 Siemens Aktiengesellschaft Apparatus for inference formation and defuzzification in a high-definition fuzzy logic co-processor
EP0636967A1 (fr) * 1993-07-29 1995-02-01 STMicroelectronics S.r.l. Procédé et dispositif pour stocker des fonctions d'appartenance

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Publication number Publication date
US6385598B1 (en) 2002-05-07
EP0735459A1 (fr) 1996-10-02
JPH08286921A (ja) 1996-11-01
DE69531772D1 (de) 2003-10-23

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