EP0721162A2 - Speicherplattenanordnung mit auf gespiegeltem Speicher basierten doppelten Steuergeräten - Google Patents
Speicherplattenanordnung mit auf gespiegeltem Speicher basierten doppelten Steuergeräten Download PDFInfo
- Publication number
- EP0721162A2 EP0721162A2 EP95113550A EP95113550A EP0721162A2 EP 0721162 A2 EP0721162 A2 EP 0721162A2 EP 95113550 A EP95113550 A EP 95113550A EP 95113550 A EP95113550 A EP 95113550A EP 0721162 A2 EP0721162 A2 EP 0721162A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- controller
- memory
- failure
- controllers
- mirrored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
- G06F11/2089—Redundant storage control functionality
- G06F11/2092—Techniques of failing over between control units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Definitions
- This invention relates, in general, to computer disk storage system controllers and, more particularly, to real-time, mirrored memory controllers for providing accurate and immediate failover reliability.
- objects of the present invention are to provide a dual controller disk storage system having real-time, synchronous, mirrored memory for providing immediate, accurate, and reliable failover in the event of failure of one controller or its memory.
- a disk storage control system includes dual controllers having real-time, synchronous, mirrored memory therebetween to provide immediate, accurate, and reliable failover in the event of failure of one controller or its memory.
- Non-volatile random access memory provides retention of data during the loss of power and during the manipulation of hardware for purposes of repair of a controller.
- a communication path is established within the mirrored memory between the controllers to monitor and coordinate their activities. The state of the mirrored memory is continuously monitored for accuracy of the mirror and failure detection.
- This system and method provides concurrent and ready access for each controller to the same disk storage control data set without need for extra manipulation or extra direct memory access (DMA) activity to satisfy host requests. Accordingly, either controller can provide immediate failover control for the disk storage system. Furthermore, either controller can be hot swapped in the event of failure without the need for preparatory intervention. Finally, in the event of a failed stand alone controller, a secondary controller can be physically inserted into the system to recover a mirror image from the failed controller's memory as long as the shared mirrored memory was not the failing component.
- DMA direct memory access
- Figure 1 is a block diagram representing an overview of the present invention computer disk storage control system having dual controllers.
- FIG. 2 is a more detailed block diagram of the dual controller disk storage system of Figure 1.
- FIG. 3 is a schematic block diagram of control circuitry of the present invention.
- Figure 4 is the schematic block diagram of Figure 3 wherein uni-directional paths of data flow are depicted exemplary of a real-time, synchronous, mirrored memory write access from controller 20 to controller 25.
- Figure 5 is a block diagram depicting a preferred embodiment communication path between each controller mirrored memory.
- Figure 6 is a table depicting messages representative of the tightly coupled communication protocol embodied in the present invention.
- Figure 1 is a system diagram representing an overview of the present inventive dual controller disk storage system.
- a disk storage system is depicted generally at 10, having disk storage devices 12 depicted generally at disk drive array 15, and dual disk storage controllers depicted at 20 (in slot “A") and 25 (in slot “B”).
- Disk storage system 10 is shown as a separate component from computer 27 and peripheral devices 29 but could be contained within a common enclosure.
- controllers 20 and 25 each have memory 30 and 35, respectively. Although most any type of Random Access Memory (RAM) is suitable for use as memory 30 and 35, in the preferred embodiment a non-volatile RAM (or volatile RAM made non-volatile by use of a power supply backup) is used to allow for retention of data in the event of a power failure, controller failure, communications failure, or the like. Although only dual controllers 20 and 25 are shown in the diagram and discussed generally herein, it will be obvious that the teachings expressed and implied herein are likewise applicable in a multiple controller environment, i.e., more than two controllers.
- RAM Random Access Memory
- Each memory 30 and 35 is a mirrored memory.
- mirrored memory simply means that data in one memory is duplicated or "mirrored” in another memory.
- mirrored memory means that data in the memory of one controller is duplicated or "mirrored” in the memory of the other controller.
- the mirrored memory is a real-time mirrored memory, i.e., a single microprocessor or direct memory access updates data into or retrieves data from both memories 30 and 35 substantially concurrently.
- the existence of dual controllers, and mirrored memory in each provides a fault tolerant environment for disk storage system 10.
- accuracy of failover is the ability of a dual controller system to failover in the presence of anomalies without data loss.
- Reliability of failover is the ability of a dual controller system to detect and recover from differing hardware failures.
- Accuracy refers to how well the system failed over
- reliability refers to how many situations the system can failover from.
- this disclosure includes a monitoring function which ensures that the failover memory image is consistent with the primary image. This certainly improves the accuracy but does little to enhance reliability. In contrast, other features concentrate on reliability but do not tend to enhance accuracy.
- Disk controllers 20 and 25 include control logic 40 and 45 that, among other functions in a preferred embodiment, control the mirroring process, maintain low level mirroring accuracy, and low level failure detection of the mirroring process.
- the control logic may be in a central location separate from the controllers.
- Low level detection works on an access by access basis looking for abnormalities in that specific operation, i.e., the hardware level detection of failure.
- a logical level of failure includes a detection in an inconsistency in the mirrored images, detection of major hardware failures, and inability of the board to communicate regarding system events.
- Data flow between the controllers and disk array 15 is through the disk assembly backplane at 66. Data flow between controller 20 and 25 is also via the backplane at 67.
- each controller 20 and 25 is referenced generally, each mirrored memory 30 and 35 is referenced as Non Volatile Dynamic Random Access Memory (NVDRAM) as used in the preferred embodiment, and control logic 40 and 45 are likewise referenced as in Figure 2.
- NVDRAM Non Volatile Dynamic Random Access Memory
- All directional arrows indicate paths of communication and/or transfer of data.
- control logic 40 and 45 contribute to monitoring and controlling the dual controller relationship to satisfy these two key factors for providing failover. Namely, signals are exchanged between the controllers (control logic) to: inform the other controller as to the working status of each controller; selectively control the real-time, synchronous, mirroring process; and detect failures. Consequently, when a low level failure is detected, the mirror can be selectively disabled, and complete, accurate, and immediate failover can occur.
- Each DRAM controller 50 and 55 has its own internal clock (not shown) for governing its respective circuitry and for purposes such as initiating a request for memory refresh.
- each control logic 40 and 45 has its own internal clock whereby a response timeout may be detected during negotiations between controllers, i.e., from one control logic to the other.
- Control logic 40 and 45 control which controller is granted access to the memories 30 and 35, and which controller is disabled from accessing the same. As such, control logic 40 and 45 talk to and arbitrate/negotiate, respectively, with each other, with DRAM controllers 50 and 55, buffers 60 and 65, control transceivers 70 and 75, and data transceivers 80 and 85.
- DRAM controllers 50 and 55 manage and generate timing and control logic signals, such as Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE), Output Enable (OE) etc., for accessing appropriate addresses in DRAM 30 and 35, respectively.
- Buffers 60 and 65 are DRAM controller buffers for enabling/disabling each DRAM controller 50 and 55 with respect to accessing DRAM 30 and 35 respectively.
- Control transceivers 70 and 75 are bi-directional transceiver buffers for a local controller (i.e., the controller on which the transceiver resides) to (1) drive address signals to a backplane 78 of the computer system to access the other (remote) controller's memory, or (2) receive address signals from the remote controller through the backplane to access the local controller's memory.
- data transceivers 80 and 85 are bi-directional transceiver buffers for a local controller to (1) drive data signals to the backplane 78 to send to the remote controller, or (2) receive data signals from the remote controller through the backplane.
- Figure 3 Operation of Figure 3 is best described by an example as shown in Figure 4.
- Figure 4 is the same as Figure 3 except that the bi-directional arrows of Figure 3 are substituted in Figure 4 with uni-directional arrows depicting the actual directional paths of data transfer for a real-time, synchronous write to both sides of the mirrored memory by controller 20.
- hardware states such as Master, Slave, Request, etc.
- logical states refer to which of the controllers are servicing a host request in an active/passive dual controller relationship.
- DRAM controller 50 asserts a Request signal to its own control logic 40.
- Control logic 40 then enters a hardware Request state and waits for control logic 45 of controller 25 to enter into a hardware Slave state (assuming controller 25 currently has access to the mirror).
- a hardware Request state is when the local control logic 40 (in this example) waits for the remote control logic 45 to grant local controller 20 access to remote DRAM 35.
- a hardware Slave state is when remote control logic 45 disables DRAM controller buffer 65 (in this example) to grant local controller 20 access to DRAM 35.
- DRAM controller 55 of controller 25 completes its cycle for using the memory (either for reading or writing), it removes its own Request to control logic 45 and enters into a hardware Slave state.
- control logic 45 disables DRAM controller buffer 65 as shown by the depiction that no directional arrow proceeds out from (points away from) buffer 65.
- Control logic 45 also sets control transceivers 75 to drive address signals from backplane 78 to DRAM 35 as shown by directional arrows 73 and 77, and sets data transceivers 85 to drive data from backplane 78 to DRAM 35 as shown by directional arrows 87 and 83.
- Control logic 40 acknowledges this by entering into a hardware Master state wherein controller 20 is allowed access to both memories 30 and 35.
- Control logic 40 enables its local DRAM controller buffer 60 as shown by directional arrow 62; sets control transceivers 70 to drive from controller 20 to backplane 78 as shown by directional arrow 73; and enables data transceivers 80 to drive from controller 20 to backplane 78 as shown by directional arrow 87.
- DRAM controller 50 performs a DRAM write cycle by driving the row address to access its own DRAM 30 as shown by directional arrow 64 and by driving the same through control transceivers 70 and 75 to access DRAM 35 of controller 25 as shown by directional arrows 66, 73 and 77.
- RAS is then asserted, the column address is driven, and CAS is likewise asserted to write appropriate data to DRAM 30 (as shown by directional arrow 71 and 74), and, substantially simultaneously, to DRAM 35 (as shown by directional arrows 76, 87 and 83). Accordingly, this writing of data to DRAM 30 and 35 is to mirrored address locations, and is performed in a substantially real-time, synchronous manner.
- one implementation of detecting failure utilizes arbitration control logic 40 and 45.
- Each control logic generates state transition signals to identify a mirrored memory access status for the controller on which the control logic resides.
- Each control logic also monitors the state transition signals of the other.
- a failure in the mirrored memory system between the dual controllers is detected by one controller sensing an incorrect state transition signal communicated from the other controller.
- a failure is also detected by one controller not sensing a state transition signal from the other within a specified timeout period.
- Memory refresh cycles are tapped to cause the arbitration control logic to cycle through state transition signals thereby forcing each controller to attempt a mirrored memory access on a regular basis whereby a memory system failure may be detected.
- This system and method affords reliability in any dual controller relationship, such as logical master/master (peer/peer) or logical master/slave. It is especially valuable in a logical master/slave controller relationship because a slave controller may not access the mirrored memory often and, therefore, would not detect whether the remote controller has failed until a later and potentially detrimental time.
- a memory access cycle read, write, or refresh
- that signal is driven to its local control logic 40 or 45.
- the local control logic drives a state transition signal to the other (remote) controller requesting such access.
- the state transition signal identifies the mirrored memory access status of the (local) controller sending the signal. For example, in this instance, a state transition signal requesting memory access is sent to the remote control logic.
- the remote controller having mirrored memory access senses the requesting state transition signal and replies with a responsive state transition signal which grants the requesting controller access to the mirrored memory. The response is granted after the remote controller completes its own mirrored memory access if such is occurring when the request is received. This process is essentially the same as previously described in reference to Figure 4 for a real-time, synchronous write.
- the local control logic sends the memory request, it initiates its own timer to clock a timeout period. If the remote controller does not respond within the predetermined interval of time, i.e., the timeout period, the local controller recognizes that a failure has occurred with the remote controller memory system or with the arbitration means associated with the remote controller.
- a remote controller memory system failure is also detected upon the sensing by the local controller of an incorrect state transition signal sent from the remote controller. For example, if the local controller is expecting to receive a state transition signal granting it access to the mirrored memory, but instead receives some other state transition signal from the remote controller, the local controller recognizes that a failure has occurred.
- each controller (1) sends its own mirrored memory access status to the other controller, (2) senses the access status of the other controller, and/or (3) senses whether an appropriate status signal is sent. Furthermore, memory refresh cycles are tapped to force arbitrary cycling through the state transition signals whereby mirrored memory is accessed on a regular basis to provide for a consistent and reliable means for failure detection in the memory system.
- FIG. 5 another means for communication and logical failure detection between the controllers includes messaging mailboxes and a tightly coupled communication protocol therewith. Namely, in each mirrored memory 30 and 35, a reserved portion 100 and 105 is designated generally as a messaging mailbox. Mailboxes 100 and 105 are used as an underlying logical layer of communication and control means to monitor and coordinate activities between the controllers.
- controllers 20 and 25 Through each mailbox, communication occurs between controllers 20 and 25 to provide a cost effective real-time link, and to allow each controller to monitor the state of the duplicate controller and to coordinate activities. Communication works by a (local) controller writing a message to its own mailbox and then the other (remote) controller reading the message out of that same mailbox.
- each mailbox 100 and 105 is read and written by the controller on which the mailbox resides but only read by the other controller.
- controller 20 reads and writes its own mailbox 100, and only reads the other mailbox 105.
- controller 25 reads and writes its own mailbox 105, and only reads the other mailbox 100.
- memory 30 and 35 is generally mirrored memory, mirroring is selectively controlled (disabled) during writing of reserved mailbox portions 100 and 105 to effectuate communication therebetween and to avoid unintentional collateral damage to the other controller's memory.
- the mirroring process is likewise selectively controlled such that only the remote data is read.
- Each mailbox 100 and 105 actually comprises at least two separate mailbox parts in the preferred embodiment: one control mailbox 110 and 115 for holding and communicating a control message, and one reply mailbox 120 and 125 for holding and communicating a reply message.
- the control message is a specific request (or inquiry) intended for the other controller, whereas the reply message is a specific response to a request or inquiry.
- the reply message is a specific response to a request or inquiry.
- mailboxes 100 and 105 make up a full duplex communication path. Specifically, requests made in mailbox 100, control part 110, are replied to in mailbox 105, reply part 125. Additionally, requests made in mailbox 105, control part 115, are replied to in mailbox 100, reply part 120.
- Communication of messages between the mailboxes and controllers occurs only through a tightly coupled communication protocol to insure proper messaging. Namely, for each message there is a specific, unambiguous, and unique response (reply) to a specific, unambiguous, and unique request (inquiry). This allows a receiver of a reply (i.e., an initiator of a request or inquiry) to validate that a reply is indeed the answer to his specific request.
- a receiver of a reply i.e., an initiator of a request or inquiry
- a sliding window interlock scheme is used in association with any message written into mailboxes 100 and 105.
- a sliding window interlock scheme includes the use of an identification number with each message to further insure message detection and one-to-one message correctness. For example, when a requesting controller writes a request message into its control mailbox, a sliding window interlock identification number is written also. When the other reply controller reads the message, it reads the identification number also. Consequently, when the reply controller writes a reply message to its own reply mailbox in response to the request message, it includes the same identification number with the reply. When the requesting controller reads the reply message, it also reads the identification number to make sure it is the same number as originally sent with the request message, and thus the requesting controller is able to detect and be sure that the reply is in fact an intended reply to its original request.
- requesting controller shall mean a controller that writes a message into its own control mailbox, and subsequently reads a reply message from the other controller's reply mailbox.
- reply controller shall mean a controller that reads a message from the control mailbox of the other controller, and subsequently writes a reply message to its own reply mailbox.
- a requesting controller After a requesting controller writes a message into its own mailbox, it immediately communicates to the reply controller that a message exists in the requesting controller's mailbox for the reply controller to read.
- the requesting controller communicates this by generating an interrupt signal to the reply controller.
- the interrupt signal is generated by hardware and/or software as is commonly known in the art.
- a reply controller is able to detect that a message exists in a requesting controller's mailbox in two distinct ways, either of which may be used as a primary means of detection.
- a reply controller detects that a message exists by detecting the interrupt signal generated by the requesting controller which explicitly communicates to the reply controller that a message exists.
- the reply controller detects that a message exists by polling the requesting controller's mailbox on a timed interval basis, regardless of ever receiving the interrupt signal generated by the requesting controller. In the preferred embodiment, the timed interval is approximately 16 seconds.
- Each controller responds to its own clock upon the timed interval basis by polling the other controller's mailbox to detect whether a message exists. This dual method of detecting messages provides additional robustness and reliability of communication between the controllers in the case of failure of one method or the other.
- a controller is able to detect and read a message that has been written in the other controller's mailbox. This type of message is referred to as an "express” message. However, a controller may also detect and “read” an "implied” message that is not actually written in the other controller's mailbox An “implied” message may be “read” from an interpretation of a set of circumstances relating to either controller. For example, assume a requesting controller sends a request message but never receives a reply message back from the other controller (this state being recognized upon detection of a timeout interval), or a reply message received was inappropriate or incorrect due to some communication problem associated with either of the controllers. In these instances, an "implied” communication has occurred. Namely, the requesting controller did not receive an "express” reply message back, but given the detection or recognition of not having received an express reply message, the requesting controller "reads" the circumstances, i.e., no reply message received, and initiates appropriate action accordingly.
- Appropriate action is any predefined standard operating procedure (SOP) which the controllers are designated to follow.
- SOP standard operating procedure
- appropriate action may be for the requesting controller to enter into an isolation mode wherein mirroring is selectively disabled between the controllers, and the requesting controller assumes control of the disk storage system on its own until a repair of the failure of communication occurs.
- SOPs any number and variety of SOPs may be designated and followed in response to an implied or express message, and it is not the purpose here to define all those possibilities. It is the purpose here to only reflect the fact that some predefined action is taken by a controller in response to an express or an implied message detected.
- a reply controller reads the message contained in the requesting controller's control mailbox 110 or 115 upon detecting that a request message exists (via interrupt or polling). In response to the request, the reply controller then writes a specific reply to its own reply mailbox 120 or 125 and subsequently sends an interrupt signal back to the requesting controller following the same procedure that the requesting controller followed. The requesting controller then detects the message in the reply controller's reply mailbox via the interrupt or the timed interval poll previously described. Consequently, each controller takes appropriate action based on the request and reply messages.
- the tightly coupled communication protocol is only one element of the present invention system and method for retaining real-time, synchronous mirrored memory and for detecting a failure in either controller in order to provide for immediate and accurate failover.
- This tightly coupled protocol demonstrates how for each message, a specific, unambiguous response to a specific, unambiguous request occurs to be sure communication is precise, understood, and known.
- the term "message sent” will refer to the fact that a message has been written by a controller to its own mailbox (either control or reply mailbox, as appropriate, given the state of the communication occurring), even though it is understood that the message is not actually "sent” anywhere but, in fact, is merely read from the mailbox by the other controller as previously discussed herein.
- Master refers to the logical Master controller that is presently operating on and responding to all host computer requests relative to the disk storage system
- the term “Slave” refers to the logical Slave status of the other controller (i.e., the controller not responding to host requests).
- Figure 6 is representative of the messages that would most likely be used in a dual controller with a logical Master/Slave relationship. However, it is obvious that the principles of the present invention are equally applicable to other multiple controller relationships (i.e. Master/Master, etc.).
- Message number 1 is a message sent by the Slave controller to the Master as a heartbeat message (sent periodically) and used by the slave to detect when the Master has failed. If the Master is still active and communicating, its only response is YES-ACTIVE, which indicates all is in order. On the other hand, if the Master recognizes that it is no longer serving as Master or is no longer able to serve as Master, its only response is NO-INACTIVE. Given either of these specific, unambiguous replies in response to the specific, unambiguous request, each controller knows exactly what action to take.
- TIMEOUT-I'M-BECOMING-MASTER is a message sent by the Slave when it detects that a timeout has occurred, i.e., the Master has not replied within a given time period (which is directly related to the rate of the timer based polling of messages).
- the only response the Master can reply with is OK-BECOMING-SLAVE, meaning the Slave will then become the Master.
- the Master may not be able to respond due to some failure, and the Slave becomes Master anyway in recognition of the failure to respond.
- Message number 3 is a message sent by the Slave to the Master when the Slave detects its own failure.
- the only response the Master can reply with is OK-REPORTING-BROKEN, meaning the Master reports the failure to the host computer.
- TAKEOVER is a message sent by the Master to the Slave when the Master wants the Slave to become the new Master.
- the only valid reply the Slave can respond with is OK-TAKING-OVER.
- COMM-FAILURE is a message sent by either controller to the other when some communication failure has been detected. The only valid reply is ACKNOWLEDGE-COMM-FAILURE.
- Message number 6 is a message sent by either controller to the other when the other needs to be reset to correct some failure that has occurred.
- the only valid reply is OK-RESETTING.
- UPDATE-TO-VALID-SLAVE is a message sent by the Master to the Slave in order for the Slave to update its mirrored state variables.
- the only valid reply in this instance is UPDATED-TO-VALID-SLAVE.
- NO-MESSAGE/NO-REPLY is a message sent by either controller to the other to validate that no message (or reply, as the case may warrant) is being sent in the respective control or reply mailbox to which the NO-MESSAGE/NO-REPLY is written.
- this messaging is to be sure that the reply mailbox is communicating a "valid" message of "nothing” or "null” (i.e., NO-REPLY) when a control message is sent to the control mailbox.
- NO-REPLY a "valid" message of "nothing” or "null” (i.e., NO-MESSAGE) when a reply message is sent to the reply mailbox.
- NO-MESSAGE/NO-REPLY is sent to communicate that no other message is being transmitted or expected at the present time.
- a requesting controller writes a message (such as ARE-YOU-ACTIVE) into its own control mailbox, it also writes a NO-REPLY message into its own reply mailbox so that the other controller knows that this is a control message being sent and not some erroneous reply message being sent.
- Each of these examples shows how a tightly coupled communication protocol is followed between the controllers for monitoring and coordinating their activities.
- Each request and reply message is very specific and unambiguous, and each "null" message is specific and unambiguous so that express communication is absolutely understood, and implied communication occurs from a lack of express communication detected by the tightly coupled protocol.
- the present invention also allows for accurate and complete failover to occur from a failed stand-alone controller. Namely, assume storage management system 10 is being used with a single controller, such as controller 20 (in slot "A"), in a stand-alone mode, and controller 25 is not presently inserted in the system. If controller 20 fails, and the failure is not related to the NVDRAM memory or its access circuitry, then the present inventive system allows for a hot swap such that controller 25 may be inserted into slot "B" to allow for complete failover from controller 20 to controller 25. Specifically, failover occurs without the need for any preparatory intervention. No preliminary commands or the like are necessary for detecting the status and accuracy of the mirror contents of the failed controller, and no preparation or manipulation is necessary to write the memory contents of the failed controller to the newly inserted (hot swapped) controller.
- either controller can use the same hot swap feature referred to above to be removed from the system without the need for preparatory commands to prepare that controller for removal. This further enhances the ability for the system to recover from hardware failures from ether of the two controllers.
- Another means for providing accurate failover is by constantly monitoring and detecting the data consistency of the mirror image on each controller memory by way of "scrubbing" of the memory. This scrubbing process helps detect errors in the memory and retain an accurate mirror image in preparation for a potential failover event.
- the logical Master controller performs the scrub process preferably in a background mode or when the system 10 is idle.
- the scrubbing process reads each and every address location to find correctable/uncorrectable errors and to fix such errors to ensure consistency between the controllers. Scrubbing continually monitors the consistency of the two mirrored memory images to ensure they remain synchronized (accurate) for a future point of failure.
- the disk storage control data set includes control structures, mapping, cache, and structures controlling host requests in progress.
- both controllers have real-time access to the data control structures associated with that data set. Therefore, concurrent access to the same data set is provided without additional manipulation or DMA activity to satisfy host requests from either controller. For example, a specific host request accessing data from a specific logical address which resides on disk or in cache can be serviced by either controller in a logical Master/Master dual controller relationship.
- the present invention system provides a fault tolerant computer disk storage control system by using dual controllers 20 and 25 and mirrored memory 30 and 35.
- a substantially complete, accurate, and immediate operational failover from one controller to the other is provided by:
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US369842 | 1989-06-22 | ||
US36984295A | 1995-01-06 | 1995-01-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0721162A2 true EP0721162A2 (de) | 1996-07-10 |
Family
ID=23457149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95113550A Withdrawn EP0721162A2 (de) | 1995-01-06 | 1995-08-29 | Speicherplattenanordnung mit auf gespiegeltem Speicher basierten doppelten Steuergeräten |
Country Status (3)
Country | Link |
---|---|
US (1) | US5928367A (de) |
EP (1) | EP0721162A2 (de) |
JP (1) | JPH08241173A (de) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0889409A1 (de) * | 1997-06-26 | 1999-01-07 | Digital Equipment Corporation | Wärmeaustausch von gespiegeltem Nachschreib-Cachespeicher |
EP1028367A1 (de) * | 1999-02-11 | 2000-08-16 | Bull S.A. | Anordnung und Verfahren für die Verbesserung der Schreibleistung einer Rechnerdatenspeicherperipherie |
US6167531A (en) * | 1998-06-18 | 2000-12-26 | Unisys Corporation | Methods and apparatus for transferring mirrored disk sets during system fail-over |
US6658542B2 (en) * | 1999-03-03 | 2003-12-02 | International Business Machines Corporation | Method and system for caching data in a storage system |
CN105389233A (zh) * | 2015-10-21 | 2016-03-09 | 广州视睿电子科技有限公司 | 双***状态参数存储方法、第一***及双***终端 |
Families Citing this family (113)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5799141A (en) * | 1995-06-09 | 1998-08-25 | Qualix Group, Inc. | Real-time data protection system and method |
JP3628777B2 (ja) | 1995-10-30 | 2005-03-16 | 株式会社日立製作所 | 外部記憶装置 |
US6189111B1 (en) * | 1997-03-28 | 2001-02-13 | Tandem Computers Incorporated | Resource harvesting in scalable, fault tolerant, single system image clusters |
US6073209A (en) * | 1997-03-31 | 2000-06-06 | Ark Research Corporation | Data storage controller providing multiple hosts with access to multiple storage subsystems |
US6578120B1 (en) * | 1997-06-24 | 2003-06-10 | International Business Machines Corporation | Synchronization and resynchronization of loosely-coupled copy operations between a primary and a remote secondary DASD volume under concurrent updating |
JP3618529B2 (ja) * | 1997-11-04 | 2005-02-09 | 富士通株式会社 | ディスクアレイ装置 |
US6170044B1 (en) * | 1997-12-19 | 2001-01-02 | Honeywell Inc. | Systems and methods for synchronizing redundant controllers with minimal control disruption |
US6230240B1 (en) * | 1998-06-23 | 2001-05-08 | Hewlett-Packard Company | Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface |
US6282584B1 (en) * | 1998-08-18 | 2001-08-28 | International Business Machines Corporation | Structure and method for reading/writing signature commands from/to a plurality of controller pairs |
US7233977B2 (en) * | 1998-12-18 | 2007-06-19 | Emc Corporation | Messaging mechanism employing mailboxes for inter processor communications |
US6449731B1 (en) * | 1999-03-03 | 2002-09-10 | Tricord Systems, Inc. | Self-healing computer system storage |
US8024761B1 (en) * | 1999-04-01 | 2011-09-20 | Cox Communications, Inc. | Method and apparatus of load sharing and fault tolerance in an interactive video distribution system |
US6697960B1 (en) | 1999-04-29 | 2004-02-24 | Citibank, N.A. | Method and system for recovering data to maintain business continuity |
US6499113B1 (en) * | 1999-08-31 | 2002-12-24 | Sun Microsystems, Inc. | Method and apparatus for extracting first failure and attendant operating information from computer system devices |
US6658595B1 (en) * | 1999-10-19 | 2003-12-02 | Cisco Technology, Inc. | Method and system for asymmetrically maintaining system operability |
US6574753B1 (en) * | 2000-01-10 | 2003-06-03 | Emc Corporation | Peer link fault isolation |
JP4462697B2 (ja) | 2000-01-31 | 2010-05-12 | 株式会社日立製作所 | 記憶制御装置 |
JP4054509B2 (ja) * | 2000-04-19 | 2008-02-27 | 株式会社東芝 | フィールド機器制御システムおよびコンピュータが読取り可能な記憶媒体 |
US6766429B1 (en) * | 2000-08-31 | 2004-07-20 | International Business Machines Corporation | Low cost and high RAS mirrored memory |
US6732289B1 (en) * | 2000-08-31 | 2004-05-04 | Sun Microsystems, Inc. | Fault tolerant data storage system |
US6618628B1 (en) * | 2000-10-05 | 2003-09-09 | Karl A. Davlin | Distributed input/output control systems and methods |
US6845467B1 (en) | 2001-02-13 | 2005-01-18 | Cisco Systems Canada Co. | System and method of operation of dual redundant controllers |
US6820212B2 (en) * | 2001-02-20 | 2004-11-16 | Digi-Data Corporation | RAID system having channel capacity unaffected by any single component failure |
JP2002259207A (ja) * | 2001-03-02 | 2002-09-13 | Fujitsu Ltd | 情報処理装置及び信号処理装置並びにインタフェース装置 |
US6708285B2 (en) | 2001-03-15 | 2004-03-16 | Hewlett-Packard Development Company, L.P. | Redundant controller data storage system having system and method for handling controller resets |
US6715101B2 (en) | 2001-03-15 | 2004-03-30 | Hewlett-Packard Development Company, L.P. | Redundant controller data storage system having an on-line controller removal system and method |
US6802023B2 (en) | 2001-03-15 | 2004-10-05 | Hewlett-Packard Development Company, L.P. | Redundant controller data storage system having hot insertion system and method |
DE10297001B4 (de) * | 2001-06-28 | 2015-07-23 | Emc Corp. | Informations-Reproduktionssystem mit verbesserter Fehlererkennung und Rekonstruktion |
US7613806B2 (en) * | 2001-06-28 | 2009-11-03 | Emc Corporation | System and method for managing replication sets of data distributed over one or more computer systems |
JP4060552B2 (ja) * | 2001-08-06 | 2008-03-12 | 株式会社日立製作所 | 記憶装置システム、および、記憶装置システムの構成方法 |
US6978282B1 (en) | 2001-09-04 | 2005-12-20 | Emc Corporation | Information replication system having automated replication storage |
US7055056B2 (en) * | 2001-11-21 | 2006-05-30 | Hewlett-Packard Development Company, L.P. | System and method for ensuring the availability of a storage system |
US6941493B2 (en) * | 2002-02-27 | 2005-09-06 | Sun Microsystems, Inc. | Memory subsystem including an error detection mechanism for address and control signals |
US20030163769A1 (en) * | 2002-02-27 | 2003-08-28 | Sun Microsystems, Inc. | Memory module including an error detection mechanism for address and control signals |
US6952792B2 (en) * | 2002-03-19 | 2005-10-04 | International Business Machines Corporation | Failover system for storage area network |
US7035953B2 (en) * | 2002-05-03 | 2006-04-25 | Hewlett-Packard Development Company, L.P. | Computer system architecture with hot pluggable main memory boards |
US8140622B2 (en) | 2002-05-23 | 2012-03-20 | International Business Machines Corporation | Parallel metadata service in storage area network environment |
US7010528B2 (en) * | 2002-05-23 | 2006-03-07 | International Business Machines Corporation | Mechanism for running parallel application programs on metadata controller nodes |
US7448077B2 (en) * | 2002-05-23 | 2008-11-04 | International Business Machines Corporation | File level security for a metadata controller in a storage area network |
US7171610B2 (en) * | 2002-06-12 | 2007-01-30 | International Business Machines Corporation | Method, system, and article of manufacture for preventing data loss |
US6996766B2 (en) * | 2002-06-28 | 2006-02-07 | Sun Microsystems, Inc. | Error detection/correction code which detects and corrects a first failing component and optionally a second failing component |
US6973613B2 (en) * | 2002-06-28 | 2005-12-06 | Sun Microsystems, Inc. | Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure |
US6976194B2 (en) * | 2002-06-28 | 2005-12-13 | Sun Microsystems, Inc. | Memory/Transmission medium failure handling controller and method |
US6938124B2 (en) * | 2002-07-19 | 2005-08-30 | Hewlett-Packard Development Company, L.P. | Hardware assisted communication between processors |
US6996743B2 (en) * | 2002-07-26 | 2006-02-07 | Sun Microsystems, Inc. | Method for implementing a redundant data storage system |
US7069465B2 (en) * | 2002-07-26 | 2006-06-27 | International Business Machines Corporation | Method and apparatus for reliable failover involving incomplete raid disk writes in a clustering system |
EP1552392B1 (de) * | 2002-08-02 | 2008-11-05 | Grass Valley (U.S.) Inc. | Echtzeit-failover-wiederherstellung für ein mediennetzwerk |
US7096383B2 (en) * | 2002-08-29 | 2006-08-22 | Cosine Communications, Inc. | System and method for virtual router failover in a network routing system |
US7076687B2 (en) * | 2002-10-16 | 2006-07-11 | Hitachi, Ltd. | System and method for bi-directional failure detection of a site in a clustering system |
US6996686B2 (en) * | 2002-12-23 | 2006-02-07 | Sun Microsystems, Inc. | Memory subsystem including memory modules having multiple banks |
US8250202B2 (en) * | 2003-01-04 | 2012-08-21 | International Business Machines Corporation | Distributed notification and action mechanism for mirroring-related events |
JP2004227097A (ja) * | 2003-01-20 | 2004-08-12 | Hitachi Ltd | 記憶デバイス制御装置の制御方法、及び記憶デバイス制御装置 |
US7299331B2 (en) * | 2003-01-21 | 2007-11-20 | Hewlett-Packard Development Company, L.P. | Method and apparatus for adding main memory in computer systems operating with mirrored main memory |
US7594002B1 (en) | 2003-02-14 | 2009-09-22 | Istor Networks, Inc. | Hardware-accelerated high availability integrated networked storage system |
US7779285B2 (en) * | 2003-02-18 | 2010-08-17 | Oracle America, Inc. | Memory system including independent isolated power for each memory module |
US6941396B1 (en) * | 2003-02-19 | 2005-09-06 | Istor Networks, Inc. | Storage controller redundancy using bi-directional reflective memory channel |
US7039771B1 (en) | 2003-03-10 | 2006-05-02 | Marvell International Ltd. | Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers |
US7870346B2 (en) | 2003-03-10 | 2011-01-11 | Marvell International Ltd. | Servo controller interface module for embedded disk controllers |
US7099963B2 (en) * | 2003-03-10 | 2006-08-29 | Qlogic Corporation | Method and system for monitoring embedded disk controller components |
US7492545B1 (en) | 2003-03-10 | 2009-02-17 | Marvell International Ltd. | Method and system for automatic time base adjustment for disk drive servo controllers |
US7080188B2 (en) | 2003-03-10 | 2006-07-18 | Marvell International Ltd. | Method and system for embedded disk controllers |
US7085886B2 (en) * | 2003-05-28 | 2006-08-01 | International Buisness Machines Corporation | Autonomic power loss recovery for a multi-cluster storage sub-system |
US8301809B2 (en) * | 2003-07-02 | 2012-10-30 | Infortrend Technology, Inc. | Storage virtualization computer system and external controller thereof |
US7530008B2 (en) | 2003-08-08 | 2009-05-05 | Sun Microsystems, Inc. | Scalable-chip-correct ECC scheme |
US7127636B2 (en) * | 2003-09-08 | 2006-10-24 | International Business Machines Corporation | Autonomic recovery of PPRC errors detected by PPRC peer |
US7188296B1 (en) | 2003-10-30 | 2007-03-06 | Sun Microsystems, Inc. | ECC for component failures using Galois fields |
FI20031628A0 (fi) * | 2003-11-10 | 2003-11-10 | Nokia Corp | Tietokoneryväs, tietokoneyksikkö ja menetelmä muistisaannin ohjaukseen tietokoneyksiköiden välillä |
US7152183B2 (en) * | 2003-11-20 | 2006-12-19 | Hitachi, Ltd. | Method and apparatus for volume replication management at planned and unplanned link down |
JP4319017B2 (ja) * | 2003-12-02 | 2009-08-26 | 株式会社日立製作所 | ストレージシステムの制御方法、ストレージシステム、及び記憶装置 |
US7137042B2 (en) * | 2004-03-17 | 2006-11-14 | Hitachi, Ltd. | Heartbeat apparatus via remote mirroring link on multi-site and method of using same |
US20050240726A1 (en) * | 2004-04-27 | 2005-10-27 | Hitachi Global Storage Technologies Netherlands B.V. | Synergistic hybrid disk drive |
US7409512B1 (en) | 2004-07-01 | 2008-08-05 | Symantec Operating Corporation | Method and apparatus for maintaining information that indicates valid regions of a working volume and using that information to delay volume initialization |
US7313724B1 (en) * | 2004-07-01 | 2007-12-25 | Symantec Operating Corporation | Method and apparatus for synchronizing redundant data with a volume |
US7240242B2 (en) * | 2004-08-05 | 2007-07-03 | International Business Machines Corporation | Apparatus and method to convert data payloads from a first sector format to a second sector format |
US7231545B2 (en) * | 2004-08-05 | 2007-06-12 | International Business Machines Corporation | Apparatus and method to convert data from a first sector format to a second sector format |
US7231546B2 (en) * | 2004-08-05 | 2007-06-12 | International Business Machines Corporation | Apparatus and method to overlay (N) first sectors onto (M) second sectors using a data queue |
US7219259B2 (en) * | 2004-08-05 | 2007-05-15 | International Business Machines Corporation | Apparatus and method to preserve data integrity during a power loss |
US7206908B2 (en) * | 2004-08-05 | 2007-04-17 | International Business Machines Corporation | Apparatus and method to convert a plurality of sectors from a first sector format to a second sector format |
US20060083102A1 (en) * | 2004-10-20 | 2006-04-20 | Seagate Technology Llc | Failover control of dual controllers in a redundant data storage system |
JP4491330B2 (ja) * | 2004-11-08 | 2010-06-30 | 富士通株式会社 | ディスクアレイ装置とそのデータのリカバリ方法およびデータリカバリプログラム |
US7730257B2 (en) * | 2004-12-16 | 2010-06-01 | Broadcom Corporation | Method and computer program product to increase I/O write performance in a redundant array |
FR2888071A1 (fr) * | 2005-06-30 | 2007-01-05 | France Telecom | Module et systeme de communication pour la mise en oeuvre d'un systeme de gestion a distance d'equipements |
JP4456060B2 (ja) | 2005-12-14 | 2010-04-28 | 富士通株式会社 | Raid制御装置、raid制御プログラム、raid制御方法 |
US7788231B2 (en) * | 2006-04-18 | 2010-08-31 | International Business Machines Corporation | Using a heartbeat signal to maintain data consistency for writes to source storage copied to target storage |
US7676690B2 (en) * | 2006-05-30 | 2010-03-09 | Dell Products L.P. | Mirroring of activity between electronic devices |
US20080065835A1 (en) * | 2006-09-11 | 2008-03-13 | Sun Microsystems, Inc. | Offloading operations for maintaining data coherence across a plurality of nodes |
US7661044B2 (en) * | 2007-02-12 | 2010-02-09 | International Business Machines Corporation | Method, apparatus and program product to concurrently detect, repair, verify and isolate memory failures |
US20080192422A1 (en) * | 2007-02-13 | 2008-08-14 | Inventec Corporation | System management protection device for server |
US8391921B2 (en) | 2007-02-13 | 2013-03-05 | Google Inc. | Modular wireless communicator |
US7970433B2 (en) | 2007-06-08 | 2011-06-28 | Modu Ltd. | SD switch box in a cellular handset |
US10027789B2 (en) | 2007-02-13 | 2018-07-17 | Google Llc | Modular wireless communicator |
US20090300291A1 (en) * | 2008-06-03 | 2009-12-03 | Gerald Keith Bartley | Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory System |
US20090300411A1 (en) * | 2008-06-03 | 2009-12-03 | Gerald Keith Bartley | Implementing Redundant Memory Access Using Multiple Controllers for Memory System |
US8412226B2 (en) | 2008-06-24 | 2013-04-02 | Google Inc. | Mobile phone locator |
US8282674B2 (en) * | 2008-07-18 | 2012-10-09 | Suspension Orthopaedic Solutions, Inc. | Clavicle fixation |
JP4739432B2 (ja) * | 2009-02-25 | 2011-08-03 | 富士通株式会社 | 冗長化システム、制御装置、制御方法 |
US8201020B2 (en) | 2009-11-12 | 2012-06-12 | International Business Machines Corporation | Method apparatus and system for a redundant and fault tolerant solid state disk |
US20120089776A1 (en) * | 2010-04-11 | 2012-04-12 | Active Storage, Inc. | Systems and methods for raid metadata storage |
US8412876B2 (en) * | 2010-06-30 | 2013-04-02 | Felicity Taiwan Corporation | Storage device with multiple storage units and control method thereof |
US20150331615A1 (en) * | 2012-11-20 | 2015-11-19 | Empire Technology Development Llc | Multi-element solid-state storage device management |
JP5949540B2 (ja) * | 2012-12-27 | 2016-07-06 | 富士通株式会社 | 情報処理装置、及び記憶情報解析方法 |
US9239797B2 (en) * | 2013-08-15 | 2016-01-19 | Globalfoundries Inc. | Implementing enhanced data caching and takeover of non-owned storage devices in dual storage device controller configuration with data in write cache |
US9594614B2 (en) * | 2013-08-30 | 2017-03-14 | Nimble Storage, Inc. | Methods for transitioning control between two controllers of a storage system |
US9836368B2 (en) * | 2015-10-22 | 2017-12-05 | Netapp, Inc. | Implementing automatic switchover |
US9952951B2 (en) * | 2015-10-22 | 2018-04-24 | Netapp Inc. | Preserving coredump data during switchover operation |
JP6547600B2 (ja) | 2015-11-13 | 2019-07-24 | 富士通株式会社 | ストレージシステム、および制御装置 |
KR102387973B1 (ko) * | 2015-12-01 | 2022-04-19 | 삼성전자주식회사 | 이중화 저장 장치, 그것을 포함한 서버 시스템 및 그것의 동작 방법 |
US10223220B2 (en) | 2016-10-13 | 2019-03-05 | International Business Machines Corporation | Processing a health condition message on a health condition to determine whether to perform a swap operation |
US10229013B2 (en) | 2016-10-13 | 2019-03-12 | International Business Machines Corporation | Generating a health condition message on a health condition detected at a server to send to a host system accessing the server |
US10884850B2 (en) * | 2018-07-24 | 2021-01-05 | Arm Limited | Fault tolerant memory system |
CN113821383A (zh) * | 2020-06-19 | 2021-12-21 | 华为技术有限公司 | 一种存储*** |
JP2022021260A (ja) | 2020-07-21 | 2022-02-02 | 富士通株式会社 | ストレージ制御装置、ストレージ装置及びストレージ制御プログラム |
CN112003793B (zh) * | 2020-08-21 | 2023-04-25 | 北京浪潮数据技术有限公司 | 一种数据镜像方法、装置、设备及介质 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4339804A (en) * | 1979-07-05 | 1982-07-13 | Ncr Corporation | Memory system wherein individual bits may be updated |
US5193154A (en) * | 1987-07-10 | 1993-03-09 | Hitachi, Ltd. | Buffered peripheral system and method for backing up and retrieving data to and from backup memory device |
US4958273A (en) * | 1987-08-26 | 1990-09-18 | International Business Machines Corporation | Multiprocessor system architecture with high availability |
EP0306211A3 (de) * | 1987-09-04 | 1990-09-26 | Digital Equipment Corporation | Synchronisiertes Doppelrechnersystem |
US5204952A (en) * | 1988-07-18 | 1993-04-20 | Northern Telecom Limited | Duplex processor arrangement for a switching system |
US5195100A (en) * | 1990-03-02 | 1993-03-16 | Micro Technology, Inc. | Non-volatile memory storage of write operation identifier in data sotrage device |
US5140592A (en) * | 1990-03-02 | 1992-08-18 | Sf2 Corporation | Disk array system |
US5214778A (en) * | 1990-04-06 | 1993-05-25 | Micro Technology, Inc. | Resource management in a multiple resource system |
US5155845A (en) * | 1990-06-15 | 1992-10-13 | Storage Technology Corporation | Data storage system for providing redundant copies of data on different disk drives |
US5212784A (en) * | 1990-10-22 | 1993-05-18 | Delphi Data, A Division Of Sparks Industries, Inc. | Automated concurrent data backup system |
US5155835A (en) * | 1990-11-19 | 1992-10-13 | Storage Technology Corporation | Multilevel, hierarchical, dynamically mapped data storage subsystem |
US5278838A (en) * | 1991-06-18 | 1994-01-11 | Ibm Corp. | Recovery from errors in a redundant array of disk drives |
DE69227956T2 (de) * | 1991-07-18 | 1999-06-10 | Tandem Computers Inc., Cupertino, Calif. | Multiprozessorsystem mit gespiegeltem Speicher |
US5237658A (en) * | 1991-10-01 | 1993-08-17 | Tandem Computers Incorporated | Linear and orthogonal expansion of array storage in multiprocessor computing systems |
US5297258A (en) * | 1991-11-21 | 1994-03-22 | Ast Research, Inc. | Data logging for hard disk data storage systems |
US5287462A (en) * | 1991-12-20 | 1994-02-15 | Ncr Corporation | Bufferless SCSI to SCSI data transfer scheme for disk array applications |
US5289418A (en) * | 1992-02-14 | 1994-02-22 | Extended Systems, Inc. | Memory apparatus with built-in parity generation |
US5418921A (en) * | 1992-05-05 | 1995-05-23 | International Business Machines Corporation | Method and means for fast writing data to LRU cached based DASD arrays under diverse fault tolerant modes |
US5459857A (en) * | 1992-05-15 | 1995-10-17 | Storage Technology Corporation | Fault tolerant disk array data storage subsystem |
US5437022A (en) * | 1992-12-17 | 1995-07-25 | International Business Machines Corporation | Storage controller having additional cache memory and a means for recovering from failure and reconfiguring a control unit thereof in response thereto |
US5546539A (en) * | 1993-12-29 | 1996-08-13 | Intel Corporation | Method and system for updating files of a plurality of storage devices through propogation of files over a nework |
US5682471A (en) * | 1994-10-06 | 1997-10-28 | Billings; Thomas Neal | System for transparently storing inputs to non-volatile storage and automatically re-entering them to reconstruct work if volatile memory is lost |
US5574863A (en) * | 1994-10-25 | 1996-11-12 | Hewlett-Packard Company | System for using mirrored memory as a robust communication path between dual disk storage controllers |
DE69523124T2 (de) * | 1994-12-15 | 2002-05-29 | Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto | Fehlererkennungssystem für einen gespiegelten Speicher in einer duplizierten Steuerung eines Plattenspeicherungssystems |
-
1995
- 1995-08-29 EP EP95113550A patent/EP0721162A2/de not_active Withdrawn
- 1995-12-11 JP JP7321539A patent/JPH08241173A/ja active Pending
-
1996
- 1996-04-29 US US08/641,084 patent/US5928367A/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
None |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0889409A1 (de) * | 1997-06-26 | 1999-01-07 | Digital Equipment Corporation | Wärmeaustausch von gespiegeltem Nachschreib-Cachespeicher |
US6167531A (en) * | 1998-06-18 | 2000-12-26 | Unisys Corporation | Methods and apparatus for transferring mirrored disk sets during system fail-over |
EP1028367A1 (de) * | 1999-02-11 | 2000-08-16 | Bull S.A. | Anordnung und Verfahren für die Verbesserung der Schreibleistung einer Rechnerdatenspeicherperipherie |
FR2789777A1 (fr) * | 1999-02-11 | 2000-08-18 | Bull Sa | Dispositif et procede d'amelioration des performances en ecriture d'un peripherique de stockage de donnees pour ordinateur |
US6658542B2 (en) * | 1999-03-03 | 2003-12-02 | International Business Machines Corporation | Method and system for caching data in a storage system |
CN105389233A (zh) * | 2015-10-21 | 2016-03-09 | 广州视睿电子科技有限公司 | 双***状态参数存储方法、第一***及双***终端 |
Also Published As
Publication number | Publication date |
---|---|
JPH08241173A (ja) | 1996-09-17 |
US5928367A (en) | 1999-07-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5928367A (en) | Mirrored memory dual controller disk storage system | |
EP0709781B1 (de) | System zur Verwendung eines gespiegelten Speichers als fehlerunempfindlichen Kommunikationspfad zwischen doppelten Plattenspeichersteuerungen | |
EP0717358B1 (de) | Fehlererkennungssystem für einen gespiegelten Speicher in einer duplizierten Steuerung eines Plattenspeicherungssystems | |
US5758057A (en) | Multi-media storage system | |
US6715101B2 (en) | Redundant controller data storage system having an on-line controller removal system and method | |
US6802023B2 (en) | Redundant controller data storage system having hot insertion system and method | |
US6708285B2 (en) | Redundant controller data storage system having system and method for handling controller resets | |
US5423044A (en) | Shared, distributed lock manager for loosely coupled processing systems | |
US6732231B1 (en) | System and method for management of mirrored storage devices storing device serial numbers | |
EP1426863B1 (de) | Verfahren und Vorrichtung zur Erhaltung der Konsistenz von Daten, die in einer Gruppe von Einspiegeleinrichtungen gespeichert sind | |
US20050071708A1 (en) | Method, system, and program for recovery from a failure in an asynchronous data copying system | |
EP0817054A2 (de) | Cache-Speicher mit doppeltem gleichzeitigem Schreiben | |
US7124244B2 (en) | Storage system and a method of speeding up writing data into the storage system | |
US6804794B1 (en) | Error condition handling | |
EP0709782A2 (de) | Fehlererkennungssystem für gespiegelten Speicher zwischen doppelten Plattenspeichersteuerungen | |
JP2005293315A (ja) | データミラー型クラスタシステム及びデータミラー型クラスタシステムの同期制御方法 | |
GB2369692A (en) | A fault tolerant computer with a bridge allowing direct memory access (DMA) between main memories of duplicated processing sets | |
KR20040005684A (ko) | 정보 처리 장치 | |
GB2369690A (en) | A dirty memory using redundant entries indicating that blocks of memory associated with the entries have been written to | |
JPH05298192A (ja) | 情報処理装置 | |
US6023748A (en) | Multiple client memory arbitration system capable of operating multiple configuration types | |
GB2369691A (en) | A dirty memory for indicating that a block of memory associated with it has been written to using control logic to interrogate the memory | |
JP3743381B2 (ja) | ホスト間処理同期方式 | |
JP2001356881A (ja) | 多重化記憶制御装置 | |
JPH06259274A (ja) | 二重系システム |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB |
|
17P | Request for examination filed |
Effective date: 19961107 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: HEWLETT-PACKARD COMPANY, A DELAWARE CORPORATION |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Effective date: 20060221 |