EP0617399B1 - Dispositif d'affichage à cristaux liquides - Google Patents

Dispositif d'affichage à cristaux liquides Download PDF

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Publication number
EP0617399B1
EP0617399B1 EP94104742A EP94104742A EP0617399B1 EP 0617399 B1 EP0617399 B1 EP 0617399B1 EP 94104742 A EP94104742 A EP 94104742A EP 94104742 A EP94104742 A EP 94104742A EP 0617399 B1 EP0617399 B1 EP 0617399B1
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Prior art keywords
selection
row
row electrode
liquid crystal
signals
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EP94104742A
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German (de)
English (en)
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EP0617399A1 (fr
Inventor
Takeshi C/O Asahi Glass Company Ltd. Kuwata
Takanori C/O Asahi Glass Company Ltd. Ohnishi
Temkar N. C/O Raman Research Inst. Ruckmongathan
Masami C/O Optrex Corporation Ito
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AGC Inc
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Asahi Glass Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present invention relates to a liquid crystal display apparatus in which a liquid crystal display element having a fast responding characteristic is used.
  • the present invention relates to a passive matrix type liquid crystal display apparatus wherein row selection voltages are generated by a multiple line selection method.
  • a liquid crystal display element responding to the effective value of a voltage applied such as a supertwisted nematic (STN) liquid crystal element has been practically used.
  • STN supertwisted nematic
  • a liquid crystal element having a fast responding characteristic has been desired.
  • the liquid crystal element having a fast responding characteristic had a problem that an optical difference was small between an ON state and an OFF state whereby contrast was poor.
  • a successive line addressing method which selects and drives for each scanning line, each element of a liquid crystal element in which the elements are arranged in a matrix form.
  • the successive line addressing method is used for a liquid crystal element having a response time of about 200 msec which is not so high, the response time is relatively long in comparison with the period of the waveform of a voltage for the successive line addressing method.
  • the response time is short as about 20-100 msec, the response time becomes close to the period of the waveform of the voltage for the successive line addressing method.
  • a multiple line selection method for selecting a plurality of scanning lines as a batch.
  • a multiple line selection method there are a method of simultaneously selecting all scanning lines as described in SID '92 DIGEST (1992) P. 228 and a method of simultaneously selecting a plurality of scanning lines which are less than all scanning lines described in SID '92 DIGEST (1992) P. 238.
  • the time sequence of each of the selection signals given to the scanning lines simultaneously selected is an orthogonal function formed by +1 and -1.
  • the signal lines for providing display data are supplied with voltages based on a result of comparison of the orthogonal function with each of the data.
  • each of the row electrodes is scanned twice in a display sequence constituted by two frames.
  • a single row electrode is selected at once, and accordingly, it is enough to use a single row electrode driver for controlling the polarity of voltage applied.
  • each of the scanning lines can be scanned 2L times in a single display sequence wherein L is the number of scanning lines simultaneously selected.
  • the period of the selection signals applied to the row electrode can be short. Namely, the reduction of the optical difference (between an ON state and an OFF state) of the liquid crystal element can be suppressed in comparison with a case of the successive line driving method. Accordingly, a driving method applicable to a fast responding element can be realized. In this case, however, it is necessary to control independently the polarity of the row electrodes corresponding to a plurality of selected scanning lines.
  • the inventors of this application proposed a driving method of liquid crystal wherein an L number of scanning lines are simultaneously selected and the polarity of the row electrodes is effectively controlled, in Japanese Unexamined Patent Publication Nos. 27904/1994, 27907/1994 and USP 5,262,881. The proposed methods will be described in brief.
  • Selection voltages applied to the row electrodes forming the m th (m is any one of 1-M) row electrode subgroup selected can be expressed by the arrangement of the L order of vectors in time sequence, the vectors being based on voltages applied to the row electrodes.
  • the arrangement of the vectors in time sequence is referred to as a selection voltage matrix.
  • column vectors which form a selection voltage matrix are referred to as selection voltage vectors.
  • each element of the selection voltage vectors which form a selection voltage matrix is applied as voltages to the corresponding row electrodes. The voltage is applied successively to each of the row electrode with respect to the all selection voltage vectors, whereby the selection of a single row electrode subgroup is completed.
  • K is determined to be excessively large, the number of selection pulses necessary to select the row electrodes is large. Accordingly, it is preferable that K may be the smallest value as possible.
  • the Hadamard's matrices shown in Figures 9 (a) and (c) could control ununiformity of display.
  • the L-row-K-column matrix A can be formed by removing an optional (K-L) rows from a K order matrix wherein the product of a matrix and a transposed matrix of the same forms a scalar multiple of the unit matrix.
  • the selection voltage matrix a matrix of vectors wherein the selection voltage vectors composed of at least ⁇ 1, ⁇ 2, ..., ⁇ k, - ⁇ 1, - ⁇ 2, ..., - ⁇ k are arranged, is selected. Namely, the selection voltage matrix composed of the 2K number of vectors wherein each of the vectors appears once in the selection voltage matrix can be selected.
  • the selection signals are dispersed in a display sequence to reduce the length of a non-selection period with respect to each of the row electrodes.
  • the selection signals should not be continuously applied to a row electrode subgroup in accordance with each pattern which is shown by selection voltage vectors, but the voltages composed of a single or some selection voltage vectors should be applied to a row electrode subgroup, and the same voltages be used for controlling another row electrode subgroup.
  • an increased number of the division of the selection voltage vectors is effective to suppress the frame response since the non-selection period can be reduced. Further, it is preferable to uniformly disperse the selection signals. Thus, after the voltages composed of one or some selection voltage vectors have been applied to a row electrode subgroup, the voltages are applied to another row electrode subgroup.
  • Signals applied to column electrodes to which display signals are provided are determined as follows. Supposing that a series of data ⁇ are composed of selected voltage vectors wherein an element of +V r is 1 and an element of -V r is 0, and a series of data ⁇ correspond to each of selected row electrodes, among data to be applied to row electrodes. Exclusive OR is applied to elements between the series of ⁇ and the series of ⁇ . And then, an arithmetical sum is obtainable from a result of the application of the operations. Accordingly, when there are an i number of elements which have different values, the arithmetical sum is i. Then, voltage to be applied to the row electrode is Vi.
  • Vi is selected from an (L+1) number of voltage levels where V O ⁇ V1 ⁇ ... ⁇ V L .
  • the absolute value of the voltage levels is determined by a threshold voltage and so on of the liquid crystal element. It is desirable that the values are selected so that the column voltages form an alternating form.
  • V i ((2i-L)/L)V c
  • V r (N 1/2 /L)V c
  • the ratio V ON /V OFF of the voltage effective value can be the maximum where V c is the maximum value in voltages applied to the column electrodes.
  • Conditions other than the above-mentioned conditions may be employed. Namely, V i and V r may be adjusted so that the best contrast ratio is obtainable in the vicinity of the conditions.
  • the gradation degree can be obtained by a frame modulation method. Further, an amplitude modulation method as proposed in Japanese Application No. 269560/1992 may be used.
  • a liquid crystal display apparatus comprising:
  • the row voltage generating means simultaneously applies voltages having the polarities indicated by row electrode selection patterns to each of the row electrodes in row electrode subgroups addressed by the row electrode selection means.
  • the row voltage generating means comprises a row electrode selection pattern setting means to output row electrode selection pattern signals corresponding to voltages applied to each row electrodes to be selected, and a row electrode driving means to apply voltages in response to patterns set by the row electrode selection pattern setting means to the each row electrodes addressed by the row electrode selection means.
  • the row electrode selection pattern setting means supplies simultaneously to the row electrode driving means voltage patterns to be applied to each of the row electrodes in row electrode subgroups addressed by the row electrode selection means.
  • the row electrode driving means includes a liquid crystal driving circuit which receives an N number (N: the total number of the row electrodes) of selection signals each corresponding to each of the row electrodes; which receives an N number of voltage setting signals each corresponding to each of the row electrodes; and which applies row voltages corresponding to the voltage setting signals to the row electrodes addressed by the selection signals;
  • the row electrode selection means includes a selection signals parallel output device which renders each of the selection signals corresponding to each of the selected row electrodes to be active and renders each of the selection signals corresponding to each of the non-selected row electrodes to be non-active whereby each of the selection signals is supplied to the liquid crystal driving circuit;
  • the row electrode selection pattern setting means includes a voltage setting signal parallel output device to supply, as voltage setting signals, the corresponding data in the row electrode selection pattern signals corresponding to the each selected row electrodes to the liquid crystal driving circuit.
  • Each of the parallel output devices supplies, as a batch, information indicative of row electrodes which form row electrode subgroups to be selected and information indicative of voltage patterns to be applied to the row electrodes, to the liquid crystal driving circuit.
  • the number of parallel outputs from the selection signal parallel output device is equal to the number of parallel outputs from the voltage setting signal parallel output device.
  • each of the parallel output devices has the same number of stages so that the determination and control of the row electrode selection patterns can be further simplified.
  • the number of the parallel outputs from the selection signal parallel output device and the number of the parallel outputs from the voltage setting signal parallel output device are equal to the total number N of the row electrodes.
  • each of the parallel output devices has the same number of spaces N so that the determination and control of the shift electrodes selection patterns can be further simplified.
  • the selection signal parallel output device includes a latch circuit which latches selection pattern signals based on selection signals to be supplied to the liquid crystal driving circuit, by means of latch pulses which are in synchronism with a timing for switching the selection of a group consisting of the simultaneously selected row electrodes, whereby the latched selection signal patterns are outputted to the liquid crystal driving circuit
  • the voltage setting signal parallel output device includes a latch circuit which latches the row electrode selection pattern signals by means of the latch pulses to output the latched signals to the liquid crystal driving circuit.
  • the latch circuit latch information which makes the selection of the row electrodes in the row electrode subgroups to be selected active, and latch information which makes the selection of other row electrodes non-active whereby information indicative of the selection and non-selection with respect to all row electrodes is supplied to the liquid crystal driving circuit.
  • the selection signal parallel output device includes a shift register which shifts data indicative of an active period of the selection signals and which has a tap output for each stage connected to the latch circuit
  • the voltage setting signal parallel output device includes a shift register which shifts a train of the row electrode selection patterns and which has a tap output for each stage connected to the latch circuit
  • the shift registers successively shift the selection signal patterns so that the information which makes the selection of the row electrodes in the row electrode subgroups to be selected active, is latched by the latch circuits at a latch timing.
  • the frequency of a shift clock to be supplied to the shift register of the voltage setting signal parallel output device is higher than the frequency of a shift clock to be supplied to the shift register of the selection signal parallel output device.
  • the shift register of the voltage setting signal parallel output device shifts the data at a speed higher than that of the shift register for shifting the selection signal patterns and supplies different patterns from those applied to a row electrode subgroup, to the next row electrode subgroup.
  • the selection signal parallel output device has parallel outputs whose number is natural number times as M where M is the number of groups consisting of the simultaneously selected row electrodes, and the voltage setting signal parallel output device has parallel outputs whose number is natural number times as L where L is the number of row electrodes which form each groups.
  • the voltage setting signal parallel output device has parallel outputs whose number is based on the number L of simultaneously selected row electrodes
  • the selection signal parallel output devices has parallel outputs whose number is based on the number M of the row electrode subgroups. Accordingly, the size of each of the parallel output devices can be small.
  • the selection signal parallel output device has an M number of parallel outputs
  • the voltage setting signal parallel output device has an L number of parallel outputs
  • the voltage setting signal parallel output device has parallel outputs whose number is equal to an L number of the simultaneously selected row electrodes
  • the selection signal parallel output device has parallel outputs whose number is equal to an M number of the row electrode subgroups. Accordingly, the size of each of the parallel output devices can be small.
  • the voltage setting signal parallel output device includes a latch circuit which latches the row electrode selection pattern signals by means of latch pulses which are in synchronism with a timing of switching the selection of the groups consisting of the simultaneously selected row electrodes whereby the latched signals are outputted to the liquid crystal driving circuit.
  • the latch circuit latches the row electrode selection patterns to be applied to a row electrode subgroup when the row electrode subgroup is selected, and the latched row electrode selection patterns are supplied to the liquid crystal driving circuit.
  • the voltage setting signal parallel output device includes a shift register which shifts a train of the row electrode selection patterns and which has a tap output for each stage connected to the latch circuit.
  • the shift register shifts row electrode selection patterns formed in series so that row electrode selection patterns to be applied to a row electrode subgroup are latched at a latch timing of the latch circuit.
  • the selection signal parallel output device includes a shift register which shifts data indicative of an active period of the selection signals by means of latch pulses which are in synchronism with a timing of switching the selection of the groups consisting of the simultaneously selected row electrodes, and which supplies, as a selection signal for each groups, a tap output for each stage to the liquid crystal driving circuit.
  • the selection signal parallel output device makes the output corresponding to a row electrode subgroup active so that the liquid crystal driving circuit can select row electrodes contained in a row electrode subgroup when the row electrode subgroup is selected.
  • the selection signal parallel output device includes a latch circuit which latches selection signal patterns based on selection signals to be supplied to the liquid crystal driving circuit, by means of latch pulses which are in synchronism with a timing for switching the selection of groups consisting of simultaneously selected row electrodes, whereby the latched selection signal patterns are outputted to the liquid crystal driving circuit.
  • the latch circuit latches the information which makes the selection of the row electrode subgroup active and information which makes another row electrode subgroup non-active when the row electrode subgroup is selected, whereby the latched information is supplied to the liquid crystal driving circuit.
  • the selection signal parallel output device includes a shift register which shifts data indicative of an active period of the selection signals by shift pulses having a period equal to a period for selecting and switching a group consisting of simultaneously selected row electrodes, and supplies the tap output of each stage of the register to the latch circuit.
  • the shift register successively shifts the selection signal patterns so that the information which makes the selection of row electrode subgroups to be selected active is latched by the latch circuit at a latch timing.
  • Figure 1 is a block diagram showing the construction of a row voltage generating circuit in the liquid crystal display apparatus according to the first embodiment of the present invention.
  • a shift register la has an N number of stages (N: the number of all row electrodes).
  • the shift register la shifts data a which are formed by arranging in series each row electrode selection pattern corresponding to each selection voltage vector according to the timing of shift clock pulses (CP).
  • CP shift clock pulses
  • An example of the row electrode selection pattern is explained with reference to Figure 9. In a matrix composed of +1 and -1 as elements, the row electrode selection pattern is such a pattern shown by each column in the matrix wherein the element of -1 is replaced by 0, for instance.
  • a latch circuit 2a having a bit width of N bits latches outputs generated at each stage of the shift register 1a, and supplies each of the outputs to each a input terminal of a liquid crystal driving circuit 3 having an N number of outputs.
  • a shift register 1b has an N number of stages (N: the number of all row electrodes).
  • the shift register 1b shifts data b which are active in a selection period of row electrodes, according to the timing of CP.
  • a latch circuit 2b having a bit width of N bits latches outputs generated from each of the stages of the shift register 1b, and supplies each of the outputs to each b input terminal of the liquid crystal driving circuit 3. Namely, selection signal patterns are supplied from the latch circuit 2b to the liquid crystal driving circuit 3.
  • the n th tap output of the latch circuits 2a, 2b corresponds to the n th row electrode.
  • the liquid crystal driving circuit 3 is supplied with voltages of +V r , 0, -V r .
  • the liquid crystal driving circuit 3 determines row voltages to be any of +V r , 0, and -V r depending on a combination of input data a and b.
  • a liquid crystal element is connected to the output side of the liquid crystal driving circuit 3 although the liquid crystal element is not shown in Figure 1.
  • L does not correspond to a value multiplied by L.
  • an output On (n: IN) from the liquid crystal driving circuit 3 contains a dummy output.
  • a column voltage generating circuit applies to each of the column electrodes voltages based on orthogonal conversion signals which are obtained by converting, with an orthogonal function, picture signals corresponding to the positions of simultaneously selected row electrodes on a display element.
  • a row electrode selection means is constituted by the shift register 1b and the latch circuit 2b.
  • a row voltage generating means is constituted by the shift register la, the latch circuit 2a and the liquid crystal driving circuit 3.
  • the latch circuit 2b is shown as an example of a selection signal parallel output device, and the latch circuit 2a is shown as an example of a voltage setting signal parallel output device.
  • Figure 8 shows signal waveforms of row electrodes R1-R9 among row electrodes Rn. Assuming that a group of R1-R3, a group of R4-R6 and a group R7-R9 are respectively selected simultaneously. Each row electrode subgroup includes three row electrodes. In this embodiment, when the first row electrode subgroup through the M th row electrode subgroup are scanned once (hereinbelow, referred to as one frame), the same row electrode selection pattern is set for each of the row electrode subgroups. When the scanning is conducted for the frame predetermined times, a display sequence for picture is finished.
  • the period of the latch pulses supplied to the latch circuits 2a, 2b is equal to a period of selecting each row voltage.
  • an L (3 in this embodiment) clock pulses are produced.
  • the data b has an active section (a high level section) which corresponds to the selection time.
  • the data a corresponding to the row electrode selection pattern has an active section which corresponds to three periods of clock pulses.
  • the data a are shifted in the shift register la by the clock pulses and the data b are shifted in the shift register 1b by the clock pulses.
  • One latch pulse is produced each time when an L number of clock pulses are produced.
  • the latch circuit 2a latches each data in the shift register 1a.
  • the latch circuit 2b latches each data in the shift register 1b.
  • An N number of outputs of the latch circuit 2a are inputted to the corresponding number of a input terminals of the liquid crystal driving circuit 3.
  • An N number of outputs of the latch circuit 2b are inputted to the corresponding b input terminals of the liquid crystal driving circuit 3.
  • V0 or V2 indicates 0, and V1 and V3 indicate -V r and +V r respectively.
  • the liquid crystal driving circuit 3 is composed of a level shifter, an analogue switch and so on.
  • the n th a input and the n th b input correspond respectively to a voltage applied to the n th row electrode. Namely, the liquid crystal driving circuit 3 makes the voltage to the n th row electrode to be a voltage corresponding to a non-selection state when the n th b input is in a low level.
  • n th b input When the n th b input is in a high level, a voltage corresponding to the polarity of the n th a input is applied to the n th row electrode. For instance, when the a input is in a high level, a voltage +V r is applied. On the other hand, when in a low level, a voltage -V r is applied.
  • the shift registers la, 1b have respectively an L number of stages, all row electrodes are selected once when the N number of clock pulses are inputted. During the selection of the row electrodes, the same row electrode selection pattern is applied to each of the row electrode subgroups.
  • the row electrode selection pattern is changed, namely, the data a are changed to execute the above-mentioned processing.
  • the data a are formed by, for instance, a table in which plural kinds of row electrode selection patterns are set, a selection circuit to select one among the row electrode selection patterns at the time of initiating each cycle and a P-S converter to convert a selected row electrode selection pattern into serial signals.
  • N the number of outputs of the latch circuits 2a, 2b.
  • a value other than N may be used. For instance, in a case of N/2, a single display picture may be divided into two separate portions to be driven.
  • the latch circuits 2a, 2b are used as parallel output devices.
  • the latch circuits 2a, 2b may be omitted while the number of stages of the shift registers 1a, 1b is N ⁇ L, and the i x L th (i: 1-N) tap output is supplied to the liquid crystal driving circuit 3.
  • the row electrode selection patterns and the selection signal patterns may be set in the latch circuits 2a, 2b without using the shift registers 1a, 1b. For instance, a selection signal pattern for making only the first row electrode subgroup active and a row electrode selection pattern corresponding to the first row electrode subgroup, a selection signal pattern for making only the second row electrode subgroup active and a row electrode selection pattern corresponding to the second row electrode subgroup, ..., a selection signal pattern for making only the M th row electrode subgroup active and a row electrode selection pattern corresponding to the M th row electrode subgroup may be stored in a ROM whereby the selection signal patterns and the row electrode selection patterns in the ROM are read by using address signals obtained by counting the clock pulses. In this case, consumption power can be reduced because the clock pulses having a high frequency are unnecessary. Further, the row electrode selection patterns to be applied to each row electrode subgroups in one frame can be optionally determined.
  • FIG. 3 is a block diagram showing the construction of a row voltage generating circuit according to a second embodiment of the present invention.
  • the frequency of shift clock signals CPa supplied to the shift register la is higher than the frequency of shift clock signals CPb supplied to the shift register 1b. Accordingly, a row electrode selection pattern which is different from the row electrode selection pattern set when a row electrode subgroup has been selected just before the one frame can be set for a row electrode subgroup selected this time.
  • a group of R1-R3, a group of R4-R6, a group of R7-R9 and so on are those groups to be simultaneously selected.
  • Each of the row electrode subgroups includes three row electrodes.
  • the frequency of the shift clock signals CPa is twice as high as the frequency of the shift clock signals CPb as shown in Figure 5.
  • an L number (3 in the second embodiment) of the shift clock signals CPb are produced in one period of latch pulse signals.
  • the operations of the shift registers 1a, 1b, the latch circuits 2a, 2b and the liquid crystal driving circuit 3 are the same as those in the first embodiment except that a series of data are successively inputted so that a row electrode selection pattern to be applied to the m th row electrode subgroup appears at each corresponding stage of the shift register la when a high level is provided to each b input terminal in the liquid crystal driving circuit 3 corresponding to the m th row electrode subgroup.
  • Such data a can be formed by, for instance, a table in which a series of data are set in parallel, a read circuit for reading the data in the table and a P-S converter.
  • the row electrode selection patterns can be shifted each time when a row electrode subgroup is selected.
  • N the number of outputs of the latch circuits 2a, 2b.
  • a value other than N may be used. For instance, in a case of N/2, a single display picture may be divided into two independent portions to be driven.
  • latch circuits 2a, 2b are used as parallel output devices.
  • another construction may be used.
  • shift registers 1a, 1b having an N ⁇ L number of stages may be used while the latch circuits 2a, 2b are omitted, and the n ⁇ L th (n: 1-N) tap output is supplied to the liquid crystal driving circuit 3.
  • the row electrode selection patterns and the selection signal patterns may be set in the latch circuits 2a, 2b while the shift registers 1a, 1b are omitted.
  • FIG. 6 shows an embodiment of a row voltage generating circuit in which two row voltage generating circuits shown in Figure 1, or Figure 3 are used.
  • clock pulse signals CPa, CPb are inputted in placed of clock pulses CP.
  • Data a shift clock pulses (CP or CPa, CPb) and latch pulses LP are commonly inputted to two row voltage generating circuits 5a, 5b.
  • a selection signal pattern is inputted as data b , to the shift register 1b (reference to Figure 1, or Figure 3) of the row voltage generating circuit 5a.
  • the output of the data b of the shift register is supplied to the input of the data b of the row voltage generating circuit 5b.
  • the row voltage generating circuit of this embodiment operates in the same manner as in the embodiments described above, and a display panel having row electrodes whose number is larger than N but smaller than 2N can be driven.
  • the number of row electrodes to be driven can be further increased. In this case, the number of row electrodes to be simultaneously selected is L.
  • FIG. 7(a) shows an example of construction wherein the number of row electrodes to be simultaneously selected is increased to 2L by using two row voltage generating circuits shown in Figure 1, or Figure 3.
  • clock pulse signals CPa, CPb are inputted in place of the clock pulses CP.
  • Data b shift clock pulses (CP or CPa, CPb) and latch pulses (LP) are commonly inputted to two row voltage generating circuits 5c, 5d.
  • a row electrode selection pattern is inputted as data a .
  • a different row electrode selection pattern is inputted as data a' .
  • An input of the data a may be the same as an input of the data a' .
  • the same operation as in the case of above-mentioned embodiment is obtainable, and the display panel can be driven while the row electrodes of a 2L number are simultaneously selected.
  • row electrodes of 3L, 4L, ... can be simultaneously selected.
  • the liquid crystal display apparatus comprises a row electrode selection means to successively address each simultaneously selected row electrodes and a row voltage generating means to apply voltages based on the corresponding data in row electrode selection pattern signals to the each row electrodes selected by the row electrode selecting means. Accordingly, in a case of driving the liquid crystal display apparatus by simultaneously selecting an L number of row electrodes, a row electrode driving circuit having a simpler structure can be realized in comparison with a case of controlling respectively voltage polarities applied to each N number of row electrodes.
  • the liquid crystal display apparatus of the present invention to include a row voltage generating circuit which comprises a row electrode pattern setting means to output row electrode selection pattern signals corresponding to voltages applied to each row electrodes selected, and a row electrodes driving means to apply voltages based on patterns determined by the row electrode pattern setting means, to the each row electrodes addressed by the row electrode selection means, it is possible to easily set desired voltage patterns to be applied to an L number of simultaneously selected row electrodes.
  • the liquid crystal display apparatus can easily determine voltage patterns to be applied to each row electrodes to be selected and the other each row electrodes.
  • the construction for simultaneously selecting row electrodes can be simplified.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a latch circuit which latches selection signal patterns based on selection signals supplied to the liquid crystal driving circuit to output the latched patterns to the liquid crystal driving circuit, and a latch circuit which latches the row electrode pattern signals to output the latched signals to the liquid crystal driving circuit, the row electrode selection patterns to be applied to each row electrodes to be selected and the other each row electrodes can be certainly supplied to the liquid crystal driving circuit.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a shift register for shifting data indicative of an active period of selection signals and a shift register for shifting a train of the row electrode selection patterns, data can be supplied with a small bit width at an input time.
  • the above structure can reduce the number of input pins of a driver.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus so that the frequency of a shift clock to be supplied to the shift register in the voltage setting signal parallel output device is higher than the frequency of a shift clock to be supplied to the shift register in the selection signal parallel output device, a voltage pattern which is different from a voltage pattern applied to the row electrodes constituting a row electrode subgroup can be easily applied to the row electrodes constituting a row electrode subgroup to the selected next.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a voltage setting signal parallel output device having parallel outputs whose number is as natural number times as the number of simultaneously selected row electrodes L, and a selection signal parallel output device having parallel outputs whose number is as natural number times as the number of row electrode subgroups M, desired voltage patterns can be formed for an L number of row electrodes which are simultaneously selected, while the construction is more simplified. Further, it is possible to drive a plurality of pictures.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a voltage setting signal parallel output device having parallel outputs which are equal to the number of simultaneously selected row electrodes L and a selection signal parallel output device having parallel outputs which are equal to the number of row electrode subgroups M, desired voltage patterns can be formed for an L number of row electrodes which are simultaneously selected, while the construction is more simplified.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a latch circuit which latches row electrode pattern signals by latch pulses in synchronism with a timing to select and switch groups consisting of simultaneously selected row electrodes, and outputs the latched signals to the liquid crystal driving circuit, row electrode selection patterns to be applied to row electrode subgroups can be certainly supplied to the liquid crystal driving circuit.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a shift register for shifting a train of row electrode selection patterns, influence of noises of the liquid crystal display element to a device for setting the row electrode selection patterns can be reduced.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a shift register which shifts data indicative of an active period of selection signals by latch pulses, and supplies the latched data to the liquid crystal driving circuit, influence of noises of the liquid crystal element to a device for setting the row electrode selection patterns can be reduced.
  • the liquid crystal display apparatus By constructing the liquid crystal display apparatus to include a latch circuit which latches selection signal patterns by latch pulses, and outputs the latched signal patterns to liquid crystal driving circuit, information indicative of row electrode subgroups to be selected can be certainly supplied to the liquid crystal driving circuit.
  • the liquid crystal display apparatus by constructing the liquid crystal display apparatus to include a shift register which shifts data indicative of an active period of selection signals, and supplies the shifted data to a latch circuit, influence of noises of the liquid crystal display element to a device for setting the row electrode setting patterns can be reduced.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (5)

  1. Dispositif d'affichage à cristaux liquides comprenant :
    un élément à cristaux liquides conçu pour être commandé en commandant plusieurs électrodes de ligne et électrodes de colonne, dans lequel plusieurs électrodes de ligne sont sélectionnées simultanément,
    un circuit générateur de tension de colonne pour appliquer à chaque électrode de colonne des tensions basées sur des signaux de conversion orthogonale qui sont obtenus en convertissant, en utilisant une fonction orthogonale, des signaux d'image correspondant aux positions des électrodes de ligne sélectionnées simultanément de l'élément d'affichage, et
    un circuit générateur de tension de ligne (5) pour appliquer des tensions basées sur des signaux de modèle de sélection d'électrode de ligne formés avec une fonction orthogonale aux électrodes de ligne sélectionnées simultanément,
       dans lequel le circuit générateur de tension de ligne (5) comprend :
    un moyen de sélection d'électrode de ligne pour adresser de façon séquentielle chaque électrode de ligne sélectionnée simultanément, et
    un moyen générateur de tension de ligne pour appliquer des tensions en réponse aux données correspondantes dans les signaux de modèle de sélection d'électrode de ligne à chaque électrode de ligne sélectionnée par le moyen de sélection d'électrode de ligne ;
    dans lequel le moyen générateur de tension de ligne comprend un moyen d'établissement de modèle de sélection d'électrode de ligne pour sortir des signaux de modèle de sélection d'électrode de ligne correspondant à des tensions appliquées à chaque électrode de ligne devant être sélectionnée, et un moyen de commande d'électrode de ligne pour appliquer des tensions en réponse à des modèles établis par le moyen d'établissement de modèle de sélection d'électrode de ligne à chaque électrode de ligne adressée par le moyen de sélection d'électrode de ligne ;
    dans lequel le moyen de commande d'électrode de ligne comprend un circuit de commande à cristaux liquides qui reçoit un nombre N, qui est égal au nombre total des électrodes de ligne, de signaux de sélection correspondant chacun à chacune des électrodes de ligne, qui reçoit un nombre N de signaux de réglage de tension correspondant chacun à chacune des électrodes de ligne, et qui applique des tensions de ligne correspondant aux signaux de réglage de tension aux électrodes de ligne déterminées par les signaux de sélection ;
    dans lequel le moyen de sélection d'électrode de ligne comprend un dispositif de sortie parallèle de signal de sélection qui rend actif chacun des signaux de sélection correspondant à chacune des électrodes de ligne sélectionnées et qui rend non-actif chacun des signaux de sélection correspondant à chacune des électrodes de ligne non-sélectionnées, ce par quoi chacun des signaux de sélection est délivré au circuit de commande à cristaux liquides ;
    dans lequel le moyen d'établissement de modèle de sélection d'électrode de ligne comprend un dispositif de sortie parallèle de signal de réglage de tension pour délivrer, sous la forme de signaux de réglage de tension, les données correspondantes dans les signaux de modèle de sélection d'électrode de ligne correspondant à chaque électrode de ligne sélectionnée au circuit de commande à cristaux liquides ;
       caractérisé en ce que le nombre de sorties parallèles provenant du dispositif de sortie parallèle de signal de sélection est égal au nombre de sorties parallèles provenant du dispositif de sortie parallèle de signal de réglage de tension.
  2. Dispositif d'affichage à cristaux liquides selon la revendication 1, dans lequel le nombre des sorties parallèles provenant du dispositif de sortie parallèle de signal de sélection et le nombre des sorties parallèles provenant du dispositif de sortie parallèle de signal de réglage de tension sont égaux au nombre total N des électrodes de ligne.
  3. Dispositif d'affichage à cristaux liquides selon la revendication 1, dans lequel
    le dispositif de sortie parallèle de signal de sélection comprend un circuit à verrouillage qui verrouille des signaux de modèle de sélection basés sur des signaux de sélection devant être délivrés au circuit de commande à cristaux liquides, au moyen d'impulsions de verrouillage qui sont en synchronisme avec un cadencement pour commuter la sélection d'un groupe composé des électrodes de ligne sélectionnées simultanément, ce par quoi les modèles de signal de sélection verrouillé sont sortis vers le circuit de commande à cristaux liquides, et dans lequel
    le dispositif de sortie parallèle de signal de réglage de tension comprend un circuit à verrouillage qui verrouille les signaux de modèle de sélection d'électrode de ligne au moyen des impulsions de verrouillage pour sortir les signaux verrouillés vers le circuit de commande à cristaux liquides.
  4. Dispositif d'affichage à cristaux liquides selon la revendication 3, dans lequel
    le dispositif de sortie parallèle de signal de sélection comprend un registre à décalage qui décale des données indiquant une période active des signaux de sélection et qui a une sortie de prise pour chaque étage connecté au circuit à verrouillage, et dans lequel
    le dispositif de sortie parallèle de signal de réglage de tension comprend un registre à décalage qui décale un train de modèles de sélection d'électrode de ligne et qui a une sortie de prise pour chaque étage connecté au circuit à verrouillage.
  5. Dispositif d'affichage à cristaux liquides selon la revendication 4, dans lequel La fréquence d'une horloge à décalage devant être délivrée au registre à décalage du dispositif de sortie parallèle de signal de réglage de tension est supérieure à la fréquence d'une horloge à décalage devant être délivrée au registre à décalage du dispositif de sortie parallèle de signal de sélection.
EP94104742A 1993-03-24 1994-03-24 Dispositif d'affichage à cristaux liquides Expired - Lifetime EP0617399B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP89268/93 1993-03-24
JP8926893 1993-03-24
JP8927593 1993-03-24
JP89275/93 1993-03-24

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EP0617399A1 EP0617399A1 (fr) 1994-09-28
EP0617399B1 true EP0617399B1 (fr) 1998-08-26

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KR (1) KR940022149A (fr)
CN (1) CN1093176A (fr)
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621425A (en) * 1992-12-24 1997-04-15 Seiko Instruments Inc. Liquid crystal display device
US6037919A (en) * 1994-10-18 2000-03-14 Intermec Ip Corp. LCD with variable refresh rate as a function of information per line
JP3538841B2 (ja) 1994-11-17 2004-06-14 セイコーエプソン株式会社 表示装置及び電子機器
JPH08179731A (ja) * 1994-12-26 1996-07-12 Hitachi Ltd データドライバ、走査ドライバ、液晶表示装置及びその駆動方式
KR100214484B1 (ko) * 1996-06-07 1999-08-02 구본준 순차 및 이중스캐닝방식을 위한 티에프티-엘씨디구동회로
JP3509398B2 (ja) * 1996-06-28 2004-03-22 富士通株式会社 画像表示方法及び装置
JP2002123208A (ja) 2000-10-13 2002-04-26 Nec Corp 画像表示装置およびその駆動方法
CN100589167C (zh) * 2006-09-20 2010-02-10 比亚迪股份有限公司 液晶驱动***中列驱动电路的实现方法及专用列解码电路

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Publication number Priority date Publication date Assignee Title
US5485173A (en) * 1991-04-01 1996-01-16 In Focus Systems, Inc. LCD addressing system and method
EP0522510B1 (fr) * 1991-07-08 1996-10-02 Asahi Glass Company Ltd. Méthode de commande d'un élément d'affichage à cristal liquide
JP3373226B2 (ja) * 1991-07-08 2003-02-04 旭硝子株式会社 液晶表示素子の駆動方法

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CN1093176A (zh) 1994-10-05
DE69412677D1 (de) 1998-10-01
DE69412677T2 (de) 1999-02-11
KR940022149A (ko) 1994-10-20
EP0617399A1 (fr) 1994-09-28

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