EP0470839A2 - Substrat céramique à conducteurs contenant de l'argent - Google Patents

Substrat céramique à conducteurs contenant de l'argent Download PDF

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Publication number
EP0470839A2
EP0470839A2 EP91307283A EP91307283A EP0470839A2 EP 0470839 A2 EP0470839 A2 EP 0470839A2 EP 91307283 A EP91307283 A EP 91307283A EP 91307283 A EP91307283 A EP 91307283A EP 0470839 A2 EP0470839 A2 EP 0470839A2
Authority
EP
European Patent Office
Prior art keywords
ceramic
silver
wiring
ceramic substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91307283A
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German (de)
English (en)
Other versions
EP0470839B1 (fr
EP0470839A3 (en
Inventor
Keiichiro C/O Nec Corporation Kata
Yuzo C/O Nec Corporation Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
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NEC Corp
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Filing date
Publication date
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Publication of EP0470839A3 publication Critical patent/EP0470839A3/en
Application granted granted Critical
Publication of EP0470839B1 publication Critical patent/EP0470839B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • the present invention relates to a ceramic substrate, and, more particularly, to a ceramic substrate for mounting thick-film hybrid ICs or high speed LSI elements.
  • Substrate materials can be roughly classified as belonging to an organic resin group, a metal group and a ceramic group. Amongst these, the ceramic group is frequently used in fields in which high quality, high reliability and long duration are required. Amongst ceramic materials, alumina has been widely used in view of its electrical characteristics and its cost.
  • the conductor material of the wiring layer is limited to metals such as tungsten or molybdenum, whose specific resistance is relatively high, since it is necessary to heat them to temperatures as high as the sintering temperature of alumina i.e. of 1500 to 1600°C.
  • a low sintering temperature ceramic which is a composite material of glass and a host ceramic. Since this composite material has a low melting point, a metal material may be used as the wiring layer whose specific resistance is low and which material cannot be sintered simultaneously with the sintering of ceramic material.
  • a metal material such as gold, silver and copper, does not occupy a large part of the hybrid IC substrate market in view of the high cost of gold and the instability against oxidation of copper and thus it can be said that silver or silver containing material is mainly used as a wiring material.
  • a wiring layer made of silver, or of material containing silver has a migration problem, and to cope with this problem a silver alloy with palladium, or the like, has been used.
  • the proportion of silver to palladium has been usually selected as 80 : 20 in view of the requirements of anti-migration, solder-wettability, solder loss, adhesiveness and resistance value, it has been desired to use a conductive material containing a high silver ratio in order to lower the resistance value and improve the solder wettability and ageing characteristics. Solder loss, bad matching with cross over glass, degradation of solder wettability due to surface galvanization and silver migration can be minimised in various ways and thus there is a high possibility that such a material may be used in future developments.
  • a multi-layered glass ceramic substrate in which the wiring length can be reduced and a high density wiring is possible is of interest for use in multi-chip packages which are used in large, high speed computers and in which a large number of LSI chips are mounted on a single substrate.
  • a wiring material in such a multi-layered glass ceramic substrate the above-mentioned silver or material containing silver may be used.
  • the size of the substrate in order to further increase the mounting density, there is a tendency for the size of the substrate to become large. In order to sinter such large substrates in the same way as those of the conventional size, it is necessary to make the sintering time longer. However, this may increase the diffusion of silver from the wiring into the glass substrate during sintering process, with the resulting problem that there is a considerable degradation in various characteristics of wiring made of silver or of material containing silver.
  • a feature of the present invention is the provision of a substrate having wiring which hardly changes its characteristics and which is of a silver series.
  • a ceramic substrate which comprises a ceramic body having a major face.
  • the ceramic body contains silver of 0.1 to 2.5 percent by weight.
  • a wiring layer is formed on the major face of the ceramic body and is made of silver and of material containing silver.
  • a ceramic substrate includes a ceramic body which is constituted by a plurality of ceramic insulating layers stacked upon each other.
  • Each of the ceramic insulating layers contains silver of 0.1 to 2.5 percent by weight and has upper and lower faces.
  • a wiring pattern made of silver or of material containing silver is formed on the upper and/or the lower faces of the ceramic insulating layers such that one group of wiring layers of the wiring pattern is positioned within the ceramic body.
  • the ceramic body or the ceramic insulating layer consists essentially of a main material and the silver
  • the main material may consist essentially of ceramic, such as alumina (aluminium oxide, Al2O3), and glass, such as borosilicate series lead glass, or of quartz glass and cordierite and borosilicate glass.
  • the silver is contained in the ceramic body in particles, each particle having preferably 1 to 5 ⁇ m diameter, with the silver being dispersed substantially uniformly in the main material such that at every portion of the ceramic body or ceramic insulating layer, the percentage ratio of the silver weight to the total weight of the main material and the silver is 0.1% or more and 2.5% or less.
  • the ceramic substrate of the preferred embodiment of the present invention includes a ceramic which contains between 0.1 - 2.5% by weight of silver, any diffusion of the conductive material containing silver as its main constituent and forming the wiring to the ceramic insulating layer of the substrate is restricted during a sintering process, resulting in more stable wiring conductor characteristics after sintering.
  • Fig. 1 is a cross-sectional view of a substrate.
  • the ceramic substrate includes a ceramic body having six ceramic insulating layers 1 stacked upon each other, and a wiring pattern 2.
  • the wiring pattern 2 is selectively formed on the upper faces 10 and on the lower faces 9 of respective ceramic insulating layers 1 and extends through holes 11 formed in the layers 1 to connect electrically the respective wiring layers of the pattern 2 on the upper and lower sides or faces of the layers 1.
  • the wiring pattern 2 which is in a 3-dimensional form, further includes first electrodes 6 which are on the upper face 10′ of the top ceramic insulating layer 1 and which are designed to be bonded to a semiconductor element 4, such as an IC or an LSI chip by means of solder 12, and second electrodes which are on the lower face 9′ of the bottom ceramic insulating layer 1 and which are designed to be bonded to terminal leads 5, including input and output terminal leads.
  • the ceramic insulating layers 1 contain fine silver particles 3, represented by black dots or circles of 0.1 - 2.5% silver by weight.
  • a ceramic substrate which is prepared using binary powder material of alumina and lead borosilicate glass as the raw materials. Since the sintering temperature of this composite material is as low as 900°C, a silver-containing paste can be used as the conductive material of the wiring to be sintered simultaneously with the substrate. As an example, an alloy of silver and palladium was used in one case.
  • ceramic and glass as the main material in that its dielectric properties, (e.g. constant) is lower than that of alumina, that its thermal expansion coefficient is substantially matched to that of elements of Si, that its mechanical strength is improved by anorthite phase deposition due to the reaction between alumina and glass, and that it restricts the migration of silver.
  • raw glass powder is crushed to control the particle size and then mixed with alumina in the proportion of 45% of glass to 55% of alumina, both by weight. Further, after adding a predetermined amount of fine silver particles having an average size of 1 - 5 ⁇ m to the mixture and mixing it therewith, it is mixed with an organic vehicle to obtain a slurry mixture. Then, a green sheet having a desired thickness is produced by using the slip casting film forming method and a shaped product is prepared with the formation of through-holes, with a silver-palladium conductor pattern used as a wiring pattern printing and through-hole filling printing, with lamination and with thermal pressing. The shaped product is sintered after the removal of the binder, resulting in a multi-layered wiring substrate.
  • the ratio of fine silver particles 3 to be added is limited to the range 0.1 - 2.5% by weight.
  • the amount of such silver particles has to be enough to prevent silver from diffusing into the glass phase forming the insulating layer during the sintering process.
  • the characteristics of the insulating layer particularly its insulating characteristics, are degraded rapidly.
  • the effect of fine silver particles on the characteristics of the silver-containing conductor and on the insulating layer have been studied over a range in which the ratio of fine silver particles added was varied from 0 to 10% by weight of silver and 95% by weight.
  • the specific resistances of conductors containing 100% by weight of silver and 95% by weight of silver were calculated from the resistance and cross sectional area values after sintering and were selected as the conductor characteristics; shrinkage and density of the sintered body were calculated on the Archimedean principle; the bending strength was calculated according to the three-point bending method; dielectric constant and dielectric loss were measured at 1 MHz; the insulation resistance was measured when a voltage of 50 V was applied; and the breakdown voltage and the average thermal line expansion coefficient in a range from room temperature to 350°C were selected as the insulating layer characteristics.
  • Table 1 In the case in which no fine silver particle was added to the insulating layer, the specific resistance of the conductor varied considerably and was unstable.
  • the ratio of added fine silver particles with which the characteristics of the silver-containing conductor forming the wiring were stabilized without affecting the characteristics of the insulating layer adversely are defined as being within a range from 0.1 to 2.5% by weight.
  • a ternary ceramic including quartz glass, cordierite and borosilicate glass is used as the raw material for a ceramic substrate and this embodiment will be described below. Since the sintering temperature of this composite material is as low as 900°C, it is possible to use a silver-containing paste as both a sintering conductor and as a wiring layer, simultaneously. In a particular example, an alloy of silver and palladium was used, as in the first embodiment described above. Further, this material has dielectric properties (e.g. a constant) as low as 4.4, which is advantageous in improving transmission speeds, and its thermal expansion coefficient is well matched to that of an Si element. Its anti-bending strength is relatively high and is 1600 kg/cm.
  • the conductor of the wiring layer contains silver as a main constituent and the ceramic insulating layer contains fine silver particles in the range of 0.1 to 2.5% by weight, the diffusion of silver contained in the conductor into the ceramic insulating layer during the sintering process is restricted and thus the characteristics of the wiring conductor after sintering are stabilized.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
EP91307283A 1990-08-08 1991-08-08 Substrat céramique à conducteurs contenant de l'argent Expired - Lifetime EP0470839B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2209484A JPH0719964B2 (ja) 1990-08-08 1990-08-08 銀系配線セラミック基板
JP209484/90 1990-08-08

Publications (3)

Publication Number Publication Date
EP0470839A2 true EP0470839A2 (fr) 1992-02-12
EP0470839A3 EP0470839A3 (en) 1993-05-26
EP0470839B1 EP0470839B1 (fr) 1995-01-25

Family

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Application Number Title Priority Date Filing Date
EP91307283A Expired - Lifetime EP0470839B1 (fr) 1990-08-08 1991-08-08 Substrat céramique à conducteurs contenant de l'argent

Country Status (4)

Country Link
US (1) US5292574A (fr)
EP (1) EP0470839B1 (fr)
JP (1) JPH0719964B2 (fr)
DE (1) DE69106978T2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4234205B2 (ja) * 1996-11-08 2009-03-04 ダブリュ．エル．ゴア アンド アソシエイツ，インコーポレイティド 電子アセンブリおよび電子物品内でのヴァイアのインダクタンスを低減する方法
JP3695893B2 (ja) * 1996-12-03 2005-09-14 沖電気工業株式会社 半導体装置とその製造方法および実装方法
JP3451868B2 (ja) * 1997-01-17 2003-09-29 株式会社デンソー セラミック積層基板の製造方法
JPH11171645A (ja) * 1997-12-09 1999-06-29 Hitachi Metals Ltd 電子部品
TW512653B (en) * 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
DE10023360A1 (de) * 2000-05-12 2001-11-29 Epcos Ag Kondensator und Verfahren zu dessen Herstellung
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
DE102006033222B4 (de) * 2006-07-18 2014-04-30 Epcos Ag Modul mit flachem Aufbau und Verfahren zur Bestückung
US7875810B2 (en) * 2006-12-08 2011-01-25 Ngk Spark Plug Co., Ltd. Electronic component-inspection wiring board and method of manufacturing the same
US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
JP6309632B2 (ja) * 2015-01-13 2018-04-11 日本特殊陶業株式会社 セラミック基板の製造方法及びセラミック基板
JP7189047B2 (ja) * 2019-02-22 2022-12-13 日本特殊陶業株式会社 電気検査用基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0016306A1 (fr) * 1979-03-23 1980-10-01 International Business Machines Corporation Procédé pour la fabrication d'un empaquetage multicouche en verre-céramique pour le montage de dispositifs semiconducteurs
US4714687A (en) * 1986-10-27 1987-12-22 Corning Glass Works Glass-ceramics suitable for dielectric substrates
US4748136A (en) * 1986-10-30 1988-05-31 Olin Corporation Ceramic-glass-metal composite

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5024883A (en) * 1986-10-30 1991-06-18 Olin Corporation Electronic packaging of components incorporating a ceramic-glass-metal composite

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0016306A1 (fr) * 1979-03-23 1980-10-01 International Business Machines Corporation Procédé pour la fabrication d'un empaquetage multicouche en verre-céramique pour le montage de dispositifs semiconducteurs
US4714687A (en) * 1986-10-27 1987-12-22 Corning Glass Works Glass-ceramics suitable for dielectric substrates
US4748136A (en) * 1986-10-30 1988-05-31 Olin Corporation Ceramic-glass-metal composite

Also Published As

Publication number Publication date
US5292574A (en) 1994-03-08
JPH0719964B2 (ja) 1995-03-06
EP0470839B1 (fr) 1995-01-25
DE69106978T2 (de) 1995-05-24
DE69106978D1 (de) 1995-03-09
EP0470839A3 (en) 1993-05-26
JPH0492497A (ja) 1992-03-25

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