EP0438469B1 - Circuit permettant l'enregistrement numerique d'une information analogique formee par l'intervalle entre deux etats successifs d'un signal - Google Patents

Circuit permettant l'enregistrement numerique d'une information analogique formee par l'intervalle entre deux etats successifs d'un signal Download PDF

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EP0438469B1
EP0438469B1 EP89911553A EP89911553A EP0438469B1 EP 0438469 B1 EP0438469 B1 EP 0438469B1 EP 89911553 A EP89911553 A EP 89911553A EP 89911553 A EP89911553 A EP 89911553A EP 0438469 B1 EP0438469 B1 EP 0438469B1
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circuit
signal
charge
time interval
circuit arrangement
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EP0438469A1 (fr
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Horst Ziegler
Gerald Riemer
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time
    • G04F10/105—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time with conversion of the time-intervals

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  • the invention relates to a circuit arrangement for the digital detection of analog information in the form of the time interval between two successive states of at least one signal or the amplitude of the signal, according to the preamble of claim 1.
  • a circuit arrangement for recording time intervals, in particular for measuring small time intervals. in the sub-millisecond range, which cannot be determined with conventional digital interval measuring devices or can only be determined with insufficient resolution, comprises an integration capacitor which has a Charging circuit is chargeable to a voltage representing the analog information, and a charge change circuit that changes the voltage of the integration capacitor at a rate of change less than that of the charging circuit.
  • a comparator compares the voltage on the integration capacitor with a predetermined threshold.
  • a counter is also provided, which counts periodic clock pulses during the change in the voltage of the integration capacitor by means of the charge change circuit until the predetermined threshold value is reached.
  • the charge change circuit changes the voltage at the integration capacitor until the threshold value monitored by the comparator is reached.
  • the duration of this voltage change of the integration capacitor by means of the charge change circuit depends on the one hand on predetermined parameters of the circuit arrangement and on the other hand on the value of the integration capacitor voltage representing the analog information.
  • the counting result of the counter represents digital information about the duration of the voltage change and thus also about the value of the analog information.
  • One possibility of improving the resolution in the time interval measurement without increasing the reference clock frequency is to determine the time intervals at the beginning and at the end of the measurement time interval which cannot be precisely determined due to the asynchronism of the measurement and reference clock signals, using a circuit arrangement of the type described above.
  • Such an application of a circuit arrangement for the digital detection of the time interval between two successive states of at least one signal is known from the magazine "Elektronik" volume 7-1988, issue 14 pages 65 to 68.
  • the known circuit arrangement works as an analog interpolator of a time interval measuring system and detects the time interval T 1 between the beginning of a time interval T x to be measured and a subsequent predetermined edge of a periodic reference clock signal.
  • Another analog interpolator detects the time interval T'1 between End of the time interval to be measured and a subsequent predetermined edge of the reference clock signal.
  • the above-mentioned predetermined edges of the reference clock signal include a time interval T m , the length of which corresponds to an integer multiple of the period of the reference clock signal and can therefore be exactly determined by counting the clock periods falling in this clock-synchronous time interval with a counting device. From the information determined with the analog interpolators and the counting device about the time segments. T 1, T 1 and T m , an evaluation device calculates a digital measured value for the measuring time interval T x to be determined, whereby a high time resolution is achieved.
  • the known circuit device comprises an integrating capacitor arranged in an integrator circuit, a charging circuit for charging the integrating capacitor with a constant current of a first charge source during the time interval to be detected T 1 or T 1, a charge changing circuit for discharging the integrating capacitor with the current of a second charge source, and a comparator which compares the voltage across the capacitor with a threshold value corresponding to the discharge state of the capacitor.
  • the first and second charge sources have opposite polarities.
  • the first charge source delivers a constant current that is a thousand times greater than the constant current of the second charge source.
  • the voltage changes at the integration capacitor during the charging and discharging phase are linear, but with different signs.
  • a counter counts periodic clock pulses of the reference clock signal. After the discharge phase, the counting result of the counter represents information about the time interval T 1 or T 1 to be recorded.
  • the known circuit arrangement has in particular the disadvantage that charge sources of opposite polarity are required for charging and discharging the integration capacitor.
  • the comparator requires a negative DC voltage to set the threshold value OV. Good constancy is required for the charging current and the discharging current.
  • the integration capacitor voltage represents the time interval to be detected only incorrectly after the end of the charging phase, while fluctuations in the discharge current have a disruptive influence on the discharge time and thus on the counting result of the counter.
  • the required stabilization of the currents of different signs to predetermined values, which also differ significantly, is associated with a high circuit complexity, which makes the circuit arrangement complicated and expensive.
  • a circuit arrangement for digitally detecting the voltage amplitude of an analog signal is known.
  • This known circuit arrangement works according to the "dual-slope" analog-digital converter method and comprises one Integration capacitor in an integrator circuit with operational amplifier.
  • the input of the integrator circuit is electrically connected to the signal source via a charging circuit during a predetermined integration time interval, as a result of which the integration capacitor is charged to a voltage proportional to the signal voltage to be measured. After the integration time interval has elapsed, the input of the integrator circuit is connected to a reference voltage source with a constant reference voltage in order to discharge the integration capacitor.
  • the capacitor voltage changes linearly with time.
  • a counter counts periodic clock pulses from a reference clock source.
  • a comparator ends the counting process when the voltage on the capacitor has dropped to the value OV. After the discharge phase has expired, the counting result of the counter represents digital information about the signal voltage to be measured.
  • a disadvantage of this known analog-digital converter is that a very good constant reference voltage is required for the controlled discharge process of the integration capacitor and thus for a high accuracy of the voltage measurement, the sign of which is opposite to the sign of the measuring voltage.
  • the known circuit arrangement therefore requires at least one positive and one negative voltage source, each with a very good constant output voltage, and a switching device which reverses the polarity of the reference voltage.
  • the invention has for its object to provide a circuit arrangement for the digital detection of analog information in the form of the time interval between two successive states of at least one signal or the amplitude of the signal, the circuit complexity and susceptibility to interference is low.
  • This object is achieved in that the charging circuit and the charge change circuit change the voltage of the integration capacitor in the same direction and are connected to a common charge source.
  • the circuit arrangement according to the invention can be implemented with little circuit complexity and is almost insensitive to faults. In particular, only one charge source, for example a DC voltage source, is required to operate the circuit. Another advantage is that the circuit arrangement can be constructed from comparatively inexpensive components without reducing its reliability.
  • the charging circuit is only activated during the time interval to be detected in order to charge the integration capacitor to a voltage representing the time interval to be measured . It is also ensured that the voltage change of the integration capacitor takes place immediately after the time interval to be detected by means of the charge change circuit, as a result of which the voltage at the integration capacitor representing the time interval can be evaluated in a fail-safe and comparatively fast manner without being falsified by leakage currents.
  • different signal states of a signal can be selected as delimiting marks of a time interval to be measured.
  • the signal states can be, for example, rising or falling edges of a measurement signal.
  • time intervals between signal states of signals from different sources can be recorded.
  • the circuit complexity for the power supply is kept to a minimum.
  • the development of the invention according to claim 6, for measuring the amplitude of the signal ensures a constant integration time interval for charging the integration capacitor to a voltage representing the amplitude of the analog signal. By counting periodic clock pulses that fall in the charge change phase that follows the integration time interval, digital information about the analog signal voltage to be detected is obtained.
  • a sample-and-hold circuit for temporarily storing signal amplitude values enables the digital detection of amplitude values of time-varying signals.
  • the charging circuit can be easily implemented by setting a first resistance value and the charge change circuit by setting a second resistance value of the resistance circuit according to claim 8, the charge and charge change circuit making do with a common charge source.
  • Claim 9 specifies a very simple possibility for changing the resistance value of the resistance circuit.
  • a particular advantage of the resistance circuit according to claim 9 is that the charge flow to the capacitor during the charging phase and during the Charge change phase essentially depends on passive components that are not susceptible to interference, namely ohmic resistors.
  • the proposed resistance circuit ensures, with a very simple structure, an almost interference-free acquisition of the analog information.
  • resistors with high precision, temperature independence and long-term stability of their resistance values can be produced with the technologies available today without difficulty and at the same time at low cost, which contributes to the inexpensive implementation of the circuit arrangement.
  • the rate of change of the voltage of the integration capacitor during the voltage change by means of the charge change circuit is significantly smaller than the rate of change of the voltage change on the integration capacitor during the charging phase by means of the charge circuit. This is particularly important if time intervals that are approximately the same length or shorter than the period of the periodic clock signal are to be recorded digitally.
  • the duration of the charge change phase which is dependent on the duration of the charge phase, can always be chosen by choosing the resistance ratio of the first and second resistors so long that several periodic clock pulses occur during the charge change phase, so that counting these clock pulses provides digital information about the duration of the charge phase becomes.
  • the integration capacitor can be short-circuited by a second switch of the control device in order to establish the initial conditions for a new measurement process.
  • the circuit arrangement designated 1 in FIG. 1 comprises an analog circuit part 3, a comparator 5, a counter 7 and a control device 9.
  • the analog circuit part 3 comprises a resistance circuit 11 with a first resistor connected to the positive pole 6 of a positive DC voltage source 13 in series with a first switch 15 in a first branch 16 and with a second resistor 17 in parallel with the first resistor 13 and the first Switch 15 in a second branch 18, furthermore in series with the resistance circuit 11, a parallel circuit 21 connected to the reference potential 19 (ground) of the DC voltage source, consisting of an integration capacitor 23 in a third branch 25 and a second switch 27 in a fourth branch 29.
  • the first switch 15 and the second switch 27 are controlled by the control device 9 and, depending on the switching state, switch a current through the first branch 16 or through the fourth branch 29 on or off.
  • An input 31 of the comparator 5 is electrically connected to a first connection 33 of the integration capacitor 23.
  • the comparator 5 compares the voltage U c at the integration capacitor 23 with a predetermined threshold value U c2 and changes the state of its comparator output signal when the capacitor voltage U c reaches the threshold value U c2 .
  • An output 35 of the comparator 5 carrying the comparator output signal is electrically connected to an input 37 of the control device 9.
  • a signal state detector 8 of the control device 9 detects predetermined successive state changes of at least one measurement signal, for example the positive and negative edge of a rectangular pulse of a measurement signal, and the control device 9 controls the first switch 15 or second switch 27 depending on the occurrence of the predetermined state changes of at least one measurement signal or depending on the occurrence of a change in state of the comparator output signal.
  • the control device 9 is also electrically connected to a counter enable input 39 of the counter 7 in order to switch the counter readiness of the counter 7 on or off as a function of the occurrence of a predetermined change in state of at least one measurement signal or the comparator output signal. When switched on The counter counts 7 clock pulses of a periodic clock signal Tref of constant clock period Tclk.
  • the chronological sequence of different steps in the digital detection of the time interval T 1 between the positive and the subsequent negative edge of a rectangular signal pulse P is described below.
  • the second switch 27 is switched on and thus the integration capacitor 23 is short-circuited and discharged via the fourth branch 29 (initial state of the circuit).
  • the signal state detector 8 of the control device 9 detects the positive edge A 1 as the start signal of a measurement, and the control device 9 simultaneously switches off the second switch 27 by outputting a control signal, so that no current flows through the fourth branch 29 can flow past the integration capacitor 23.
  • a charging phase for charging the integration capacitor 23 to a time interval T 1 between the pulse edges A 1, A 2 of the rectangular pulse P represents voltage U c1 .
  • the first switch 15 is switched on, so that the integration capacitor 23 is charged via the first and second resistors 13, 17.
  • the analog circuit 3 works as a charging circuit 3 'with a charging time constant ⁇ 1.
  • the signal state detector 8 of the control device 9 detects the negative edge A2 as a stop signal for the charging phase, and the control device 9 ends the charging phase by switching off the first switch 15 End of the loading phase a signal to the counter 7 to turn on the readiness of the counter 7, so that this counts clock pulses of the periodic clock signal Tref.
  • a charge change phase ⁇ T Immediately following the charging phase is a charge change phase ⁇ T, in which the integration capacitor 23 is only charged via the second resistor 17.
  • the analog circuit 3 works as a charge change circuit 3scnies for relieving the voltage U c on the integration capacitor 23 until the threshold value U c2 monitored by the comparator 5 is reached.
  • the charge time constant ⁇ 2 of the charge change circuit is significantly greater than the charge time constant ⁇ 1 of the charge circuit, so that the voltage U c at the integration capacitor 23 is changed during the charge change phase ⁇ T with a much smaller rate of change than during the charge phase T 1.
  • the time constant ⁇ 2 of the charge change circuit is greater than the time constant ⁇ 1 of the charge circuit, since the total resistance of the resistance circuit 11 during the charge change phase (charge of the integration capacitor 23 via the second resistor 17) is greater than during the charge phase (charge of the integration capacitor 23 via a parallel circuit from the first and second resistor 13, 17).
  • Charge and charge change circuit 3 ', 3 ⁇ change the voltage U c on the integration capacitor 23 in the same direction.
  • the comparator 5 changes the state of the comparator output signal, whereupon the control device 9 switches off the readiness of the counter 7 and switches on the second switch 27.
  • the integration capacitor 23 is then short-circuited and discharged via the second switch 27, as a result of which the circuit arrangement according to the invention is reset to its initial state.
  • the counting result X of the counter 7 is read out after the end of the charge change phase by an evaluation device (not shown) and evaluated as digital information for calculating a measured value for the time interval T 1 between the edges A 1, A 2 of the measurement signal.
  • the signal state detector 8 of the control device 9 can optionally also react to predetermined signal states other than those described above.
  • the signal states for starting and stopping the charging phase of the integration capacitor and thus the measuring time interval can come from different signal sources.
  • the circuit arrangement according to the invention is able to carry out self-calibration measurements.
  • the first switch 15 is switched off and the second switch 27 is switched on (initial switching state), so that the integration capacitor 23 is discharged.
  • the control device 9 starts the calibration measurement by switching off the second switch 27 and switching on the readiness of the counter 7.
  • the integration capacitor 23 is then charged only via the second resistor 17 from its discharge state until the threshold value U c2 is reached .
  • the comparator 5 changes the state of its output signal, whereupon the control device 9 ends the calibration measurement by switching off the readiness of the counter 7 and switching on the second switch 27.
  • the counter 7 counts the clock pulses of the periodic clock signal Tref.
  • the counting result XT of the counter 7 is read out by the evaluation device after the calibration measurement and is buffered. This counting result XT of the calibration measurement is included by the evaluation device in the evaluation of one or more time intervals T 1 to be measured.
  • the following is a mathematical basis for determining a time interval T 1 between successive states of at least one signal.
  • C denotes the charge time constant of the charge change circuit and U c2 denotes the threshold value of the integration capacitor voltage monitored by the comparator 5.
  • Equating equations (1) and (4) and resolving the result according to T1 leads to a mathematical description of the duration of the charging phase or the time interval to be recorded between two successive states of at least one signal, which is independent of the unknown voltage U c1 :
  • T1 - R1 R2C / (R1 + R2) ln ((U O - U c2 ) / U O ) - R1 / (R1 + R2) X Tclk
  • equation (5) the time constants ⁇ 1 and ⁇ 2 are expressed by the resistance values R1 and R2 and by the capacitance C of the integration capacitor 23.
  • the symbol ⁇ T for the duration of the charge change phase has been replaced in equation (5) by the equivalent expression: X Tclk.
  • X denotes the counting result of the counter 7 after the charge change phase has ended and Tclk the period of the periodic clock signal Tref.
  • Equation (5) can be considerably simplified by including the counting result XT of a calibration measurement.
  • the time delay T 1 of two successive states of at least one signal is neither the value of the supply voltage U o nor the threshold value U c2 of the comparator 5, nor the capacitance value C of the integration capacitor 23.
  • Long-term stability of the above-mentioned variables is therefore not necessary if a time interval measurement or a series of measurements of time interval measurements is carried out with the circuit arrangement according to the invention in each case in connection with a calibration measurement. All that is then required is an easy-to-meet short-term stability of the above-mentioned parameters for one measurement process. Expensive precision components with high long-term stability or complex stabilization circuits can therefore be dispensed with.
  • the capacitance value C of the integration capacitor 23 is not included in the equation (8), larger deviations from the nominal capacitance value, for example due to manufacturing tolerances, also play no role.
  • the only device parameters included in the evaluation are the resistance values R1 and R2 and the period Tclk of the clock signal. These values are very easy to determine and have good constancy.
  • the calibration measurement is very simple to carry out and, instead of requiring additional computational effort, the computational evaluation for determining a measuring time interval is considerably simplified.
  • the control device can be constructed from known electronic components such as flip-flops, digital gates, etc.
  • the DC voltage source is preferably a DC supply voltage source for all components of the switching device, in particular a 5 V DC voltage source.
  • a DC supply voltage source for all components of the switching device, in particular a 5 V DC voltage source.
  • MOS field-effect transistors with short switching times are preferably used as the first and second switches 15, 27.
  • the comparator 5 should have an input resistance value which is substantially greater than the resistance values R1, R2 of the first and second resistors 13, 17 in order to keep the load on the analog circuit 3 by the comparator negligibly small.
  • the comparator threshold U c2 is set to a value of approximately 2/3 of the supply voltage U o of the DC voltage source. It is thereby achieved that the integration capacitor voltage U c does not rise during the measurement up to the flat-ended asymptotic range of the exponential charging function.
  • the resistance R2 should be at least a factor of the order of magnitude 100 greater than the resistance value R1 of the first resistor 13, so that the time constant ⁇ 2 of the charge change circuit 3 ⁇ is also large compared to the time constant ⁇ 1 of the charging circuit 3 '.
  • a time interval measuring device 2 with a circuit arrangement according to the invention for digital detection of a time interval is described below.
  • time intervals Tx between positive edges A+ of a measurement signal TCP with several successive pulses P are to be determined (FIG. 4).
  • Time intervals T x are longer than the period Tclk of a reference clock signal Tref, so that several clock pulses of the reference clock signal fall in time in a time interval T x .
  • T m denotes a time interval, which is composed of an integer multiple of the period Tclk of the reference clock signal Tref, T1 the error time interval at the beginning of the measuring time interval T x and T'1 the error time interval at the beginning of the measuring time interval beginning with the next positive edge of the measuring signal TCP.
  • the clock-synchronous time interval T m is determined by counting the reference clock periods falling in the time interval T m with a counter 41, whereas the error time intervals T 1, T 1 are detected with the circuit arrangement 1 a.
  • the time interval measuring device 2 comprises a counting device 41 and a counter enable circuit 43.
  • the circuit arrangement 1a is constructed essentially like the circuit arrangement 1 of the previously described exemplary embodiment. Components already described are identified by the letter a after the reference number. Deviations from the previous embodiment are explained below.
  • the counting device 41 comprises a pulse pause counter 45 for counting clock pulses of the reference clock signal Tref during a pulse pause between the pulses P of the measurement signal TCP and a pulse length counter 47 for Counting clock pulses of the reference clock signal during the duration of a pulse P.
  • a counting device 41 with pulse pause and pulse length counters 45, 47 is advantageous if both pulse durations and pulse pauses are longer than the period duration Tclk of the reference clock signal.
  • the advantage lies in the fact that the pulse length counter 47 or the pulse pause counter 45 can be read out alternately by an evaluation device (not shown), while the other counter 45, 47 counts clock pulses. No very high speed requirements with regard to the reading of the counting results of the counters 45, 47 then need be made to the evaluation device in order to register all counting events or clock pulses of the reference clock signal Tref falling within a time interval T m .
  • the measurement signal is present at an input 49 of the control device 9a and at an input 50 of the counter enable circuit 43.
  • the counter enable circuit 43 controls the readiness to count the counters 45, 47 depending on the occurrence of pulse edges of the measurement signal TCP.
  • the periodic reference clock signal Tref is present at the counting inputs of the pulse length counter 47, the pulse pause counter 45 and the counter 7a of the switching device 1a. Furthermore, the reference clock signal Tref is fed to an input 55 of the control device 9a. A takeover signal of the pulse length counter 47 is fed to a control input 57 of the control device 9a.
  • the first switch 15a of the circuit arrangement 1a is switched on by the control device 9a and the second switch 27a is switched off.
  • the charging phase thus begins, during which the integration capacitor 23a via the first resistor 13a and via the second resistor 17a is loaded.
  • the counter enable circuit 43 blocks the readiness for counting of the pulse pause counter 45 and switches on the readiness for counting of the pulse length counter 47.
  • the charging phase of the integration capacitor 23a ends with the occurrence of a first negative edge of the reference clock signal Tref counted by the pulse length counter 47 and corresponds to an error time interval T 1 or T 1 to be determined.
  • the control device 9a turns off the first switch 15a at the end of the charging phase T1, so that the integration capacitor 23a is further charged during the charge change phase ⁇ T via the second resistor 17a to a voltage threshold U c2 monitored by the comparator 5a.
  • the control device 9a monitors the transfer signal from the pulse length counter 47 in order to determine whether the pulse length counter 47 has actually counted the first negative edge of the periodic clock signal Tref after the start of the measuring time interval T 1, and only ends the charging phase T 1 with the occurrence of a negative edge of the reference clock signal. when the edge has been registered by counter 47.
  • the counter 7a counts clock pulses or negative edges of the periodic reference clock signal Tref.
  • control unit 9a The interaction of the control unit 9a with the counter 7a and the comparator 5a for ending the charge change phase and for controlling the readiness to count (release) of the counter 7a has already been explained in connection with the previously described exemplary embodiment of the invention.
  • the circuit arrangement 1a After the charge change phase has elapsed, the circuit arrangement 1a is in its initial state and is so ready for the detection of a next error time interval T1 or T'1.
  • the readiness for counting (release) of the pulse length counter 47 is switched off when a negative edge A ⁇ of the measurement signal TCP occurs and that of the pulse pause counter 45 is switched on.
  • the counting results of the counters 7a, 45 and 47 are each read out by the evaluation device and temporarily stored after the corresponding counter has come to a standstill.
  • the evaluation device calculates a digital value for the measurement time interval Tx to be determined from the temporarily stored count results.
  • the counter enable circuit (43) monitors both the measurement signal TCP and the reference signal Tref and only switches the readiness for counting of the pulse length counter 47 or the pulse pause counter 45 on or off when the first positive edge of the reference signal Tref follows the positive or negative edge A+ of the measurement signal TCP (Fig. 4a).
  • the triggering a first count event of the pulse length counter negative edge of the reference clock signal Tref which simultaneously ends the charging phase T1 of the integration capacitor 23a, then occurs at the earliest after half a clock period of the reference clock signal Tref after the start of the measuring time interval T x .
  • the time interval T 1 or T 1 to be detected with the circuit arrangement 1 a can then be a minimum of half and a maximum of three half period periods Tclk of the reference signal Tref.
  • the problem that a first edge of the reference clock signal Tref to be counted by the pulse length counter 47 follows the positive edge A+ of the measurement signal TCP too closely to be registered by the counter 47 is eliminated in this way.
  • a typical time behavior of the circuit arrangement 1a is discussed below on the basis of example values for the resistors R1, R2, for the capacitance C of the integration capacitor 23a, for the period Tclk of the reference clock signal Tref and for the comparator threshold U c2 .
  • ⁇ T max 98 ⁇ s
  • the counter 7a X max 487 count events.
  • T 1 300 ns
  • the charge change phase then lasts for ⁇ T min - 73 ⁇ s. This corresponds to a counter reading of 364 counter events of the counter 7a, with a reference clock period of 200 ns.
  • T x denotes the measurement time interval to be determined between successive positive edges of the measurement signal
  • V the count result of the pulse length counter after the pulse duration has expired
  • W the counting result of the pause counter after a pulse pause
  • X the counting result of the counter 7a after the error time interval T 1 has elapsed
  • X 'the counting result of the counter 7a after the error time interval T'1 and Tclk the period of the periodic clock signal Tref.
  • Equation (10) is a simple calculation rule for determining the measured value T x from the counting results of the pulse length counter 47, the pulse pause counter 45 and the counter 7a of the circuit arrangement 1a.
  • the time interval measurement of successive time intervals with the circuit device 1a according to the invention is even superfluous a calibration measurement.
  • the right side of the equation (10) includes the summand Tclk. (V + W), which is measured as an integer multiple of the reference clock period Tclk, and the summand R1 / (R1 + R2) .Tclk (X'-X), which Detection of the error time intervals T1 or T'1 describes.
  • the error time intervals T1, T'1 appear to be divided into significantly smaller time quanta than Tclk, as illustrated in the following example:
  • the error time intervals are scanned with a time pattern of 200 ns / 101, i.e. the virtual clock period in this example is about 2 ns with a real clock period of 200 ns.
  • the reference clock signal Tref can originate, for example, from a system clock source which also clocks a microprocessor unit of the evaluation device.
  • a time interval measuring device with a switching device requires only a single supply DC voltage source and also only a single reference clock source.
  • the form of the measurement signal required to explain the working principle of the time interval measuring device 2 is not mandatory. In this exemplary embodiment of the invention, too, predetermined signal states other than those described can be selected as delimitation marks of time intervals.
  • This further exemplary embodiment is a circuit arrangement for digitally detecting the amplitude of a signal and comprises an analog circuit part 3b, a comparator 5b, a counter 7b, a control device 9b, furthermore a time control circuit 57 and a sample and hold circuit 59.
  • the essential principle of the analog circuit part 3b , the comparator 5b, the counter 7b and the control device 9b essentially emerge from the description of the preceding exemplary embodiments; Deviations from this are described below.
  • the components already described in the previous exemplary embodiments, which also have the same or similar function in the circuit arrangement 1b for digital detection the amplitude of a signal are used are marked with a b after the corresponding reference number.
  • the analog circuit part 3b is connected to a sample and hold circuit 59 which represents the charge source for the integration capacitor 23b.
  • the sample and hold circuit 59 samples the unknown signal U m , for example a voltage signal, and outputs a voltage U x which is proportional to a respectively current sample or hold value to the analog circuit 3b.
  • the timing control circuit 57 is clocked with the reference clock signal Tref and outputs a timing control signal with signal edges successive at a predetermined time interval Tk to the control device 9b.
  • the control device 9b switches the first switch 15b on and the second switch 27b off and thus starts the charging phase of the integration capacitor 23b.
  • the integration capacitor 23b is charged during the charging phase via the first and second resistors 13b, 17b to a voltage U c1 which represents the sample hold value of the sample hold circuit applied to the analog circuit.
  • the control device switches off the first switch 15b and the readiness to count the counter 7b for counting periodic reference clock pulses, which means that the charge change phase for changing the voltage on the integration capacitor 23b until reaching one predetermined threshold value U c2 monitored by the comparator 5b begins.
  • the comparator 5b changes when the Voltage U c2 at the integration capacitor 23b has its output signal, whereupon the control device 9b switches on the second switch 27b and switches off the readiness of the counter 7b to count.
  • the control device 9b notifies the sample-and-hold circuit 59 of the readiness for a new measurement cycle via a ready signal, so that the sample-and-hold circuit 59 outputs a new sample value U x for a next measurement cycle.
  • an evaluation device (not shown) reads out the counting result of the counter 7b in order to thereby calculate a digital measured value for the signal voltage U x or U m to be detected.
  • control device can be provided with delay compensation circuits that take into account different signal delays and switching times or preparation times for components.
  • control device in particular include control circuits which ensure that a new measuring cycle can only begin when the previous measuring cycle has been completed.
  • the dimensions of the first and second resistors, the integration capacitor, and the period Tclk of the reference clock signal essentially depend on the desired digital resolution of an analog information to be acquired and on the tolerated maximum duration of a measurement cycle.
  • the analog circuit 3, 3a, 3b for realizing the charging circuit and the charge change circuit can be replaced by equivalent circuits, for example by a parallel circuit fed by a constant current source, consisting of an integration capacitor, a first and a second resistor with a first switch in series with the first resistor and a second switch in series with the second resistor.

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  • Measurement Of Unknown Time Intervals (AREA)

Abstract

Circuit permettant l'enregistrement numérique d'une information analogique, notamment de l'intervalle entre deux états consécutifs d'au moins un signal ou de l'amplitude dudit signal. Ledit circuit comporte un condensateur d'intégration (23), qui est chargé pendant une phase de charge à une tension Uc1, représentant l'information analogique, par l'intermédiaire d'un circuit parallèle comprenant une première résistance (13) et une deuxième résistance (17). A la fin de cette phase de charge, un premier commutateur (15), lequel est commandé par un dispositif de commande (9) et relié en série à la première résistance (13), interrompt le passage du courant à travers la première résistance (13), de sorte que pendant la phase de modification de charge qui s'ensuit, le condensateur d'intégration (23) n'est chargé que par l'intermédiaire de la deuxième résistance (17) jusqu'à ce que la tension Uc du condensateur atteigne une valeur seuil prédéterminée Uc2 contrôlée par un comparateur (5). La deuxième résistance (17) présente une valeur R2 supérieure à la première résistance (13), de sorte que la constante de temps de charge (τ2) pendant la phase de modification de charge est supérieure à la constante de temps de charge τ1 pendant la phase de charge. Pendant la phase de modification de charge, laquelle est généralement plus longue que la phase de charge, un compteur (7) compte les impulsions périodiques de synchronisation d'un signal de synchronisation de référence. A la fin de la phase de modification de charge, le résultat indiqué par le compteur (7) est lu et traité ultérieurement par un dispositif d'évaluation en vue de l'obtention d'une valeur numérique pour l'information analogique.

Claims (13)

1. Circuit pour l'enregistrement numérique d'une information analogique sous la forme de l'intervalle de temps séparant deux états successifs d'au moins un signal ou de l'amplitude du signal,
comportant un condensateur d'intégration (23;,23a; 23b) qui peut être chargé, par l'intérmédiaire d'un circuit de charge (3′; 3a′; 3b′), sur une tension représentant l'information analogique, avec un circuit de variation de charge (3˝; 3a˝; 3b˝)
qui fait varier la tension du condensateur d'intégration (23; 23a; 23b) avec un taux de variation inférieur à celui du circuit de charge (3′; 3a′; 3b′),
comportant un comparateur (5; 5a; 5b) comparant la tension du condensateur d'intégration (23; 23a; 23b) à une valeur de seuil prédéterminée et comportant un compteur (7; 7a; 7b) qui, pendant la variation de la tension du condensateur d'intégration (23; 23a; 23b), compte des impulsions périodiques de rythme jusqu'à ce que la valeur de seuil prédéterminée soit atteinte,
caractérisé en ce que le circuit de charge (3′; 3a′; 3b′) et le circuit de variation de charge (3˝; 3a˝; 3b˝) font varier dans le même sens la tension du condensateur d'intégration (23; 23a; 23b) et sont connectés à une source de charge commune.
2. Circuit selon la revendication 1, caractérisé en ce que pour l'enregistrement numérique de l'intervalle de temps séparant deux états successifs d'au moins un signal, un détecteur d'état de signal (8, 8a) d'un dispositif de commande (9, 9a), en particulier un détecteur de fronts, détecte les états successifs et en ce que le dispositif de commande rend opérant le circuit de charge (3′, 3a′) à l'apparition du premier état dans le temps et rend opérant le circuit de variation de charge (3˝, 3a˝), à l'apparition du deuxième état.
3. Circuit selon la revendication 2, caractérisé en ce que le premier état de signal dans le temps et le deuxième correspondent chacun, au choix, au dépassement ou à des valeurs inférieures à des niveaux d'amplitude prédéterminés d'un signal.
4. Circuit selon la revendication 2 ou 3, caractérisé en ce que le premier état de signal dans le temps correspond, au choix, au dépassement ou à des valeurs inférieures à des niveaux d'amplitude prédéterminés d'un premier signal et en ce que le deuxième état correspond, au choix, au dépassement ou à des valeurs inférieures à des niveaux d'amplitude prédéterminés d'un deuxième signal.
5. Circuit selon la revendication 2, 3 ou 4, caractérisé en ce que la source de charge est une source de tension continue, en particulier une source de tension continue d'alimentation du circuit.
6. Circuit selon la revendication 1, caractérisé en ce que pour mesurer l'amplitude d'un signal un circuit de commande de temps (57), produisant un intervalle de temps d'intégration de longueur prédéterminée, coopère avec un dispositif de commande (9b) qui, au début de l'intervalle de temps d'intégration, rend opérant le circuit de charge (3b˝) et, à la fin de l'intervalle de temps d'intégration, rend opérant le circuit de variation de charge (3b˝) et en ce que la source de charge est la source du signal analogique ou un circuit qui délivre une tension proportionnelle à l'amplitude du signal analogique.
7. Circuit selon la revendication 6, caractérisé en ce que la source de charge est un circuit de détection et de maintien (59) détectant le signal et stockant de manière intermédiaire et analogique des valeurs détectées de l'amplitude du signal, lequel circuit produit, pendant l'intervalle de temps d'intégration, une tension de sortie proportionnelle à une valeur détectée de l'amplitude du signal.
8. Circuit selon l'une des revendications précédentes, caractérisé en ce que le condensateur d'intégration (23; 23a; 23b) est connecté à la source de charge, par un circuit résistant (11: 11a; 11b) avec valeur de résistance globale commandable, monté en série avec le condensateur d'intégration (23; 23a; 23b).
9. Circuit selon la revendication 8, caractérisé en ce que le circuit résistant (11; 11a; 11b) comporte un circuit parallèle constitué d'une première résistance (13; 13a; 13b) et d'une deuxième résistance (17; 17a; 17b) et en ce que le courant, passant à travers la première résistance (13; 13a; 13b), peut être alimenté et coupé par un premier interrupteur (15; 15a; 15b) du dispositif de commande (9; 9a; 9b).
10. Circuit selon la revendication 9, caractérisé en ce que la valeur (R₂) de la deuxième résistance (17; 17a) dépasse la valeur (R₁) de la première résistance (13; 13a), d'un multiple de la valeur de la première résistance.
11. Circuit selon l'une des revendications précédentes, caractérisé en ce que, pour décharger le condensateur d'intégration (23; 23a; 23b), les branchements du condensateur d'intégration (23; 23a; 23b) peuvent être court-circuités par un deuxième interrupteur (27; 27a; 27b) du dispositif de commande (9; 9a; 9b).
12. Circuit selon l'une des revendications 1, 2, 3, 4, 5, 8, 9 et 11, caractérisé en ce que le circuit (1a) fait partie d'un dispositif de mesure d'intervalle de temps (2) pour l'enregistrement numérique d'intervalles de temps (Tx) dont la durée dépasse, d'un multiple, celle des impulsions périodiques de rythme, en ce qu'un dispositif de comptage (41) compte les impulsions périodiques de rythme pendant un intervalle de temps (Tm) d'une durée correspondant à un multiple entier de la durée de la période de rythme (Tclk) et en ce que le circuit (1a) enregistre les intervalles de temps (T₁, T′₁) entre le début d'un intervalle de temps de mesure (Tx) et le début de l'intervalle de temps (Tm) de rythme synchrone ainsi qu'entre la fin de l'intervalle de temps de mesure (Tx) et la fin de l'intervalle de temps (Tm) de rythme synchrone et en ce qu'un dispositif d'exploitation traite les résultats de comptage du dispositif de comptage (41) et du compteur (7a) afin de calculer une valeur de mesure numérique pour l'intervalle de temps (Tx).
13. Circuit selon la revendication 12, caractérisé en ce que le dispositif de comptage (41) comprend un compteur de longueur d'impulsions (47) et un compteur de pause d'impulsions (45), le compteur de longueur d'impulsions (47) et le compteur de pause d'impulsions (45) se déclenchant l'un l'autre lors du comptage des impulsions périodiques de rythme, tombant pendant la période de temps (Tm) de rythme synchrone.
EP89911553A 1988-10-13 1989-10-12 Circuit permettant l'enregistrement numerique d'une information analogique formee par l'intervalle entre deux etats successifs d'un signal Expired - Lifetime EP0438469B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT89911553T ATE77496T1 (de) 1988-10-13 1989-10-12 Schaltungsanordnung zur digitalen erfassung einer analogen information in der form des zeitabstandes zweiter aufeinanderfolgender zustaende eines signals.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3834938 1988-10-13
DE3834938A DE3834938C1 (fr) 1988-10-13 1988-10-13

Publications (2)

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EP0438469A1 EP0438469A1 (fr) 1991-07-31
EP0438469B1 true EP0438469B1 (fr) 1992-06-17

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EP89911553A Expired - Lifetime EP0438469B1 (fr) 1988-10-13 1989-10-12 Circuit permettant l'enregistrement numerique d'une information analogique formee par l'intervalle entre deux etats successifs d'un signal

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EP (1) EP0438469B1 (fr)
DE (2) DE3834938C1 (fr)
WO (1) WO1990004219A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT401985B (de) * 1991-09-19 1997-01-27 Vaillant Gmbh Analog-digital-umsetzer
DE19703633C2 (de) * 1997-01-31 2002-12-12 Sick Ag Verfahren zur Bestimmung eines Zeitintervalls zwischen zwei Ereignissen
US8618965B2 (en) 2011-12-28 2013-12-31 St-Ericsson Sa Calibration of a charge-to-digital timer
US9379729B2 (en) * 2011-12-28 2016-06-28 St-Ericsson Sa Resistive/residue charge-to-digital timer
US8659360B2 (en) 2011-12-28 2014-02-25 St-Ericsson Sa Charge-to-digital timer
WO2013098359A2 (fr) * 2011-12-28 2013-07-04 St-Ericsson Sa Compteur de temps charge-numérique

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2134112B1 (fr) * 1971-04-20 1974-03-22 Sodern
US3735261A (en) * 1971-06-07 1973-05-22 Northrop Corp Pulse analyzer
US4301360A (en) * 1979-10-25 1981-11-17 Tektronix, Inc. Time interval meter
US4613950A (en) * 1983-09-22 1986-09-23 Tektronix, Inc. Self-calibrating time interval meter
US4772843A (en) * 1986-06-06 1988-09-20 Yokogawa Electric Corporation Time measuring apparatus

Also Published As

Publication number Publication date
WO1990004219A1 (fr) 1990-04-19
EP0438469A1 (fr) 1991-07-31
DE3834938C1 (fr) 1989-12-07
DE58901716D1 (de) 1992-07-23

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