EP0378453B1 - Stable reference voltage generator - Google Patents

Stable reference voltage generator Download PDF

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Publication number
EP0378453B1
EP0378453B1 EP90400024A EP90400024A EP0378453B1 EP 0378453 B1 EP0378453 B1 EP 0378453B1 EP 90400024 A EP90400024 A EP 90400024A EP 90400024 A EP90400024 A EP 90400024A EP 0378453 B1 EP0378453 B1 EP 0378453B1
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Prior art keywords
transistor
transistors
collector
current mirror
voltage
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German (de)
French (fr)
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EP0378453A1 (en
Inventor
Patrick Bernard
Christophe Magnier
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STMicroelectronics SA
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SGS Thomson Microelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/901—Starting circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/907—Temperature compensation of semiconductor

Definitions

  • the present invention relates to a voltage generator capable of being able to generate a reference voltage V REF which is independent, on the one hand, of the variation of the ambient temperature and, on the other hand, of variation of the supply voltage of this generator.
  • FIG. 1 A block diagram of a stable voltage generator independent, theoretically at least, of the temperature. Such a diagram is illustrated in FIG. 1.
  • the transistors Q1, Q2 are of geometry such that the first transistor Q1 is equivalent to "N" transistors identical to the second transistor Q2 arranged in parallel.
  • the output of the assembly 10, giving the reference voltage V REF is arranged at the connection point between the resistor R2 and the drain of the transistor M1.
  • the structure of the transistor Q1 has been chosen so that the latter is equivalent to N transistors Q2 put in parallel and that we know that the differences between the base-emitter voltages of two bipolar transistors, of different geometry, but crossed by the same current is proportional to the ambient temperature as expressed by the following relation: where "k” and “q” are the universal constants well known to those skilled in the art and V SE1 and V BE2 are the base-emitter voltages of the transistors Q1 and Q2.
  • the base-emitter voltage has, in the first order, a linear decrease with temperature. It follows that the base-emitter voltage (V SE2 ) of transistor Q2 is given by the following relationship: where a and V co2 are constants related to the structure of transistor Q2. This equation neglects the higher order terms in T as well as very small variations in V CO2 as a function of the current flowing through the transistor.
  • the drain voltage of M2 roughly follows the variation of V DD while the drain voltage of M1 will remain relatively stable.
  • the transistors M1 and M2 operating in saturation mode it is known that the drain-source current which passes through them is likely to vary as a function of the drain-source voltage with a relatively small but not zero slope.
  • the drain-source voltages of the transistors M1 and M2 become different it follows that the latter will be crossed by currents of substantially different amplitude: the basic assumption that the bipolar transistors Q1 and Q2 are crossed by an identical current is consequently falsified as soon as the supply voltage V DD varies.
  • transistor Q2 has a relatively stable collector voltage (equal to the base-emitter voltage of transistor Q1) while the voltage at the collector of transistor Q1 more or less follows the variations of the supply voltage V DD as a result of the transparency of the transistor M2 in this regard.
  • the Early effect modulation of the width of the base of a bipolar transistor as a function of the collector-base voltage
  • V BEZ - V BEL the voltage at the collector of transistor Q1 more or less follows the variations of the supply voltage V DD as a result of the transparency of the transistor M2 in this regard.
  • the subject of the present invention is a voltage generator operating generally on the same principle as that illustrated in FIG. 1 but in which, on the one hand, the voltage variations at the output of the current mirror circuit do not affect, or little affect , the voltage at the collector of the first transistor Q1 and, on the other hand, in which the equality of the currents passing through the first and second transistors (Q1 and Q2) is respected as much as possible.
  • the generator which, in general, has a structure generally in accordance with that mentioned above, is it characterized in that it further comprises an isolation transistor arranged in series between the primary branch of the current mirror circuit and the first transistor, the collector of the latter being connected to the emitter of the isolation transistor, and means for supplying voltage to the base of the isolation transistor , this voltage being predetermined to allow the conduction of said isolation transistor.
  • a mirror comprising at least two stages of transistors mounted in cascode is chosen as the current mirror.
  • the voltage generator includes a voltage mirror whose performance is clearly superior to that of the voltage mirror constituted by the MOS-P transistors M1 and M2 described in support of FIG. 1. It follows that when the supply voltage V DD varies the current flowing in the secondary branch remains the image of that flowing in the primary branch. Thanks to this characteristic, the sum of the first order factors in T in equation (4) above is effectively zero because the starting hypothesis (equality of the currents flowing in the first transistor Q1 and second transistor Q2) is respected.
  • the present invention provides for supplementing the assembly succinctly mentioned above by start-up means allowing the transition from the stable state where all the transistors are blocked to that where the transistors are conductive.
  • these means include one or more start-up capacitors intended to cause the current mirror circuit to turn on and therefore that of the other transistors.
  • start-up means comprising in particular a field effect transistor so-called “start-up” intended to cause the transistors of the current mirror circuit to be turned on and an inverter assembly intended to drive the start-up field effect transistor to, in particular, block it when the generator has switched over its stable state where all the bipolar transistors are conductive.
  • a transistor arrangement such as the assembly Q3-Q6 functions as a precise current mirror circuit, the current flowing in the secondary branch, constituted by the transistors Q3, Q5 being the image of that flowing in the branch primary constituted by the transistors Q4, Q6.
  • the current mirror circuit constituted by the transistors Q3-Q6 is not subject to significant differences between the amplitudes of the currents flowing in its primary branch and in its secondary branch. in the event of variation of the voltage V DD .
  • an isolation transistor according to the invention such as the transistor Q7 also makes it possible, in connection here with the Wilson current mirror used in the diagram of FIG. 2, to guarantee compliance with the theoretical conditions of operation (equality of currents) by making it possible to isolate the collector of the first transistor Q1 from voltage variations at the collector of the transistor Q6.
  • the potential at the transistor Q6 also varies. However, such a variation cannot be transmitted as such to the collector of the first transistor Q1 because the transistor Q7 acts as an isolation means.
  • the potential V TH applied to the base of transistor Q7 is relatively stable and sufficient to allow conduction of Q7 (on the support of FIG. 3, a means will be described making it possible to obtain such a potential V TH ); it is therefore the same for the potential at the emitter of transistor Q7: we know that in a bipolar transistor the potential of the emitter is 0.6 V lower than that of the base as soon as it enters conduction.
  • FIG. 3 there is illustrated an embodiment of the voltage source V TH to be connected to the base of the isolation transistor Q7.
  • the voltage source V TH can be of the order of 1 V to 1.5 V to guarantee operation of the circuit with supply voltages of 3 V.
  • Such a voltage is obtained by arranging two bipolar NPN transistors Q8 and Q9 in series. These transistors are arranged to be in the saturated state (base connected to the collector). Under these conditions, the potential at the base of transistor Q8 is equal to twice the base-emitter voltage existing in a bipolar transistor in the saturated state, ie 1.2 V.
  • a MOS-P transistor M4 is mounted "en resistance "and arranged between the collector of Q8 and the supply V DD , its grid being connected to ground.
  • the voltage V TH on the basis of Q7 is therefore 1.2 V and varies little. It is known in fact that if the collector current of the transistors Q8 and Q9 is caused to vary as a result of a large variation of the voltage V DD, the base-emitter voltage of the transistors Q8 and Q9 will however vary little: it follows that the voltage V TH is relatively stable, in any case sufficient to avoid an amplitude of harmful variation at the level of the collector of transistor Q1.
  • the FET transistor M4 can be replaced by a resistor.
  • the voltage V TH can be obtained by means of an assembly such as that illustrated in FIG. 1.
  • this problem is solved by interposing the starting capacity C1 between the collector of transistor Q7 and the ground.
  • This capacity acts as a means of passing the rest of the assembly from the stable state blocked to the stable state where all the transistors are conductive.
  • the transistor Q6 is blocked and seeks to remain blocked because the entire assembly is in the blocked stable state.
  • the transistor Q6 can be maintained in a stable state blocked its base must be maintained at a potential close to V DD , which will require to charge the starting capacity C1, since the latter is also connected to the base of the transistor Q6.
  • To provide the necessary charge Q6 must unlock. It is then the same for transistor Q4.
  • the current mirror circuit then comes into operation, which results in the unlocking of the transistors Q3, Q5 then that of the transistors Q1 and Q2.
  • the entire assembly then switches to the stable state where all the transistors are conductive.
  • a capacity C1 of sufficiently high value In practice, it is necessary to choose a capacity C1 of sufficiently high value. In the preferred embodiment of the present invention, a capacitance C1 with a value of 3pF is used.
  • a capacitor C2 is connected to the collector of the bipolar transistor Q3 of the secondary branch of the current mirror. This capacity is connected to ground via a MOS-N transistor referenced in M3. The gate of this transistor is itself connected to the collector of the second bipolar transistor Q5 of the secondary branch of the current mirror circuit.
  • the capacitance C2 is connected to earth. Even in the presence of sudden variations in the supply voltage V DD, the capacitors C1 and C2 will be loaded symmetrically, which makes it possible to guarantee the equality of the currents at the level of the bipolar transistors Q1 and Q2.
  • the role of the field effect transistor M3 is as follows.
  • the capacitor C2 has a disadvantage in the absence of such a transistor and if it is connected directly to ground: it prevents the correct start of the assembly from the power up because it absorbs the whole of the current passing through the transistor Q3, thereby preventing the conduction of the transistor Q2. Under these conditions, the entire assembly ends up in the stable state where all the transistors are blocked.
  • the inventor found that it was necessary to annihilate the capacitor C2 as long as the second bipolar transistor Q2 is not in a conduction state: this is the role of the MOS-N transistor M3.
  • the capacitor C2 is in these conditions not connected to ground.
  • the transistors Q2 and M3 become conductive and the capacitor C2 is connected to ground, thus allowing the assembly to absorb any subsequent variations in the supply voltage V DD and preventing these variations from affecting the output voltage V REF .
  • the role of the resistor R3 is to slightly raise the gate potential of the transistor M to ensure the conduction of the latter after starting.
  • the assembly illustrated in FIG. 3 makes it possible to obtain a gain of the order of 20 dB, at the level of the output of the assembly (V REF ) as regards the filtering of the variations of the supply voltage V DD , for frequencies from 100 kHz to a few MHz.
  • the capacitor C1 is replaced there by a MOS-P transistor M4, the gate of this transistor being connected to the output S of an inverter constituted by a MOS-P transistor M6 and a MOS-N transistor M7.
  • the source of transistor M6 is connected to the power supply V DD while that of transistor M7 is connected to ground.
  • the input at E of the inverter (constituted by the gates connected to each other and the transistors M6-M7), is itself connected to the collector of the transistor Q5.
  • the output S of the inverter is at the potential of the source of the MOS-P M6 transistor which is then conductive (V DD in the species). It follows that the gate of the transistor M4 is then at the potential V DD and the transistor M4 which is an N-channel MOS becomes conductive when the generator is put into service. Under these conditions the transistor M4 imposes a current in the primary branch of the current mirror circuit which makes it possible to start all the other bipolar transistors.
  • the present invention is in no way limited to the embodiments chosen and shown, but on the contrary quite encompasses any variant within the reach of ordinary skill in the art.
  • it is in no way limited to the use of the Wilson assembly as a current mirror circuit.

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Abstract

The stable reference voltage generator consists of a current mirror circuit connected between a voltage supply (VDD) and an earth connection, this circuit comprising a primary branch and a secondary branch, a first bipolar transistor (Q1) connected in series through its collector with the primary branch of the current mirror, a potential divider bridge consisting of at least two resistors (R1, R2) arranged in series, this bridge being itself connected in series between the secondary branch of the current mirror and the collector of a second bipolar transistor (Q2), the base of the second transistor (Q2) being connected to the point linking the said resistors, while the base of the first transistor (Q1) is connected to the collector of the second transistor (Q2), the output from the generator (VREF) being arranged at the terminal of the bridge opposite to that connected to the collector of the second transistor Q2, the said transistors having a geometry such that the first transistor (Q1) is equivalent to "N" transistors identical to the second transistor (Q2) connected in parallel, and an insulating bipolar transistor (Q7) connected in series between the primary branch of the current mirror circuit and the first transistor, the collector of the latter transistor being connected to the emitter of the insulating transistor. <IMAGE>

Description

La présente invention concerne un générateur de tension susceptible de pouvoir générer une tension de référence VREF qui soit indépendant, d'une part, de la variation de la température ambiante et, d'autre part, de variation de la tension d'alimentation de ce générateur.The present invention relates to a voltage generator capable of being able to generate a reference voltage V REF which is independent, on the one hand, of the variation of the ambient temperature and, on the other hand, of variation of the supply voltage of this generator.

On connaît dans l'état de la technique le schéma de principe d'un générateur de tension stable indépendant, théoriquement tout au moins, de la température. Un tel schéma est illustré en figure 1.We know in the prior art the block diagram of a stable voltage generator independent, theoretically at least, of the temperature. Such a diagram is illustrated in FIG. 1.

Le générateur 10 qui y est représenté comporte, agencés entre une alimentation en tension VDD et une mise à la masse :

  • - un circuit miroir de courant comportant, de façon classique une branche primaire 11 et une branche secondaire 12. Dans le schéma illustré le miroir de courant est réalisé au moyen de deux transistors MOS-P référencés en M1 et M2, le circuit source-drain du transistor M2 constituant ici la branche primaire 11, tandis que le circuit source-drain du transistor M1 constitue la branche secondaire 12. Les transistors M1 et M2 sont reliés par leurs grilles, ces dernières étant en outre reliées au drain du transistor M2.
  • - un premier transistor bipolaire Q1 raccordé en série par son collecteur avec la branche primaire 11 du miroir de courant. Dans le schéma illustré le transistor Q1 est un transistor NPN, son émetteur étant relié à la masse.
  • - un pont diviseur de tension comportant ici deux résistances R1 et R2 agencées en série, ce pont étant lui-même agencé en série entre la branche secondaire 12 du miroir de courant et le collecteur d'un second transistor bipolaire Q2. Ce second transistor, qui est ici aussi un transistor de type NPN, est relié à la masse par son émetteur, tandis que sa base est reliée au point de liaison entre les résistances R1, R2.
The generator 10 which is shown there comprises, arranged between a voltage supply V DD and an earthing:
  • a current mirror circuit comprising, in a conventional manner a primary branch 11 and a secondary branch 12. In the diagram illustrated, the current mirror is produced by means of two MOS-P transistors referenced in M1 and M2, the source-drain circuit of the transistor M2 here constituting the primary branch 11, while the source-drain circuit of the transistor M1 constitutes the secondary branch 12. The transistors M1 and M2 are connected by their gates, the latter being further connected to the drain of the transistor M2.
  • - A first bipolar transistor Q1 connected in series by its collector with the primary branch 11 of the current mirror. In the diagram illustrated the transistor Q1 is an NPN transistor, its emitter being connected to ground.
  • - A voltage divider bridge here comprising two resistors R1 and R2 arranged in series, this bridge itself being arranged in series between the secondary branch 12 of the current mirror and the collector of a second bipolar transistor Q2. This second transistor, which here is also an NPN type transistor, is connected to ground by its emitter, while its base is connected to the connection point between the resistors R1, R2.

Les transistors Q1, Q2 sont de géométrie telle que le premier transistor Q1 équivaut à "N" transistors identiques au second transistor Q2 agencés en parallèle. La sortie du montage 10, donnant la tension de référence VREF, est disposée au point de liaison entre la résistance R2 et le drain du transistor M1.The transistors Q1, Q2 are of geometry such that the first transistor Q1 is equivalent to "N" transistors identical to the second transistor Q2 arranged in parallel. The output of the assembly 10, giving the reference voltage V REF , is arranged at the connection point between the resistor R2 and the drain of the transistor M1.

Un tel montage permet de générer une tension de référence VREF qui s'avère stable par rapport aux variations de la température ambiante pour autant que les valeurs de R1, R2 et de N soient choisies de manière judicieuse. En effet, on sait que si l'on s'arrange pour que le transistor M1 soit saturé, le circuit constitué par les transistors M 1 et M2 est un miroir de courant, le courant circulant dans la branche secondaire 12 ayant des caractéristiques très semblables à celles du courant circulant dans la branche primaire 11. Dès lors, en négligeant les courants de base des transistors Q1 et Q2, un courant de caractéristiques semblables traverse d'une part l'ensemble constitué par le pont de résistance R1, R2 et le transistor Q2 et, d'autre part le transistor Q1. On sait par ailleurs qu'il existe une relation expotentielle entre courant et tension base-émetteur dans un transistor bipolaire. Comme par ailleurs la structure du transistor Q1 a été choisie de telle sorte que ce dernier équivaut à N transistors Q2 mis en parallèle et que l'on sait que les différences entre les tensions base-émetteur de deux transistors bipolaires, de géométrie différente, mais traversés par un même courant est proportionnelle à la température ambiante comme l'exprime la relation suivante :

Figure imgb0001
où "k" et "q" sont les constantes universelles bien connues de l'homme de l'art et VSE1 et VBE2 sont les tensions base-émetteur des transistors Q1 et Q2.Such an arrangement makes it possible to generate a reference voltage V REF which proves to be stable with respect to variations in the ambient temperature provided that the values of R1, R2 and N are chosen judiciously. Indeed, we know that if we arrange for the transistor M1 to be saturated, the circuit formed by the transistors M 1 and M2 is a current mirror, the current flowing in the secondary branch 12 having very similar characteristics. to those of the current flowing in the primary branch 11. Consequently, by neglecting the basic currents of the transistors Q1 and Q2, a current of similar characteristics crosses on the one hand the assembly constituted by the resistance bridge R1, R2 and the transistor Q2 and, on the other hand, transistor Q1. We also know that there is an expotential relationship between current and base-emitter voltage in a bipolar transistor. As also the structure of the transistor Q1 has been chosen so that the latter is equivalent to N transistors Q2 put in parallel and that we know that the differences between the base-emitter voltages of two bipolar transistors, of different geometry, but crossed by the same current is proportional to the ambient temperature as expressed by the following relation:
Figure imgb0001
 where "k" and "q" are the universal constants well known to those skilled in the art and V SE1 and V BE2 are the base-emitter voltages of the transistors Q1 and Q2.

En négligeant les courants de base on considère que les résistances R1 et R2 sont traversées par un même courant. Il s'ensuit :

Figure imgb0002
By neglecting the basic currents we consider that the resistors R1 and R2 are crossed by the same current. It follows:
Figure imgb0002

Par ailleurs on sait que la tension base-émetteur a, au premier ordre, une décroissance linéaire avec la température. Il s'ensuit que la tension base-émetteur (VSE2) du transistor Q2 est donnée par la relation suivante:

Figure imgb0003
où a et Vco2 sont des constantes liées à la structure du transistor Q2. Cette équation néglige les termes d'ordre supérieur en T ainsi que de très faibles variations de VCO2 en fonction du courant qui traverse le transistor.Furthermore, we know that the base-emitter voltage has, in the first order, a linear decrease with temperature. It follows that the base-emitter voltage (V SE2 ) of transistor Q2 is given by the following relationship:
Figure imgb0003
 where a and V co2 are constants related to the structure of transistor Q2. This equation neglects the higher order terms in T as well as very small variations in V CO2 as a function of the current flowing through the transistor.

Des trois équations ci-dessus on tire la relation suivante :

Figure imgb0004
From the three equations above we derive the following relation:
Figure imgb0004

Il s'ensuit qu'en choisissant judicieusement R1, R2 et N on peut, dans l'équation (4) ci-dessus, annuler la somme des termes au premier ordre en T.It follows that by judiciously choosing R1, R2 and N we can, in equation (4) above, cancel the sum of the first order terms in T.

Il reste alors que la tension en sortie du montage VREF est dépendante seulement de la composante constante Vco de la tension base-émetteur du transistor Q2.It then remains that the voltage at the output of the assembly V REF is dependent only on the constant component V co of the base-emitter voltage of the transistor Q2.

Ce schéma donne globalement satisfaction en ce qu'il permet de s'affranchir des variations de la température ambiante. En effet, les variations au second ordre (en T2) et aux ordres suivants étant négligeables dans la plupart des applications, il vient d'être démontré ci-dessus que le montage de la figure 1 permet de s'affranchir des variations au premier ordre de la température. Ce montage présente cependant une grande sensibilité aux variations de la tension d'alimentation VDD.This scheme is generally satisfactory in that it makes it possible to overcome variations in the ambient temperature. Indeed, the second order variations (in T 2 ) and the following orders being negligible in most applications, it has just been shown above that the assembly of FIG. 1 makes it possible to overcome variations at the first temperature order. However, this arrangement is very sensitive to variations in the supply voltage V DD .

En effet lorsque la tension d'alimentation VDD augmente la tension au drain de M2 suit à peu près la variation de VDD tandis que la tension au drain de M1 va rester relativement stable. Les transistors M1 et M2 fonctionnant en régime de saturation, on sait que le courant drain-source qui les traverse est susceptible de varier en fonction de la tension drain-source avec une pente relativement faible mais non nulle. Les tensions drain-source des transistors M1 et M2 devenant différentes il s'ensuit que ces derniers vont être traversés par des courants d'amplitude sensiblement différente : l'hypothèse de base selon laquelle les transistors bipolaires Q1 et Q2 sont traversés par un courant identique se trouve en conséquence faussée dès que la tension d'alimentation VDD varie.In fact when the supply voltage V DD increases the drain voltage of M2 roughly follows the variation of V DD while the drain voltage of M1 will remain relatively stable. The transistors M1 and M2 operating in saturation mode, it is known that the drain-source current which passes through them is likely to vary as a function of the drain-source voltage with a relatively small but not zero slope. As the drain-source voltages of the transistors M1 and M2 become different it follows that the latter will be crossed by currents of substantially different amplitude: the basic assumption that the bipolar transistors Q1 and Q2 are crossed by an identical current is consequently falsified as soon as the supply voltage V DD varies.

De même, s'agissant des transistors bipolaires, on observe que le transistor Q2 a une tension collecteur relativement stable (égale à la tension base-émetteur du transistor Q1) tandis que la tension au collecteur du transistor Q1 suit plus ou moins les variations de la tension d'alimentation VDD par suite de la transparence du transistor M2 à cet égard. Dans ces conditions l'effet Early (modulation de la largeur de la base d'un transistor bipolaire en fonction de la tension collecteur-base) va avoir pour conséquence d'engendrer des déviations de la différence des tensions base-émetteur des transistors Q1, Q2 (VBEZ - VBEL) par rapport à sa valeur théorique ci-avant rappelée.Similarly, with regard to bipolar transistors, it is observed that transistor Q2 has a relatively stable collector voltage (equal to the base-emitter voltage of transistor Q1) while the voltage at the collector of transistor Q1 more or less follows the variations of the supply voltage V DD as a result of the transparency of the transistor M2 in this regard. Under these conditions the Early effect (modulation of the width of the base of a bipolar transistor as a function of the collector-base voltage) will have the consequence of causing deviations in the difference of the base-emitter voltages of the transistors Q1, Q2 (V BEZ - V BEL ) compared to its theoretical value mentioned above.

La présente invention a pour objet un générateur de tension fonctionnant globalement selon le même principe que celui illustré en figure 1 mais dans lequel, d'une part, les variations de tension en sortie du circuit miroir de courant n'affectent pas, ou affectent peu, la tension au collecteur du premier transistor Q1 et, d'autre part, dans lequel l'égalité des courants traversant les premier et second transistors (Q1 et Q2) soit autant que possible respectée.The subject of the present invention is a voltage generator operating generally on the same principle as that illustrated in FIG. 1 but in which, on the one hand, the voltage variations at the output of the current mirror circuit do not affect, or little affect , the voltage at the collector of the first transistor Q1 and, on the other hand, in which the equality of the currents passing through the first and second transistors (Q1 and Q2) is respected as much as possible.

Ainsi, selon un aspect de la présente invention, le générateur, qui, d'une manière générale, présente une structure globalement conforme à celle ci-avant rappelée, est-il caractérisé en ce qu'il comporte en outre un transistor d'isolation agencé en série entre la branche primaire du circuit miroir de courant et le premier transistor, le collecteur de ce dernier étant relié à l'émetteur du transistor d'isolation, et des moyens d'alimentation en tension de la base du transistor d'isolation, cette tension étant prédéterminée pour permettre la conduction dudit transistor d'isolation.Thus, according to one aspect of the present invention, the generator, which, in general, has a structure generally in accordance with that mentioned above, is it characterized in that it further comprises an isolation transistor arranged in series between the primary branch of the current mirror circuit and the first transistor, the collector of the latter being connected to the emitter of the isolation transistor, and means for supplying voltage to the base of the isolation transistor , this voltage being predetermined to allow the conduction of said isolation transistor.

Grâce à ces dispositions on évite que les variations éventuelles de tension en sortie de la branche primaire du circuit miroir de courant soient transmises au collecteur du premier transistor. En effet la tension d'alimentation de la base du transistor d'isolation étant prédéterminée et ce transistor étant raccordé par son émetteur au collecteur du premier transistor, il s'ensuit que le potentiel du collecteur du premier transistor est stable.Thanks to these arrangements, it is avoided that any variations in voltage at the output of the primary branch of the current mirror circuit are transmitted to the collector of the first transistor. In fact, the supply voltage of the base of the isolation transistor being predetermined and this transistor being connected by its emitter to the collector of the first transistor, it follows that the potential of the collector of the first transistor is stable.

Selon une autre caractéristique de l'invention, on choisit comme miroir de courant un miroir comportant au moins deux étages de transistors montés en cascode.According to another characteristic of the invention, a mirror comprising at least two stages of transistors mounted in cascode is chosen as the current mirror.

Grâce à cette disposition le générateur de tension comporte un miroir de tension dont les performances sont nettement supérieures à celles du miroir de tension constitué par les transistors MOS-P M1 et M2 décrits à l'appui de la figure 1. Il s'ensuit que lorsque la tension d'alimentation VDD varie le courant circulant dans la branche secondaire reste l'image de celui circulant dans la branche primaire. Grâce à cette caractéristique la somme des facteurs du premier ordre en T dans l'équation (4) ci-avant est effectivement nulle car l'hypothèse de départ (égalité des courants circulant dans le premier transistor Q1 et second transistor Q2) est respectée.Thanks to this arrangement, the voltage generator includes a voltage mirror whose performance is clearly superior to that of the voltage mirror constituted by the MOS-P transistors M1 and M2 described in support of FIG. 1. It follows that when the supply voltage V DD varies the current flowing in the secondary branch remains the image of that flowing in the primary branch. Thanks to this characteristic, the sum of the first order factors in T in equation (4) above is effectively zero because the starting hypothesis (equality of the currents flowing in the first transistor Q1 and second transistor Q2) is respected.

Le Demandeur s'est également trouvé confronté au problème du démarrage du générateur tel que succinctement rappelé ci-dessus, lors de ses mises sous tension. En effet, un tel générateur présente un second état stable où tous les transistors sont bloqués.The Applicant was also faced with the problem of starting the generator as succinctly recalled above, when it was powered up. Indeed, such a generator has a second stable state where all the transistors are blocked.

La présente invention prévoit de compléter le montage succinctement rappelé ci-dessus par des moyens de mise en route permettant le passage de l'état stable où tous les transistors sont bloqués à celui où les transistors sont conducteurs.The present invention provides for supplementing the assembly succinctly mentioned above by start-up means allowing the transition from the stable state where all the transistors are blocked to that where the transistors are conductive.

Selon un aspect de la présente invention ces moyens comportent une ou plusieurs capacités de mise en route destinées à provoquer la mise en conduction du circuit miroir de courant et par conséquent celle des autres transistors.According to one aspect of the present invention, these means include one or more start-up capacitors intended to cause the current mirror circuit to turn on and therefore that of the other transistors.

Selon un autre aspect de l'invention, pour éviter d'avoir à employer des capacités de mise en route, qui dans certaines applications peuvent présenter des inconvénients, la présente invention prévoit des moyens de mise en route comportant notamment un transistor à effet de champ dit de "mise en route" destiné à provoquer la mise en conduction des transistors du circuit miroir de courant et un montage inverseur destiné à piloter le transistor à effet de champ de mise en route pour, notamment, le bloquer lorsque le générateur a basculé dans son état stable où tous les transistors bipolaires sont conducteurs.According to another aspect of the invention, in order to avoid having to use start-up capacitors, which in certain applications can have drawbacks, the present invention provides start-up means comprising in particular a field effect transistor so-called "start-up" intended to cause the transistors of the current mirror circuit to be turned on and an inverter assembly intended to drive the start-up field effect transistor to, in particular, block it when the generator has switched over its stable state where all the bipolar transistors are conductive.

Les caractéristiques et avantages de la présente invention ressortiront d'ailleurs de la description qui va suivre en référence aux dessins annexés sur lesquels :

  • - la figure 1 a déjà été décrite,
  • - la figure 2 est un schéma simplifié illustrant un mode de réalisation de la présente invention,
  • - la figure 3 est un schéma plus complexe illustrant l'agencement de certains moyens non montrés en figure 2 et,
  • - la figure 4 est une variante de réalisation du circuit illustré en figure 3.
The characteristics and advantages of the present invention will become apparent from the description which follows with reference to the appended drawings in which:
  • FIG. 1 has already been described,
  • FIG. 2 is a simplified diagram illustrating an embodiment of the present invention,
  • FIG. 3 is a more complex diagram illustrating the arrangement of certain means not shown in FIG. 2 and,
  • FIG. 4 is an alternative embodiment of the circuit illustrated in FIG. 3.

Sur les dessins les éléments communs à plusieurs figures conservent les mêmes références.In the drawings, the elements common to several figures keep the same references.

En figure 2 on reconnaît un schéma semblable à celui décrit en figure 1. Par rapport à ce dernier les différences sont les suivantes :

  • - le miroir de courant constitué en figure 1 par les transistors MOS-P M1, M2 est remplacé conformément à un aspect de l'invention par un miroir de courant cascode ici de type Wilson à transistors bipolaires référencés, sur cette figure, en Q3-Q6. Ce miroir est du type Wilson car dans la branche primaire, constituée ici par les transistors Q4-Q6, la base du transistor de sortie (Q6) est reliée au collecteur de ce transistor, tandis que, dans la branche secondaire, constituée ici par les transistors Q3, Q5, c'est la base du transistor raccordé à l'alimentation VDD qui est relié au collecteur de ce transistor; par ailleurs la base du transistor Q3 est reliée à celle du transistor Q4 tandis que la base du transistor Q5 est reliée à celle du transistor Q6.
  • - conformément à un autre aspect de l'invention un transistor d'isolation Q7 est agencé en série entre la branche primaire 11 du circuit miroir de courant et le premier transistor Q1, le collecteur du transistor Q1 étant relié à l'émetteur du transistor d'isolation Q7. On observe que le collecteur du transistor d'isolation Q7 est relié au point de sortie de la branche primaire du circuit miroir de courant, en l'espèce le collecteur du transistor Q6. Des moyens d'alimentation en tension de la base du transistor d'isolation sont prévus, cette tension étant prédéterminée pour permettre la conduction du transistor d'isolation Q7. Par le mode de réalisation choisi et représenté ces moyens d'alimentation sont constitués par une source de tension VTH dont on décrira un mode de réalisation à l'appui de la figure 3.
  • - conformément à un autre aspect de l'invention une capacité C1, dite de mise en route est raccordée entre le collecteur du transistor Q7 et la masse.
In Figure 2 we recognize a diagram similar to that described in Figure 1. Compared to the latter the differences are as follows:
  • the current mirror formed in FIG. 1 by the MOS-P transistors M1, M2 is replaced in accordance with one aspect of the invention by a cascode current mirror here of Wilson type with bipolar transistors referenced in this figure in Q3- Q6. This mirror is of the Wilson type because in the primary branch, constituted here by the transistors Q4-Q6, the base of the output transistor (Q6) is connected to the collector of this transistor, while, in the secondary branch, constituted here by the transistors Q3, Q5, this is the base of the transistor connected to the power supply V DD which is connected to the collector of this transistor; moreover, the base of transistor Q3 is connected to that of transistor Q4 while the base of transistor Q5 is connected to that of transistor Q6.
  • - In accordance with another aspect of the invention, an isolation transistor Q7 is arranged in series between the primary branch 11 of the current mirror circuit and the first transistor Q1, the collector of transistor Q1 being connected to the emitter of transistor d insulation Q7. It is observed that the collector of the isolation transistor Q7 is connected to the output point of the primary branch of the current mirror circuit, in this case the collector of the transistor Q6. Means for supplying voltage to the base of the isolation transistor are provided, this voltage being predetermined to allow the conduction of the isolation transistor Q7. By the embodiment chosen and shown, these supply means consist of a voltage source V TH , an embodiment of which will be described in support of FIG. 3.
  • - In accordance with another aspect of the invention, a capacitor C1, called start-up capacitor, is connected between the collector of transistor Q7 and the ground.

Le fonctionnement du schéma illustré en figure 2 est le suivant :The operation of the diagram illustrated in FIG. 2 is as follows:

Il est connu qu'un agencement transistors tel que l'ensemble Q3-Q6 fonctionne comme un circuit miroir de courant précis, le courant circulant dans la branche secondaire, constitué par les transistors Q3, Q5 étant l'image de celui circulant dans la branche primaire constitué par les transistors Q4, Q6. Cependant, au contraire du circuit miroir de courant illustré en figure 1, le circuit miroir de courant constitué par les transistors Q3-Q6 n'est pas sujet à des différences significatives entre les amplitudes des courants circulant dans sa branche primaire et dans sa branche secondaire en cas de variation de la tension VDD.It is known that a transistor arrangement such as the assembly Q3-Q6 functions as a precise current mirror circuit, the current flowing in the secondary branch, constituted by the transistors Q3, Q5 being the image of that flowing in the branch primary constituted by the transistors Q4, Q6. However, unlike the current mirror circuit illustrated in FIG. 1, the current mirror circuit constituted by the transistors Q3-Q6 is not subject to significant differences between the amplitudes of the currents flowing in its primary branch and in its secondary branch. in the event of variation of the voltage V DD .

Il s'ensuit que, comme le transistor Q7 est agencé de telle sorte qu'il est conducteur, le courant circulant dans le premier transistor Q1 est identique à celui circulant dans le transistor Q2, les courants de base sont négligés. Cette caractéristique contribue donc à permettre au générateur de tension stable de référence de fonctionner conformément à la théorie ci-avant rappelée.It follows that, as the transistor Q7 is arranged so that it is conductive, the current flowing in the first transistor Q1 is identical to that flowing in the transistor Q2, the base currents are neglected. This characteristic therefore contributes to enabling the reference stable voltage generator to operate in accordance with the above-mentioned theory.

De plus la présence d'un transistor d'isolation conforme à l'invention tel que le transistor Q7 permet également, en liaison ici avec le miroir de courant Wilson utilisé dans le schéma de la figure 2, de garantir le respect des conditions théoriques de fonctionnement (égalité des courants) en permettant d'isoler le collecteur du premier transistor Q1 des variations de tension au niveau du collecteur du transistor Q6.In addition, the presence of an isolation transistor according to the invention such as the transistor Q7 also makes it possible, in connection here with the Wilson current mirror used in the diagram of FIG. 2, to guarantee compliance with the theoretical conditions of operation (equality of currents) by making it possible to isolate the collector of the first transistor Q1 from voltage variations at the collector of the transistor Q6.

En effet si la tension d'alimentation VDD varie, le potentiel au niveau du transistor Q6 varie lui aussi. Cependant une telle variation ne peut pas être transmise telle quelle au collecteur du premier transistor Q1 car le transistor Q7 fait office de moyen d'isolation. Le potentiel VTH appliqué à la base du transistor Q7 est relativement stable et suffisant pour permettre la conduction de Q7 (à l'appui de la figure 3 il sera décrit un moyen permettant d'obtenir un tel potentiel VTH) ; il en est donc de même du potentiel au niveau de l'émetteur du transistor Q7: on sait que dans un transistor bipolaire le potentiel de l'émetteur est inférieur de 0,6 V à celui de la base dès lors qu'il entre en conduction.If the supply voltage V DD varies, the potential at the transistor Q6 also varies. However, such a variation cannot be transmitted as such to the collector of the first transistor Q1 because the transistor Q7 acts as an isolation means. The potential V TH applied to the base of transistor Q7 is relatively stable and sufficient to allow conduction of Q7 (on the support of FIG. 3, a means will be described making it possible to obtain such a potential V TH ); it is therefore the same for the potential at the emitter of transistor Q7: we know that in a bipolar transistor the potential of the emitter is 0.6 V lower than that of the base as soon as it enters conduction.

De la sorte il est possible de garantir que le potentiel au niveau du collecteur Q1 sera le potentiel VTH diminué de 0,6 V : on s'est ainsi affranchi des variations de tension au niveau du collecteur du transistor Q6 en sortie de la branche primaire du circuit miroir de courant, ces variations étant absorbées par le transistor d'isolation Q7.In this way it is possible to guarantee that the potential at the level of the collector Q1 will be the potential V TH reduced by 0.6 V: we have thus been freed from voltage variations at the level of the collector of the transistor Q6 at the output of the branch primary of the current mirror circuit, these variations being absorbed by the isolation transistor Q7.

En figure 3 il est illustré un mode de réalisation de la source de tension VTH devant être reliée à la base du transistor d'isolation Q7.In Figure 3 there is illustrated an embodiment of the voltage source V TH to be connected to the base of the isolation transistor Q7.

La source de tension VTH peut être de l'ordre de 1 V à 1,5 V pour garantir un fonctionnement du circuit avec des tensions d'alimentations de 3V.The voltage source V TH can be of the order of 1 V to 1.5 V to guarantee operation of the circuit with supply voltages of 3 V.

Une telle tension est obtenue en agençant deux transistors bipolaires NPN Q8 et Q9 en série. Ces transistors sont agencés pour être à l'état saturé (base reliée au collecteur). Dans ces conditions le potentiel au niveau de la base du transistor Q8 est égal au double de la tension base-émetteur existant dans un transistor bipolaire à l'état saturé, soit 1,2 V. Un transistor MOS-P M4 est monté "en résistance" et agencé entre le collecteur de Q8 et l'alimentation VDD, sa grille étant reliée à la masse.Such a voltage is obtained by arranging two bipolar NPN transistors Q8 and Q9 in series. These transistors are arranged to be in the saturated state (base connected to the collector). Under these conditions, the potential at the base of transistor Q8 is equal to twice the base-emitter voltage existing in a bipolar transistor in the saturated state, ie 1.2 V. A MOS-P transistor M4 is mounted "en resistance "and arranged between the collector of Q8 and the supply V DD , its grid being connected to ground.

La tension VTH sur la base de Q7 est donc de 1,2 V et varie peu. On sait en effet que si le courant de collecteur des transistors Q8 et Q9 est amené à varier par suite d'une importante variation de la tension VDD la tension base-émetteur des transistors Q8 et Q9 variera en revanche peu : il s'ensuit que la tension VTH est relativement stable, en tous cas suffisante pour éviter une amplitude de variation néfaste au niveau du collecteur du transistor Q1.The voltage V TH on the basis of Q7 is therefore 1.2 V and varies little. It is known in fact that if the collector current of the transistors Q8 and Q9 is caused to vary as a result of a large variation of the voltage V DD, the base-emitter voltage of the transistors Q8 and Q9 will however vary little: it follows that the voltage V TH is relatively stable, in any case sufficient to avoid an amplitude of harmful variation at the level of the collector of transistor Q1.

En variante le transistor FET M4 peut être remplacé par une résistance. Dans une autre variante la tension VTH peut être obtenue au moyen d'un montage tel que celui illustré en figure 1.As a variant, the FET transistor M4 can be replaced by a resistor. In another variant, the voltage V TH can be obtained by means of an assembly such as that illustrated in FIG. 1.

Le rôle de la capacité C1 (figure 2) est le suivant. Comme la plupart des générateurs de tension stable de référence mettant en oeuvre des transistors bipolaires, le schéma de la figure 2 présente, en plus de l'état stable où tous les transistors sont en conduction, un second état stable où tous les transistors sont bloqués. Avant la mise en service du générateur de tension tous les transistors sont à l'état bloqué et, comme il s'agit d'un état stable il n'y a aucune raison pour que, lors de la mise en service l'ensemble du montage bascule vers le premier état stable où tous les transistors sont conducteurs. Le Demandeur a cherché un moyen de permettre au montage de passer de l'état stable où tous les transistors sont bloqués à l'état stable où tous les transistors sont conducteurs.The role of capacity C1 (Figure 2) is as follows. Like most reference stable voltage generators using bipolar transistors, the diagram in FIG. 2 presents, in addition to the stable state where all the transistors are in conduction, a second stable state where all the transistors are blocked . Before the voltage generator is put into service, all the transistors are in the blocked state and, since it is a stable state, there is no reason why, during the commissioning of the whole of the mounting switches to the first stable state where all the transistors are conductive. The Applicant has sought a way to allow the assembly to pass from the stable state where all the transistors are blocked to the stable state where all the transistors are conductive.

Selon une caractéristique de la présente invention ce problème est résolu en interposant la capacité de mise en route C1 entre le collecteur du transistor Q7 et la masse.According to a characteristic of the present invention, this problem is solved by interposing the starting capacity C1 between the collector of transistor Q7 and the ground.

Cette capacité agit comme moyen de passage du reste du montage de l'état stable bloqué à l'état stable où tous les transistors sont conducteurs. En effet lors de la mise en route de l'installation, le transistor Q6 est bloqué et cherche à se maintenir bloqué car l'ensemble du montage est dans l'état stable bloqué. Or pour que le transistor Q6 puisse se maintenir dans un état stable bloqué sa base doit se maintenir à un potentiel proche de VDD, ce qui imposera de charger la capacité de mise en route C1, puisque cette dernière est également reliée à la base du transistor Q6. Cependant pour fournir la charge nécessaire Q6 doit se débloquer. Il en est alors de même du transistor Q4. Le circuit miroir de courant entre alors en fonction ce qui entraîne le déblocage des transistors Q3, Q5 puis celui des transistors Q1 et Q2. L'ensemble du montage bascule alors vers l'état stable où tous les transistors sont conducteurs.This capacity acts as a means of passing the rest of the assembly from the stable state blocked to the stable state where all the transistors are conductive. In fact, when the installation is started up, the transistor Q6 is blocked and seeks to remain blocked because the entire assembly is in the blocked stable state. However so that the transistor Q6 can be maintained in a stable state blocked its base must be maintained at a potential close to V DD , which will require to charge the starting capacity C1, since the latter is also connected to the base of the transistor Q6. However to provide the necessary charge Q6 must unlock. It is then the same for transistor Q4. The current mirror circuit then comes into operation, which results in the unlocking of the transistors Q3, Q5 then that of the transistors Q1 and Q2. The entire assembly then switches to the stable state where all the transistors are conductive.

En pratique il faut choisir une capacité C1 de valeur suffisamment élevée. Dans le mode de réalisation préféré de la présente invention il est utilisé une capacité C1 de valeur de 3pF.In practice, it is necessary to choose a capacity C1 of sufficiently high value. In the preferred embodiment of the present invention, a capacitance C1 with a value of 3pF is used.

Ce qui vient d'être expliqué est vrai pour des variations lentes de la tension d'alimentation VDD mais, dans certaines circonstances, notamment en cas de variations brusques et rapides de la tension d'alimentation VDD le schéma illustré en figure 2 ne fonctionne pas de façon satisfaisante.What has just been explained is true for slow variations in the supply voltage V DD but, in certain circumstances, in particular in the event of sudden and rapid variations in the supply voltage V DD, the diagram illustrated in FIG. 2 does not not working satisfactorily.

En effet pour des montées rapides de la tension d'alimentation VDD (par exemple parasites de haute fréquence) la tension base-émetteur des transistors Q3 et Q4 augmente brusquement en valeur absolue entraînant de ce fait une augmentation de courant dans les deux branches du circuit miroir de courant constituée par les transistors Q3-Q6. Cependant même si les variations de courant restent identiques dans les deux branches, comme en aval de la branche primaire sont montés en parallèle, d'une part une branche de circuit comportant, agencés en série, les transistors Q7 et Q1, et d'autre part, la capacité C1 il s'avère qu'une partie du courant circulant dans la branche primaire du circuit miroir de courant est déviée vers C1 ce qui entraîne un déséquilibre des courants circulant respectivement dans les transistors Q1 et Q2. Dans ces conditions l'hypothèse de départ (égalité des courants dans Q1 et Q2) n'est plus respectée ce qui entraîne une variation brusque de la tension de référence en sortie du montage (VREF). De plus la disymétrie des courants traversant Q1 et Q2 dure tant que la capacité C1 n'est pas chargée ce qui fait que le temps nécessaire pour que la tension de référence en sortie du montage (VREF) revienne au niveau souhaité est assez long ce qui, dans certaines applications, est inacceptable.Indeed for rapid increases in the supply voltage V DD (for example high frequency interference) the base-emitter voltage of the transistors Q3 and Q4 increases suddenly in absolute value thereby causing an increase in current in the two branches of the current mirror circuit constituted by the transistors Q3-Q6. However even if the current variations remain identical in the two branches, as downstream of the primary branch are mounted in parallel, on the one hand a circuit branch comprising, arranged in series, the transistors Q7 and Q1, and on the other share, the capacitance C1 it turns out that part of the current flowing in the primary branch of the current mirror circuit is deflected towards C1 which results in an imbalance of the currents flowing respectively in the transistors Q1 and Q2. Under these conditions, the starting hypothesis (equality of the currents in Q1 and Q2) is no longer respected, which leads to an abrupt variation in the reference voltage at the output of the assembly (V REF ). In addition, the asymmetry of the currents passing through Q1 and Q2 lasts as long as the capacitor C1 is not charged, which means that the time necessary for the reference voltage at the output of the assembly (V REF ) to return to the desired level is quite long, which in some applications is unacceptable.

Pour pallier cet inconvénient l'inventeur a eu l'idée d'adjoindre une seconde capacité C2 de valeur équivalente à C1 entre le collecteur Q3 et la masse, de sorte qu'une symétrie des courants est conservée au niveau des transistors Q1 et Q2 même en présence de variations brusques de la tension d'alimentation VDD. Cette caractéristique de l'invention est illustrée en figure 3.To overcome this drawback, the inventor had the idea of adding a second capacitor C2 of value equivalent to C1 between the collector Q3 and the ground, so that a symmetry of the currents is preserved at the level of the transistors Q1 and Q2 itself. in the presence of sudden variations in the supply voltage V DD . This characteristic of the invention is illustrated in FIG. 3.

On y observe en effet qu'une capacité C2 est raccordée au collecteur du transistor bipolaire Q3 de la branche secondaire du miroir de courant. Cette capacité est reliée à la masse par l'intermédiaire d'un transistor MOS-N référencé en M3. La grille de ce transistor est elle-même reliée au collecteur du second transistor bipolaire Q5 de la branche secondaire du circuit miroir de courant.It is observed in fact that a capacitor C2 is connected to the collector of the bipolar transistor Q3 of the secondary branch of the current mirror. This capacity is connected to ground via a MOS-N transistor referenced in M3. The gate of this transistor is itself connected to the collector of the second bipolar transistor Q5 of the secondary branch of the current mirror circuit.

Ainsi, lorsque le transistor M3 est conducteur, pour les raisons qui vont être exposées ci-après, la capacité C2 se trouve reliée à la terre. Même en présence de variations brusques de la tension d'alimentation VDD les capacités C1 et C2 vont être chargées symétriquement ce qui permet de garantir l'égalité des courants au niveau des transistors bipolaires Q1 et Q2.Thus, when the transistor M3 is conductive, for the reasons which will be explained below, the capacitance C2 is connected to earth. Even in the presence of sudden variations in the supply voltage V DD, the capacitors C1 and C2 will be loaded symmetrically, which makes it possible to guarantee the equality of the currents at the level of the bipolar transistors Q1 and Q2.

Le rôle du transistor à effet de champ M3 est le suivant. La capacité C2 présente de son côté un désavantage en l'absence d'un tel transistor et si elle est reliée directement à la masse : elle empêche le démarrage correct de l'ensemble du montage à la mise sous tension car elle absorbe l'ensemble du courant traversant le transistor Q3, empêchant de ce fait la mise en conduction du transistor Q2. Dans ces conditions l'ensemble du montage finit par se retrouver à l'état stable où tous les transistors sont bloqués. L'inventeur a trouvé qu'il fallait annihiler la capacité C2 tant que le second transistor bipolaire Q2 n'est pas en état de conduction : c'est le rôle du transistor MOS-N M3.The role of the field effect transistor M3 is as follows. The capacitor C2 has a disadvantage in the absence of such a transistor and if it is connected directly to ground: it prevents the correct start of the assembly from the power up because it absorbs the whole of the current passing through the transistor Q3, thereby preventing the conduction of the transistor Q2. Under these conditions, the entire assembly ends up in the stable state where all the transistors are blocked. The inventor found that it was necessary to annihilate the capacitor C2 as long as the second bipolar transistor Q2 is not in a conduction state: this is the role of the MOS-N transistor M3.

En effet tant que le transistor bipolaire Q2 ne conduit pas le potentiel de grille du transistor MOS-N M3 reste proche de zéro et ce transistor est donc bloqué : la capacité C2 n'est dans ces conditions pas raccordée à la masse. Après le démarrage, lorsque la tension d'alimentation VDD atteint un certain potentiel les transistors Q2 et M3 deviennent conducteurs et la capacité C2 se trouve reliée à la masse permettant ainsi au montage d'absorber toutes variations subséquentes de la tension d'alimentation VDD et empêchant ces variations d'avoir une incidence sur la tension en sortie VREF.In fact as long as the bipolar transistor Q2 does not conduct the gate potential of the MOS-N transistor M3 remains close to zero and this transistor is therefore blocked: the capacitor C2 is in these conditions not connected to ground. After start-up, when the supply voltage V DD reaches a certain potential, the transistors Q2 and M3 become conductive and the capacitor C2 is connected to ground, thus allowing the assembly to absorb any subsequent variations in the supply voltage V DD and preventing these variations from affecting the output voltage V REF .

Le rôle de la résistance R3 est d'élever un peu le potentiel de grille du transistor M pour assurer la conduction de celui-ci après démarrage.The role of the resistor R3 is to slightly raise the gate potential of the transistor M to ensure the conduction of the latter after starting.

Un autre problème de démarrage peut surgir si la charge raccordée à la sortie VREF est capacitive et du même ordre de grandeur que la capacité C1. En effet la capacité constituée par la charge est directement raccordée à la masse et, lors du démarrage elle absorbe l'ensemble du courant traversant la branche secondaire Q3-Q5 du circuit miroir de courant, empêchant de ce fait la mise en conduction du transistor Q2. Pour pallier cet inconvénient il suffit de choisir C1 et C2 de valeur suffisamment importante en tous cas supérieure à celle de la charge prévue pour se garantir de problèmes de démarrage.Another starting problem can arise if the load connected to the output V REF is capacitive and of the same order of magnitude as the capacity C1. In fact, the capacity constituted by the load is directly connected to ground and, during startup, it absorbs all of the current flowing through the secondary branch Q3-Q5 of the current mirror circuit, thereby preventing the transistor Q2 from turning on. . To overcome this drawback, it suffices to choose C1 and C2 of sufficiently large value, in any case greater than that of the load envisaged, to guarantee start-up problems.

Le montage illustré en figure 3 permet d'obtenir un gain de l'ordre de 20 dB, au niveau de la sortie du montage (VREF) pour ce qui est du filtrage des variations de la tension d'alimentation VDD, pour des fréquences de 100 kHz à quelques MHz.The assembly illustrated in FIG. 3 makes it possible to obtain a gain of the order of 20 dB, at the level of the output of the assembly (V REF ) as regards the filtering of the variations of the supply voltage V DD , for frequencies from 100 kHz to a few MHz.

Pour certaines applications haute fréquence, ou pour d'autres raisons, il peut être utile de prévoir un montage sans capacités de mise en route telles que les capacités C1 et C2 tout en présentant des performances de filtrage des variations d'alimentations semblables à celles du schéma illustré en figure 3. Le montage illustré en figure 4 résout ce problème.For certain high-frequency applications, or for other reasons, it may be useful to provide an assembly without start-up capacities such as the capacities C1 and C2 while exhibiting filtering variations variations in power supply similar to those of the diagram illustrated in figure 3. The assembly illustrated in figure 4 solves this problem.

La capacité C1 y est remplacée par un transistor MOS-P M4, la grille de ce transistor étant raccordée à la sortie S d'un inverseur constitué par un transistor MOS-P M6 et un transistor MOS-N M7. La source du transistor M6 est reliée à l'alimentation VDD tandis que celle du transistor M7 est reliée à la masse. L'entrée en E de l'inverseur (constitué par les grilles reliées entre elles et les transistors M6-M7), est elle-même reliée au collecteur du transistor Q5.The capacitor C1 is replaced there by a MOS-P transistor M4, the gate of this transistor being connected to the output S of an inverter constituted by a MOS-P transistor M6 and a MOS-N transistor M7. The source of transistor M6 is connected to the power supply V DD while that of transistor M7 is connected to ground. The input at E of the inverter (constituted by the gates connected to each other and the transistors M6-M7), is itself connected to the collector of the transistor Q5.

Ce montage fonctionne comme suit.This assembly works as follows.

Classiquement tant que la tension sur l'entrée E de l'inverseur est en-dessous d'un certain seuil la sortie S de l'inverseur est au potentiel de la source du transistor MOS-P M6 qui est alors conducteur (VDD en l'espèce). Il s'ensuit que la grille du transistor M4 est alors au potentiel VDD et le transistor M4 qui est un MOS à canal N devient conducteur à la mise en service du générateur. Dans ces conditions le transistor M4 impose un courant dans la branche primaire du circuit miroir de courant ce qui permet d'amorcer l'ensemble des autres transistors bipolaires.Conventionally as long as the voltage on the input E of the inverter is below a certain threshold, the output S of the inverter is at the potential of the source of the MOS-P M6 transistor which is then conductive (V DD in the species). It follows that the gate of the transistor M4 is then at the potential V DD and the transistor M4 which is an N-channel MOS becomes conductive when the generator is put into service. Under these conditions the transistor M4 imposes a current in the primary branch of the current mirror circuit which makes it possible to start all the other bipolar transistors.

Cependant le potentiel au collecteur du transistor Q5 s'élève et lorsque la tension de seuil de l'inverseur est dépassée le transistor M6 se bloque tandis que le transistor M7 devient conducteur : la sortie S de l'inverseur se trouve alors reliée à la masse de même que la grille du transistor M4 qui se bloque : l'ensemble du courant circulant dans la branche primaire du circuit miroir de courant est alors acheminée dans le transistor Q1. Comme par ailleurs les courants de grille des transistors M6 et M7 sont négligeables l'ensemble du courant circulant dans la branche secondaire du circuit miroir de courant se trouve acheminé vers Q2 : l'égalité des courants dans les transistors Q1 et Q2 est respectée et le montage génère alors une tension de référence stable indépendante de la température et des variations de la tension d'alimentation VDD pour les raisons exposées plus haut.However the potential at the collector of transistor Q5 rises and when the threshold voltage of the inverter is exceeded the transistor M6 is blocked while the transistor M7 becomes conductive: the output S of the inverter is then connected to ground as well as the gate of transistor M4 which is blocked: all of the current flowing in the primary branch of the current mirror circuit is then routed in transistor Q1. As also the gate currents of the transistors M6 and M7 are negligible, all of the current flowing in the secondary branch of the current mirror circuit is routed to Q2: the equality of the currents in the transistors Q1 and Q2 is respected and the mounting then generates a stable reference voltage independent of the temperature and variations in the supply voltage V DD for the reasons explained above.

En remplaçant ainsi les capacités C1 et C2 du schéma de la figure 3 par divers transistors à effet de champ on peut ainsi s'affranchir des inconvénients liés aux signaux haute fréquence éventuellement présents sur le bus d'alimentation VDD.By thus replacing the capacitors C1 and C2 of the diagram in FIG. 3 by various field effect transistors, it is thus possible to overcome the drawbacks linked to the high frequency signals possibly present on the supply bus V DD .

Bien entendu la présente invention ne se limite nullement aux modes de réalisations choisis et représentés mais englobe bien au contraire toute variante à la portée de l'homme de l'art. En particulier elle ne se limite nullement à l'emploi du montage de Wilson comme circuit miroir de courant.Of course, the present invention is in no way limited to the embodiments chosen and shown, but on the contrary quite encompasses any variant within the reach of ordinary skill in the art. In particular, it is in no way limited to the use of the Wilson assembly as a current mirror circuit.

Claims (9)

1. Stable reference voltage generator comprising, disposed between a voltage supply (VDD) and an earth connection, a current mirror circuit comprising a primary branch and a secondary branch which, in operation, carries a current with characteristics at least comparable with, and if possible identical to, those of the current in the primary branch, a first bipolar transistor (Q1) with its collector connected in series with the primary branch of the current mirror, a voltage divider bridge comprising at least two series-connected resistors (R1, R2), said bridge being connected in series between the secondary branch of the current mirror and the collector of a second bipolar transistor (Q2), the base of the second transistor (Q2) being connected to the common point of said resistors, the base of the first transistor (Q1) being connected to the collector of the second transistor (Q2), the output of the generator (VREF) being connected to the terminal of the bridge opposite that connected to the collector of the second transistor (Q2), the geometry of said transistors being such that the first transistor (Q1) is equivalent to "N" transistors identical to the second transistor (Q2) connected in parallel, the reference voltage (VREF) being given by the equation:
Figure imgb0009
Figure imgb0010
R1, R2 and N being chosen so that the sum of the terms aT and Rl q .LogN is null, characterised in that it further comprises an isolation bipolar transistor (Q7) connected in series between the primary branch of the current mirror circuit and the first transistor, the collector of the latter being connected to the emitter of the isolation transistor, and means for feeding to the base of the isolation transistor a voltage predetermined to enable conduction in said isolation transistor.
2. Voltage generator according to claim 1 characterised in that the current mirror circuit comprises at least two cascode transistor stages (Q3, Q4 and Q5, Q6).
3. Generator according to claim 1 characterised in that the transistors are bipolar transistors in a so-called "Wilson" circuit in which the base of the output transistor (Q6) of the primary branch of the circuit is connected to the collector of this transistor (Q6) whereas the base of the transistor (Q3) connected to the supply voltage of the generator (VDD), is connected to the collector of this transistor (Q3), the bases of the transistors of each stage being connected together.
4. Generator according to any one of claims 1 through 3 characterised in that it comprises a starter capacitor (C1) between the collector of the isolation transistor (Q7) and earth.
5. Generator according to claim 4 characterised in t hat it comprises a second starter capacitor (C2) connected between the collector of the bipolar transistor connected to the generator supply voltage (VDD) and earth through isolating means adapted to isolate the second starter capacitor (C2) from earth when the second bipolar transistor (Q2) is not turned on.
6. Generator according to claim 5 characterised in that said means for isolating the second starter capacitor (C2) comprise a field-effect transistor (M3) connected in series between said second starter capacitor (C2) and earth, the gate of said field-effect transistor being connected to the output of the secondary branch (12) of the current mirror.
7. Generator according to any one of claims 1 through 3 characterised in that it comprises starting means comprising in particular a so-called "starter" field-effect transistor (M4) adapted to turn on the transistors of the current mirror circuit and an inverter circuit designed to drive the starter field-effect transistor, in particular to turn it off when the generator has switched to its stable state in which all the bipolar transistors are turned on.
8. Generator according to any one of claims 1 through 3 characterised in that it comprises a so-called "starter" field-effect transistor (M4) between the collector of the isolation transistor (Q7) and earth and an inverter circuit between said voltage supply (VDD) and earth, the output (S) of said inverter circuit being connected to the gate of the starter transistor (M4) and the input (E) of the inverter circuit being connected to the output of the secondary branch (12) of the current mirror circuit.
9. Generator according to claim 7 or claim 8 characterised in that the inverter circuit comprises a PMOS transistor (M6) the source of which is connected to said voltage supply (VDD) and an NMOS transistor (M7) the source of which is connected to earth, the drains of said transistors being connected together and constituting the output (S) of the inverter circuit and the gates of said transistors being connected together and constituting the input (E) of said inverter circuit.
EP90400024A 1989-01-11 1990-01-04 Stable reference voltage generator Expired - Lifetime EP0378453B1 (en)

Priority Applications (1)

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AT90400024T ATE99435T1 (en) 1989-01-11 1990-01-04 STABLE REFERENCE VOLTAGE GENERATOR.

Applications Claiming Priority (2)

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FR8900274A FR2641626B1 (en) 1989-01-11 1989-01-11 STABLE REFERENCE VOLTAGE GENERATOR
FR8900274 1989-01-11

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US5030903A (en) 1991-07-09
KR900012147A (en) 1990-08-03
JP2749681B2 (en) 1998-05-13
FR2641626B1 (en) 1991-06-14
FR2641626A1 (en) 1990-07-13
EP0378453A1 (en) 1990-07-18
USRE34772E (en) 1994-11-01
ATE99435T1 (en) 1994-01-15
DE69005460T2 (en) 1994-05-11
DE69005460D1 (en) 1994-02-10
JPH02226409A (en) 1990-09-10

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