EP0341929A2 - Circuit multiplex - Google Patents

Circuit multiplex Download PDF

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Publication number
EP0341929A2
EP0341929A2 EP89304573A EP89304573A EP0341929A2 EP 0341929 A2 EP0341929 A2 EP 0341929A2 EP 89304573 A EP89304573 A EP 89304573A EP 89304573 A EP89304573 A EP 89304573A EP 0341929 A2 EP0341929 A2 EP 0341929A2
Authority
EP
European Patent Office
Prior art keywords
path
switching means
capacitors
channels
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89304573A
Other languages
German (de)
English (en)
Other versions
EP0341929B1 (fr
EP0341929A3 (fr
Inventor
Walter Scott Bartky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xaar Ltd
Original Assignee
Xaar Ltd
Multigraphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB888811458A external-priority patent/GB8811458D0/en
Priority claimed from GB888830397A external-priority patent/GB8830397D0/en
Application filed by Xaar Ltd, Multigraphics Inc filed Critical Xaar Ltd
Publication of EP0341929A2 publication Critical patent/EP0341929A2/fr
Publication of EP0341929A3 publication Critical patent/EP0341929A3/fr
Application granted granted Critical
Publication of EP0341929B1 publication Critical patent/EP0341929B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/07—Ink jet characterised by jet control
    • B41J2/075—Ink jet characterised by jet control for many-valued deflection
    • B41J2/08—Ink jet characterised by jet control for many-valued deflection charge-control type
    • B41J2/085—Charge means, e.g. electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
    • B41J2202/01—Embodiments of or processes related to ink-jet heads
    • B41J2202/10—Finger type piezoelectric elements

Definitions

  • This invention relates to multiplexer circuits for effecting in successive phases of operation thereof actuation of selected devices of respective groups of devices of a series of capacitance actuated devices.
  • a multiplexer circuit is a pulsed droplet deposition apparatus, such as a drop-on-demand ink jet printer having a multi-channel array from the channels of which the droplets are ejected and in which the channels are arranged in groups, channels from the respective groups being selected for printing droplets in successive phases of operation of the multiplexer circuit.
  • a pulsed droplet deposition apparatus such as a drop-on-demand ink jet printer having a multi-channel array from the channels of which the droplets are ejected and in which the channels are arranged in groups, channels from the respective groups being selected for printing droplets in successive phases of operation of the multiplexer circuit.
  • circuits to handle substantial actuating currents have to be constructed and such currents give rise to risk of burn-out failure.
  • One object of the present invention is to provide a multiplexer circuit for such an application which is called upon to handle only relatively low power. Further, in known forms of pulsed droplet ink jet printed die switching of the substantial actuating currents gives rise to radio fre
  • the present invention consists in a multiplexer circuit for effecting in successive phases of operation thereof actuation of selected devices of respective groups of devices of a series of capacitance actuated devices, characterised in that said circuit comprises a series of parallel connected electrical paths to which the respective devices are adapted to be connected, said paths being adapted for connection in parallel with a signal generator, with two capacitors of each device connected between the path of the associated device and the respective paths on opposite sides of said path of said associated device and first and second switching means disposed in each path and adapted to be closed by respective logic signals applied thereto so that when the first and second switching means of one path are respectively closed and open and the first and second switching means of each of the paths on respective opposite sides of said one path are respectively open and closed, charging of the capacitors connected to said one path takes place and when thereafter the first and second switching means of said one path are respectively open and closed discharge of the capacitors connected to said one path takes place.
  • a diode device is connected across the second switching means of each path and provides a conductive path for discharging capacitors connected between the path in which said diode is connected and the paths on respective opposite sides thereof.
  • the first and second switching means are provided on a silicon chip integrated circuit, said switching means comprising transistor switches.
  • the transistor means comprise field effect transistors.
  • the second switching means of each path comprises first and second switching components of which the first switching component provides a by-pass path in parallel with the second switching component during charging of the capacitors connected between the path containing said second switching means and the paths on opposite sides thereof by way of the first switching means of said paths on opposite sides of the path containing said second switching means, whilst the second switching component provides a conductive path for discharging the capacitors connected to the path containing said second switching component after charging thereof by way of the first switching means contained in the same path as said second switching component.
  • the first and second switching means are provided on a silicon chip integrated circuit, the first switching means comprising a field effect transistor and the first and second switching components of the second switching means comprising respectively a field effect transistor and a field effect transistor controlling conduction of a bipolar transistor.
  • the capacitors of devices selected for actuation are charged in an initial part of a voltage waveform-supplied from the signal generator after which the signal generator is disconnected from the circuit for a further interval of said waveform prior to discharge of the charged capacitors.
  • the signal generator and the parallel electrical paths and the first and second switching means thereof are formed in a silicon chip integrated circuit.
  • the logic signal applying means are adapted to apply signals to the first and second switching means to enable charging of the capacitors of each of the devices selected fob actuation for a period dependent upon the actuated or non-actuated status of devices adjacent each of said selected devices.
  • the invention further consists in a multi-channel array, electrically pulsed droplet deposition apparatus for depositing liquid droplets upon a surface, comprising a droplet deposition head formed from electrically active material, a multiplicity of channels for liquid formed in said head and arranged in a plurality of groups, nozzles communicating with the respective channels, longitudinal side walls each serving to divide one channel from the next and electrically actuable means for effecting transverse displacement in opposite senses of said longitudinal side-walls of each channel, said electrically actuable means comprising electrodes in each channel on respective facing surfaces of the longitudinal channel side-walls, conductive means connecting the electrodes in each channel, said electrodes forming a series of capacitors each consisting of one of said longitudinal channel side walls and the electrodes on opposite sides thereof and a multiplexer circuit for effecting in successive phases of operation actuation of said longitudinal walls of selected channels in the respective channel groups, said circuit comprising a series of parallel electrical paths, said capacitors being connected respectively between successive paths of said electrical paths, a signal generator connected across said parallel
  • the logic signal applying means are adapted to apply signals to the first and second switching means in each of said parallel paths to which the capacitors of selected channels are connected to enable charging of the capacitors of each selected channel for a period to provide a voltage level thereon dependent upon the selected or non-selected status of adjacent channels of the group containing the selected channels.
  • the signal generator is adapted during charging of said capacitors to apply a signal to the capacitors of the selected channels which is of relatively slowly increasing voltage and the logic signal applying means are adapted to effect disconnection of the signal generator from the capacitors of said selected channels when a predetermined charge voltage is reached and after an interval to actuate the switching means to effect rapid discharge of the charged capacitors whereby during charging of the capacitors of the selected channels the longitudinal side walls of the said channel are displaced outwardly relatively slowly and during discharge of the capacitors the channel walls are rapidly returned.
  • Figure 1 illustrates a module part 10 of an ink jet printhead 12 in which a multiplicity of closely spaced drop-on-demand ink drop ejectors are disposed side by side in an array.
  • the ejectors consist of extended parallel channels 20-28 filled with ink and separated by piezo-electric shear mode wall actuators 30-39, such as are disclosed in co-pending European Patent Application No. 88300146.3 the contents of which are herein incorporated by reference.
  • the ink channels 20-28 have electrodes 40-48 coating the walls of each channel, which provide actuating electrodes for the wall actuators and which, together with the wall actuators effectively form capacitors 50 to 58.
  • the electrodes are connected via tracks 70-78 to terminals 60-68 of a silicon chip integrated circuit hereinafter referred to.
  • the ink ejectors are divided separately into two groups of odd and even numbered channels and selected channels in the odd and even numbered groups are actuated in alternating cycles.
  • operation is performed by holding the electrodes of one group (e.g. the even numbered channels) at earth potential and applying a voltage waveform to those channels due to print in the odd group of channels.
  • FIG. 2 shows a signal generator 100 provided in a silicon chip integrated circuit 101 and connected across internal buses 102 and 103 thereof, bus 102 being connected to the positive output terminal of the signal generator and bus 103 to the negative output terminal thereof which is held at ground potential. Between the buses 102 and 103, there are provided parallel electrical paths respectively associated with the actuator channels and of which only paths 113 to 117 are illustrated and these respectively include terminals 63 to 67.
  • the paths 113 to 117 respectively include the collector emitter paths of n-p-n bipolar transistor devices 133 to 137.
  • the base emitter paths of these devices respectively include field effect devices 143 to 147 to the gate electrodes of which are applicable internally generated logic signals to render these devices conductive.
  • the collector emitter paths of devices 133 to 137 are shunted by respective field effect devices 153 to 157 the gate electrodes of which are connected to the gate electrodes of devices 143 to 147 so that these devices are rendered conductive by the same logic signals as activate the devices 143 to 147.
  • the devices 153 to 157 are themselves respectively shunted by diodes 163 to 167 which provide capacitor discharge paths as hereinafter referred to.
  • the logic signals for effecting and terminating conduction of the transistors 123-127, 143-147 and 153-157 are supplied from registers 173-177 of logic block 178 to which is supplied print pattern data on a line 179 and relatively high frequency clock pulses on a line 180 which connects also with the signal generator 100 to which is also connected a clock line 181 on which are supplied relatively low frequency clock pulses.
  • the data stream supplied on line 179 consists of an N bit print pattern applied to each chip of the printhead where N is the number of channels to which the chip is connected.
  • the N bits determine in one cycle which of the channels of the even numbered channel group are to be actuated and in a following cycle which of the channels of the odd numbered channel group are to be actuated.
  • the N bit data stream additionally contains subsets n of data relating to the print status of channels of the same group as those selected for actuation on opposite sides of each of the selected channels which are to be actuated.
  • the data sets n may be four bit words in which case they give the print status of two channels of the same group as the selected channels on each side of each channel selected for actuation. If the data sets n are in the form of six bit words they give the print status of three channels on each side of each channel which is to be actuated.
  • the data N with its subsets n is loaded into the registers 173 to 177 at the rate set by the clock pulses on line 180, suitably about 10MHertz and the data sets n are sent to a look-up table in a ROM (not shown) which sends digital signals respectively determined by the data sets n to the registers 173-177 which signals are stored in the registers and employed to afford a count of pulses on line 180 which determines the level of charging of the capacitors of each actuated channel.
  • the voltage cycles applied by the signal generator 100 across the buses 102 and 103 are initiated by the pulses on the clock line 181 and upon initiation of one such cycle the data stored in the registers 171 to 177 selects for printing the channels of one of the channel groups which have their transistors 123-127 switched on and their transistors 143 to 147 switched off so that charging of the capacitors of the selected channels commences and is terminated by switching off of the transistors 123-127 of the selected channels when the voltage level thereon reaches a value determined by the digital signals stored in the registers 173-179 and supplied thereto from the look-up table referred to.
  • the registers of each of the end channels of modules making up the printhead receive from the ROM sets n of bits which provide the print status of adjoining channels spanning the butted region of the module in which the end channel concerned is located and the adjoining module.
  • the integrated circuit of Figure 2 is a bi-C mos design.
  • FIG 4 illustrates the waveform provided by the signal generator 100 to energise the actuators 30 to 39 during successive phases of the two phase multiplexer circuit circuit of Figure 2.
  • the waveform consists of a charge period ⁇ 1 during which the charge on the capacitors 52 to 57 belonging to one of the channel groups gradually rises to predetermined values for each channel of that group selected for actuation at which the capacitors are disconnected from the signal generator and remain at or substantially at their charged voltage level for a further period, the "hold" period, ⁇ 2, during which the signal voltage is kept at least at the level of the charge voltage.
  • the signal voltage is allowed in this period first to rise above and at the end of the period return to the charge voltage.
  • the signal voltage proceeds to zero to enable reconnection of the signal generator to the capacitors for the next phase of operation. Before that commences a rapid discharge of the capacitors, as hereinafter described, is effected.
  • the wall actuator electrodes of selected channels of say the odd numbered channels 21 to 27 are energised to cause the wall actuators to deform outwards from the channels into a chevron or cantilever form as described in the co-pending European patent application referred to due to the charge voltage and the direction of polarisation of the wall actuators.
  • the rate of rise of voltage is however gradual so that the magnitude of the acoustic waves formed in the ink channels only mildly disturbs the ink menisci in the ejection nozzles of the channels and is not sufficient to eject drops of ink from the nozzles of the even numbered channels adjacent the activated even numbered channels.
  • the charge period ⁇ 1 exceeds the time of travel of acoustic waves in the activated channels so that ⁇ 1 ⁇ L/C where L is the channel length and C is the acoustic wave velocity in the channels.
  • the hold period ⁇ 2 further ink is drawn into the activated odd numbered channels by the action of the acoustic waves and this causes the channel wall actuators to relax outwardly as the ink quantity in the channels increases.
  • the pressure of ink in the selected channels is a maximum and the capacitors of those channels are then rapidly discharged to cause rapid inward movement of the channel actuator walls which generates pressure waves in the selected channels causing ejection of an ink drop from the nozzles of those channels.
  • the next phase of operation is effected on selected even numbered channels by a further signal phase of the signal generator.
  • the capacitors 54 and 55 therefore, relatively slowly, charge to a predetermined voltage during the period ⁇ 1, by way of, in the case of capacitor 54, the field effect devices 125 and 154, and, in the case of capacitor 55, by way of field effect devices 125 and 156, the predetermined voltage being determined by the signal from the ROM stored in register 175.
  • the actuator walls of channel 25 accordingly move outwards allowing flow of ink into that channel and, because of the slow rate of charge, no ink drops are expelled from the adjoining channels.
  • the logic signals to the field effect devices 125 are removed so disconnecting the actuators from the drive circuit signal.
  • Firing that is to say discharge of the capacitor 54 and 55 is effected by applying a signal from the register 175 after a predetermined count of pulses on line 180 to the gate electrodes of the field effect devices 145 and 155 rendering bipolar transistor 135 conducting.
  • This establishes a discharge for capacitor 54 by way of transistor 135 and diode 164 and for capacitor 55 by way of transistor 135 and diode 166.
  • both field effect devices 145 and 155 are conducting, because of the relative resistances of bi-polar transistor 135 and field effect device 155 most of the discharge current flows through transistor 135.
  • capacitors 54 and 55 flow through transistor 135 and divide equally between diodes 164 and 166 and these relatively high discharge currents flow respectively in clockwise and anti-clockwise paths so that the electromagnetic effects thereof effectively cancel out thus minimising radio frequency interference.
  • the heating effect of current in the circuit 101 is largely confined to the capacitor discharge currents and therefore to the turn on time of the bi-polar transistors which lasts, typically 30 n. seconds.
  • discharge of capacitors 54 and 55 takes place in 2 ⁇ seconds causing currents typically of the order of 100mA and resulting in rapid return of the actuator walls of channel 25 to their relaxed positions thereby developing ink drop ejection pressure in channel 25.
  • Figure 3 shows a fragment of an alternative design of two phase multiplexer circuit to that of Figure 2 and which is of C-Mos design. It will be seen that in the parallel paths 114,115,116, the diodes now shunt respective field effect transistors 194,195,196. The requisite logic signals for effecting operation of the circuit are the same as for the circuit of Figure 2 and are not shown.
  • devices 124 to 126 are in a non-conducting condition and devices 194 to 196 are held in a conducting state by a logic signal applied to their gate electrodes.
  • capacitors 54 and 55 are charged during period ⁇ 1 by reason of a logic signal being applied to the gate electrode of field effect devices 125 from the associated register, such as register 175 of Figure 2 and the signal at the gate electrode of device 195 is removed.
  • switch devices of the integrated circuit could include instead of field effect and bi-polar transistors, silicon controlled rectifiers, four layer diodes or other forms of semi-conductor switch devices.

Landscapes

  • Electronic Switches (AREA)
  • Particle Formation And Scattering Control In Inkjet Printers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Circuits Of Receivers In General (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Ink Jet (AREA)
EP89304573A 1988-05-13 1989-05-05 Circuit multiplex Expired - Lifetime EP0341929B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB8811458 1988-05-13
GB888811458A GB8811458D0 (en) 1988-05-13 1988-05-13 Two phase multiplexer circuit
GB888830397A GB8830397D0 (en) 1988-12-30 1988-12-30 Multiplexer circuit
GB8830397 1988-12-30

Publications (3)

Publication Number Publication Date
EP0341929A2 true EP0341929A2 (fr) 1989-11-15
EP0341929A3 EP0341929A3 (fr) 1991-08-14
EP0341929B1 EP0341929B1 (fr) 1995-02-15

Family

ID=26293889

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89304573A Expired - Lifetime EP0341929B1 (fr) 1988-05-13 1989-05-05 Circuit multiplex

Country Status (7)

Country Link
EP (1) EP0341929B1 (fr)
JP (1) JP2666084B2 (fr)
AT (1) ATE118404T1 (fr)
CA (1) CA1321508C (fr)
DE (1) DE68921091T2 (fr)
ES (1) ES2067538T3 (fr)
GR (1) GR3015062T3 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992022429A1 (fr) * 1991-06-17 1992-12-23 Xaar Limited Appareil permettant de deposer des gouttelettes dans un reseau de canaux multiples
FR2705279A1 (fr) * 1993-05-14 1994-11-25 Toxot Science & Appl Générateur de tensions de charges électriques des gouttes émises dans une imprimante à jet d'encre multibuse.
EP0779151A3 (fr) * 1995-12-14 1997-11-12 Kabushiki Kaisha TEC Dispositif d'entraínement de tête pour imprimante à jet d'encre

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04369861A (ja) * 1991-06-19 1992-12-22 Matsushita Electric Ind Co Ltd 化合物半導体集積回路用容量素子の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4350989A (en) * 1979-03-19 1982-09-21 Hitachi, Ltd. Ink-jet printing apparatus
GB2104005A (en) * 1981-07-02 1983-03-02 Suwa Seikosha Kk Ink jet printer head

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4350989A (en) * 1979-03-19 1982-09-21 Hitachi, Ltd. Ink-jet printing apparatus
GB2104005A (en) * 1981-07-02 1983-03-02 Suwa Seikosha Kk Ink jet printer head

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992022429A1 (fr) * 1991-06-17 1992-12-23 Xaar Limited Appareil permettant de deposer des gouttelettes dans un reseau de canaux multiples
US5463414A (en) * 1991-06-17 1995-10-31 Xaar Limited Multi-channel array droplet deposition apparatus
US6991323B1 (en) 1991-06-17 2006-01-31 Xaar Technology Limited Multi-channel array droplet deposition apparatus
FR2705279A1 (fr) * 1993-05-14 1994-11-25 Toxot Science & Appl Générateur de tensions de charges électriques des gouttes émises dans une imprimante à jet d'encre multibuse.
EP0779151A3 (fr) * 1995-12-14 1997-11-12 Kabushiki Kaisha TEC Dispositif d'entraínement de tête pour imprimante à jet d'encre
US6113209A (en) * 1995-12-14 2000-09-05 Toshiba Tec Kabushiki Kaisha Driving device for electrostrictive ink-jet printer head having control circuit with switching elements for setting electrical potential ranges of power supply to electrodes of the printer head
SG83183A1 (en) * 1995-12-14 2001-09-18 Tokyo Electric Co Ltd Head driving device for ink-jet printer

Also Published As

Publication number Publication date
DE68921091T2 (de) 1995-06-14
CA1321508C (fr) 1993-08-24
GR3015062T3 (en) 1995-05-31
ES2067538T3 (es) 1995-04-01
DE68921091D1 (de) 1995-03-23
EP0341929B1 (fr) 1995-02-15
JPH0218054A (ja) 1990-01-22
JP2666084B2 (ja) 1997-10-22
ATE118404T1 (de) 1995-03-15
EP0341929A3 (fr) 1991-08-14

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