EP0224707A1 - Dispositif pour contrôler plusieurs signaux électriques analogues - Google Patents

Dispositif pour contrôler plusieurs signaux électriques analogues Download PDF

Info

Publication number
EP0224707A1
EP0224707A1 EP19860114814 EP86114814A EP0224707A1 EP 0224707 A1 EP0224707 A1 EP 0224707A1 EP 19860114814 EP19860114814 EP 19860114814 EP 86114814 A EP86114814 A EP 86114814A EP 0224707 A1 EP0224707 A1 EP 0224707A1
Authority
EP
European Patent Office
Prior art keywords
signal
comparator
reference value
circuit arrangement
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19860114814
Other languages
German (de)
English (en)
Other versions
EP0224707B1 (fr
Inventor
Wolfgang Esser
Peter Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wincor Nixdorf International GmbH
Original Assignee
Wincor Nixdorf International GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wincor Nixdorf International GmbH filed Critical Wincor Nixdorf International GmbH
Publication of EP0224707A1 publication Critical patent/EP0224707A1/fr
Application granted granted Critical
Publication of EP0224707B1 publication Critical patent/EP0224707B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16528—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values using digital techniques or performing arithmetic operations

Definitions

  • the invention relates to a circuit arrangement for the automatic monitoring of a plurality of analog electrical signals for compliance with predetermined tolerance ranges by successive comparisons with reference values and comparison-dependent generation and storage of error signals.
  • a circuit arrangement of this type is known from US Pat. No. 4,454,500.
  • This object is achieved according to the invention for a circuit arrangement of the type mentioned above in that clock-controlled access to a reference value memory takes place simultaneously with the connection of the respective signal to be monitored to a comparator, from which reference values assigned to each signal and defining a tolerance range are successively read out clock-controlled and the Comparator are supplied and that the respective output signal of the comparator for generating similar error signals to be stored is logically linked with an evaluation signal that indicates which of the two reference values is present at the comparator.
  • the invention thus provides that the successive connection of the respective signal to be monitored is coordinated with the connection of previously stored reference values in a clock-controlled, time-related assignment to one another and that similar error signals generated in a specific logic combination are stored. Overall, this enables a cyclical, automatic interrogation of several monitoring points in an electrical device, the monitoring results being able to be extracted from a memory as a bundle of statements after a respective cycle. By using a reference value memory, it is possible for each of the like monitoring cycle based on new reference values for each analog signal.
  • the digital output signal of a comparator When a reference value is exceeded by an input signal, the digital output signal of a comparator has the state L, for example. If a reference value is undershot, it then has the state H. If a single comparator is used, the respective reference value can be exceeded and the reference value undercut Comparison can only be recognized by a certain error signal state, that is, either only by state L or only by state H. Therefore, the invention provides for the generation of an error signal with a certain state by logically combining the output signal of the comparator with an evaluation signal identifying the respectively effective reference value, so that exceeding or falling below a reference value is similar, i.e. is signaled as a deviation from the specified tolerance range.
  • a multiplexer is provided for the successive supply of the analog electrical signals to the comparator.
  • the lines carrying the signals to be monitored can be connected to the comparator in a simple manner one after the other by appropriate multiplexer addressing.
  • the comparator for control with the reference values is connected via a digital / analog converter to the reference value memory containing the reference values digitally.
  • the reference value memory is freely programmable, then in the reference digitally stored reference values can be changed as desired.
  • the reference value memory contains, for each signal to be monitored, the small or large reference value under an even-numbered address and the large or small reference value under the next higher, odd-numbered address, and becomes the reference value memory with successive double frequency compared to the multiplexer increasing address sequence addressed. This ensures in a simple manner that the comparator is supplied with the reference values one after the other with each signal to be monitored.
  • the evaluation signal which indicates which of the two reference values is in each case on the Kompara Tor is present, advantageously formed by counter bit 0 of the binary counter. If the reference value memory contains, for example, the small reference value for each signal to be monitored under an even-numbered address and the large reference value under the next higher, odd-numbered address, counter bit 0 of the binary counter is in state L when a small reference value is being read from the reference value memory. and in state H when a large reference value is being read from the reference value memory.
  • the respective output signal of the comparator is logically combined with the signal of counter bit 0 of the binary counter by an EXCLUSIVE OR gate.
  • the small reference value is stored in the reference value memory for each signal to be monitored under an even-numbered address and the large reference value under the next higher, odd-numbered address, and the output signal of the comparator assumes the state L if a monitored signal is greater than a reference value, and the state H on, if a monitored signal is less than a reference value
  • the EXCLUSIVE-OR combination of the respective comparator output signal with the signal of the counter bit 0 of the binary counter, which addresses the reference value memory results in a uniform error signal, which in the state H signals that the small reference value has been fallen short of or the large reference value has been exceeded, that is to say a deviation from the specified tolerance range.
  • the multiplexer and the comparator are connected to one another via a holding element which can be controlled with regard to the takeover of the respective multiplexer output signal, the control input of which is connected to the output of an AND element which connects the inverted signal of the counter bit 0 of the binary counter to a linked this incrementing clock signal.
  • the holding element is used for the defined takeover and temporary storage of the respective multiplexer output signal.
  • the error signals occurring in one monitoring cycle are stored in a shift register until the start of the next monitoring cycle.
  • This has the advantage that the shift register content can be evaluated at the end of a monitoring cycle. In this way, it can be determined at which analog electrical signal a limit value has been exceeded or fallen below.
  • a control unit is provided in a further advantageous embodiment of the invention, which further controls the programming of the reference value memory between two monitoring cycles and the defined starting and stopping of the monitoring cycles.
  • Fig. L shows a circuit arrangement for intermittent automatic monitoring of several analog electrical signals with regard to compliance with predetermined tolerance ranges. It contains a multiplexer l0, at its on gears L2 the analog electrical signals to be monitored are present.
  • the output l4 of the multiplexer l0 is connected to the measuring input l8 of a comparator 20 via a holding element l6 which is controllable with regard to the takeover of the respective multiplexer output signal.
  • the reference input 22 of the comparator 20 is connected to the analog output 25 of a digital / analog converter 24, the digital input of which is connected on the one hand to a control unit 26 and to the data output 28 of a read / write memory 30 which serves as a reference value memory.
  • the address inputs 32 of this reference value memory 30 are connected to the control unit 26 for the purpose of storing the reference values. Furthermore, they are connected to all counter bits 0 to N of a binary counter 34, the counter bits 1 to N of which are also connected to the address inputs 36 of the multiplexer l0.
  • the binary counter 34 is driven by a clock signal CL via its clock input 38. Its count direction input 40 and its count preset input 42 are also connected to the control unit 26.
  • the reference value memory 30 is also connected to the control unit 26 with its data input 44 and with its write input 46 for storing the reference values.
  • the holding element l6 is connected at its control input 48 to the output 50 of an AND gate 52 with an inverting input, which links the inverted signal ZB 0 of the counter bit 0 of the binary counter 34 with the clock signal CL.
  • This logical combination has the effect that the respective multiplexer output signal only in the event of an even number of binary counters 34, ie when the address of the multiplexer l0 has just been incremented by 1, transferred to the holding element l6 and from its output l7 to the measurement input l8 of the comparator 20 is placed.
  • the output 54 of the comparator 20 is connected to an input of an EXCLUSIVE-OR gate 56, which combines the output signal of the comparator 20 with the signal ZB 0 of the counter bit 0 of the binary counter 34. Any error signals then appear at the output 58 of this EXCLUSIVE OR element 56, which indicate a reference value overshoot and a reference value undershoot in the same way by a signal to be monitored.
  • the error signals occurring in a monitoring cycle are supplied directly to the control unit 26 via a connecting line 60, and are temporarily stored in a shift register 62 until the start of the next monitoring cycle and only then supplied to the control unit 26 via its output 64.
  • the shift register 62 like the binary counter 34, is controlled by the clock signal CL via its clock input 66.
  • the control unit 26 is connected via its connection 68 to an electronic data processing system (not shown) for the purpose of presetting the binary counter, storing the reference values in the reference value memory 30 and evaluating the error signals buffered in the shift register 62.
  • the analog electrical signals to be monitored are fed to, for example, 2 N inputs l2 of multiplexer l0.
  • the address inputs 36 of the multiplexer 10 are driven by the counter bits 1 to N of the binary counter 34.
  • the reference value memory 30 is addressed with the counter bits 0 to N of the binary counter 34.
  • the reference value memory 30 contains the small reference value under an even-numbered address (including address 0) and the large reference value under the next higher, odd-numbered address. These reference values were stored during an initialization phase under the control of the control unit 26 by an electronic data processing system (not shown in FIG. 1).
  • the binary counter 34 is preset to the counter reading 2 N + 1 - 1, likewise under the control of the control unit 26. Since the signals of all the counter bits of the binary counter 34 are in state H at this counter reading, the signals of all counter bits 0 to N assume the state L when the first positive clock edge occurs when the monitoring cycle has started. Both the multiplexer 10 and the reference value memory 30 are then addressed with an address which has the state L at all address locations. At this address, the analog input l of the multiplexer l0 is connected to its output l4, so that the first signal to be monitored is fed to the holding element l6.
  • the control input 48 of the holding element l6 is acted upon by the AND element 52 by a signal having the state H, so that the signal present at the holding element l6 is taken over by it and thus fed to the measuring input 18 of the comparator 20.
  • the address 0 in the reference value memory 30 for the first signal to be monitored is digitally ge stored small reference value is read out and fed to the reference input 22 of the comparator 20 via the digital / analog converter 24. Since the first signal to be monitored has a voltage of 2 V and thus exceeds the reference value of 1 V stored in address 0 in the reference value memory 30, the comparator output signal maintains its L state. This comparator output signal is combined with the signal ZB 0 of the counter bit 0 in the EXCLUSIVE OR gate 56. Since the signal ZB 0 of the counter bit 0 has the state L, the signal appearing at the output 58 of the EXCLUSIVE-OR gate 56 assumes the state L in accordance with the output signal of the comparator 20.
  • the current state of the output signal of the EXCLUSIVE-OR gate 56 is transferred to the shift register 62.
  • the binary counter 34 is incremented by 1 with this positive edge, so that the signal of the counter bit 0 now has the state H. Since counter bit 0 is not connected to multiplexer l0, the first signal to be monitored remains at output l4 of multiplexer l0. The holding element l6 is locked because the output signal of the AND gate 52 present at its control input 48 assumes the state L when the counter bit 0 has the state H.
  • the next incrementing of the binary counter 34 leads to the fact that the small reference value of ⁇ 1 V stored in the reference value memory 30 under the address 4 for the third 3 V signal to be monitored is fed to the comparator 20. Furthermore, the analog input 3 of the multiplexer l0 is connected to its output l4. Since the signal to be monitored with 3 V is not below the small reference value of - 1 V, there is no error signal at the output 58 of the EXCLUSIVE-OR gate 56. This is only possible with further incrementing of the binary counter 34, if the one under address 5 stored large reference value of 1 V is fed to the comparator 20. Since the signal to be monitored is then 3 V above the large reference value of 1 V, an error signal is generated. These measurement steps can also be seen in the illustration in FIG. 2.
  • the error signals that have just occurred in the monitoring cycle that has just ended and are stored in the shift register 62 can be evaluated in an electronic data processing system before the start of the next monitoring cycle.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
EP86114814A 1985-11-22 1986-10-24 Dispositif pour contrôler plusieurs signaux électriques analogues Expired - Lifetime EP0224707B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19853541343 DE3541343A1 (de) 1985-11-22 1985-11-22 Schaltungsanordnung zur intermittierenden selbsttaetigen ueberwachung mehrerer analoger elektrischer signale
DE3541343 1985-11-22

Publications (2)

Publication Number Publication Date
EP0224707A1 true EP0224707A1 (fr) 1987-06-10
EP0224707B1 EP0224707B1 (fr) 1991-01-16

Family

ID=6286585

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86114814A Expired - Lifetime EP0224707B1 (fr) 1985-11-22 1986-10-24 Dispositif pour contrôler plusieurs signaux électriques analogues

Country Status (4)

Country Link
US (1) US4890095A (fr)
EP (1) EP0224707B1 (fr)
JP (1) JPS62175038A (fr)
DE (2) DE3541343A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19601881A1 (de) * 1996-01-19 1997-07-24 Siemens Ag Überwachungseinrichtung für Strom- und Leistungsaufnahme
WO2005008896A1 (fr) * 2003-07-14 2005-01-27 Infineon Technologies Ag Circuit electrique et procede pour tester des composants electroniques
EP2911477A1 (fr) * 2014-02-25 2015-08-26 Pintsch Bamag Antriebs- und Verkehrstechnik GmbH Dispositif et son utilisation destiné à surveiller des éclairages à DEL

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3709805A1 (de) * 1987-03-25 1988-10-13 Kloeckner Moeller Elektrizit Verarbeitungsmodul zur erfassung analoger eingangsgroessen, insbesondere fuer mikroprozessorsysteme und speicherprogrammierbare steuerungen
DE8909649U1 (de) * 1989-08-11 1990-12-06 Siemens AG, 1000 Berlin und 8000 München Signalumsetzer mit freibleibendem Eingangsspannungspegel
US5111203A (en) * 1990-11-27 1992-05-05 Data Translation, Inc. Circuitry for conditioning analog signals and converting to digital form
US5416727A (en) * 1992-12-15 1995-05-16 American Ceramic Service Company Mobile process monitor system for kilns
US5372155A (en) * 1993-11-02 1994-12-13 You; Ching-Chuan Joint mechanism for an umbrella
TW576959B (en) * 2001-01-22 2004-02-21 Tokyo Electron Ltd Productivity enhancing system and method thereof of machine
DE10307690A1 (de) * 2003-02-21 2004-05-27 Infineon Technologies Ag Vorrichtung sowie Verfahren zur Toleranzanalyse von digitalen und/oder digitalisierten Messwerten
ES2374514T3 (es) * 2009-09-29 2012-02-17 Leuze Electronic Gmbh + Co. Kg Sensor óptico.
US8633844B2 (en) * 2012-01-31 2014-01-21 Silicon Laboratories Inc. Performing digital windowing in an analog-to-digital converter (ADC)
US9831889B1 (en) 2016-10-31 2017-11-28 Silicon Laboratories Inc. Converting large input analog signals in an analog-to-digital converter without input attenuation
US9742423B1 (en) 2016-10-31 2017-08-22 Silicon Laboratories Inc Separating most significant bits and least significant bits in charge storage elements of an analog-to-digital converter
CN108562784B (zh) * 2018-03-14 2024-03-29 杭州思泰微电子有限公司 一种应用于磁电流传感器的快速过流检测电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1284987B (de) * 1964-11-23 1968-12-12 Hawker Siddeley Dynamics Ltd Analog-Digital-Umsetzer mit Grenzwertvergleich
DE1944191B2 (de) * 1969-08-30 1971-01-14 Siemens Ag Anordnung zum Umsetzen von Analogwerten in Digitalwerte
DE3002199A1 (de) * 1979-01-26 1980-07-31 Hitachi Ltd Komparator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1284987B (de) * 1964-11-23 1968-12-12 Hawker Siddeley Dynamics Ltd Analog-Digital-Umsetzer mit Grenzwertvergleich
DE1944191B2 (de) * 1969-08-30 1971-01-14 Siemens Ag Anordnung zum Umsetzen von Analogwerten in Digitalwerte
DE3002199A1 (de) * 1979-01-26 1980-07-31 Hitachi Ltd Komparator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN, Band 32, Nr. 25, Dezember 1984, Seite 269, Waseca, MN, US; C. PANASUK: "CMOS comparator chip multiplexes 4 inputs under digital control" *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19601881A1 (de) * 1996-01-19 1997-07-24 Siemens Ag Überwachungseinrichtung für Strom- und Leistungsaufnahme
WO2005008896A1 (fr) * 2003-07-14 2005-01-27 Infineon Technologies Ag Circuit electrique et procede pour tester des composants electroniques
US7912667B2 (en) 2003-07-14 2011-03-22 Infineon Technologies Ag Electrical circuit and method for testing electronic component
EP2911477A1 (fr) * 2014-02-25 2015-08-26 Pintsch Bamag Antriebs- und Verkehrstechnik GmbH Dispositif et son utilisation destiné à surveiller des éclairages à DEL

Also Published As

Publication number Publication date
EP0224707B1 (fr) 1991-01-16
DE3541343A1 (de) 1987-06-25
JPH0357660B2 (fr) 1991-09-02
US4890095A (en) 1989-12-26
JPS62175038A (ja) 1987-07-31
DE3676963D1 (de) 1991-02-21

Similar Documents

Publication Publication Date Title
EP0224707B1 (fr) Dispositif pour contrôler plusieurs signaux électriques analogues
DE2721319C2 (de) Rekonfigurationseinrichtung
DE3818546C2 (fr)
DE2340547B2 (de) Schaltungsanordnung zum testen logischer schaltungen
DE2162486A1 (de) Digital gesteuerter Impulsgenerator
DE2725396C3 (fr)
DE2748529A1 (de) Ueberwachungsschaltung
DE2258884A1 (de) Einrichtung und verfahren zur pruefung elektronischer geraete
DE2536625C2 (de) Paritätsprüfschaltung für ein binär zählendes Register
DE2746743C2 (de) Verfahren und Anordnung zur computergesteuerten Erzeugung von Impulsintervallen
DE2917126C2 (de) Verfahren zum Prüfen einer integrierten Schaltung und Anordnung zur Durchführung des Verfahrens
EP0012185A1 (fr) Circuit de test pour le fonctionnement synchrone de générateurs de cadence
DE2829709A1 (de) Verfahren und anordnung zur erzeugung zeitlich unmittelbar aufeinanderfolgender impulszyklen
DE2828285A1 (de) Verfahren und vorrichtung zur erzeugung und verarbeitung elektrischer impulse
DE3023699A1 (de) Verfahren und anordnung zur erzeugung von impulsen vorgegebener zeitrelation innerhalb vorgegebener impulsintervalle mit hoher zeitlicher aufloesung
DE2242279C3 (de) Schaltungsanordnung zur Ermittlung von Fehlern in einer Speichereinheit eines programmgesteuerten Datenvermittlungssystems
DE19651713C2 (de) Bauelement-Testgerät zum Testen elektronischer Bauelemente
DE2455440A1 (de) Verifizierungsanordnung
DE69006388T2 (de) Digitaldatengenerator.
DE2133729C3 (de) Anordnung mit einer Kaskadenschaltung einer Anzahl von Speicherelementen
AT391952B (de) Schaltungsanordnung zur auswertung eines von einem pruefling, z.b. einer flachbaugruppe, abgegebenen testsignals
DE3240891C2 (de) Zählschaltung zum Messen von Zeitintervallen
DE3650136T2 (de) Schaltung zur Speicherschaltzustanderkennung.
DE3417816A1 (de) Programmierbares schaltnetz
DE2931417C2 (de) Schaltungsanordnung zum gezielten Unterbrechen des Funktionsablaufs einer Steuerschaltung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE ES FR GB GR IT LI LU NL SE

17P Request for examination filed

Effective date: 19870507

RBV Designated contracting states (corrected)

Designated state(s): CH DE FR GB IT LI NL SE

17Q First examination report despatched

Effective date: 19900403

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SIEMENS NIXDORF INFORMATIONSSYSTEME AKTIENGESELLSC

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): CH DE FR GB IT LI NL SE

REF Corresponds to:

Ref document number: 3676963

Country of ref document: DE

Date of ref document: 19910221

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
ITF It: translation for a ep patent filed

Owner name: MODIANO & ASSOCIATI S.R.L.

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19920914

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19921016

Year of fee payment: 7

Ref country code: FR

Payment date: 19921016

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19921031

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19921216

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19930121

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19931024

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19931025

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19931031

Ref country code: CH

Effective date: 19931031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19940501

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19931024

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19940630

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19940701

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

EUG Se: european patent has lapsed

Ref document number: 86114814.6

Effective date: 19940510

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20051024