EP0182430B1 - Light-emitting diodes array and method for its production - Google Patents

Light-emitting diodes array and method for its production Download PDF

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Publication number
EP0182430B1
EP0182430B1 EP85201836A EP85201836A EP0182430B1 EP 0182430 B1 EP0182430 B1 EP 0182430B1 EP 85201836 A EP85201836 A EP 85201836A EP 85201836 A EP85201836 A EP 85201836A EP 0182430 B1 EP0182430 B1 EP 0182430B1
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European Patent Office
Prior art keywords
layer
diodes
iii
lines
conductivity type
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German (de)
French (fr)
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EP0182430A1 (en
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Jacques Varon
Marc Mahieu
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Radiotechnique Compelec RTC SA
Koninklijke Philips NV
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Radiotechnique Compelec RTC SA
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the subject of the present invention is a matrix of light-emitting diodes comprising at least one active layer of III-V material of a first type of conductivity and a surface injection layer of Ill-V material of the second type of opposite conductivity and zones semi-insulators arranged at least along columns and extending over the thickness of the injection layer and of the active layer so as to separate at least partially in said layers the individual diodes and to receive at least some of the contacts conductors.
  • the semi-insulating zones also extend along the lines so as to produce optimal electrical insulation between the adjacent diodes.
  • the invention also relates to a method of manufacturing the above-mentioned matrix.
  • the thickness e o of the layer 2 depends (all other things being equal) on the admissible series resistance.
  • the width 1 of the zones 8 is preferably as small as possible, on the one hand because they only perform an electrical isolation function between the adjacent regions 4 (diode in reverse) and on the other hand because since the localization layer 7 does not need to have a thickness greater than a few microns, it only occurs during epitaxy that an imperfect compensation of the gra din produced by the openings 3, resulting in unevenness in the surface of the layer 5 which it is preferable not to accentuate too much. It will be noted that these level inequalities have no influence on the operation since they occur at places where the layers subsequently deposited are subsequently made semi-insulating.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Devices (AREA)

Description

La présente invention a pour objet une matrice de diodes électroluminescentes comportant au moins une couche active en matériau III-V d'un premier type de conductivité et une couche superficielle d'injection en matériau Ill-V du second type de conductivité opposé et des zones semi-isolantes disposées au moins suivant des colonnes et s'étendant sur l'épaisseur de la couche d'injection et de la couche active de manière à séparer au moins partiellement dans lesdites couches les diodes individuelles et à recevoir au moins une partie des contacts conducteurs.The subject of the present invention is a matrix of light-emitting diodes comprising at least one active layer of III-V material of a first type of conductivity and a surface injection layer of Ill-V material of the second type of opposite conductivity and zones semi-insulators arranged at least along columns and extending over the thickness of the injection layer and of the active layer so as to separate at least partially in said layers the individual diodes and to receive at least some of the contacts conductors.

Une telle matrice est connue de la demande de brevet français FR-A-2491714 au nom de la Demanderesse, déposée le 6 octobre 1980 et intitulée « DISPOSITIF SEMICONDUCTEUR A DIODES ELECTROLUMINESCENTES LOCALI-SEES ET SON PROCEDE DE FABRICATION •.Such a matrix is known from French patent application FR-A-2491714 in the name of the Applicant, filed on October 6, 1980 and entitled "SEMICONDUCTOR DEVICE WITH LOCALIZED LIGHT-EMITTING DIODES AND ITS MANUFACTURING PROCESS.

Cette demande décrit une matrice de diodes pour laquelle les contacts reliant ligne par ligne une électrode des diodes et l'autre électrode colonne par colonne sont disposés sur une face et présentent des languettes de contact situées au-dessus des régions actives d'émission. Cette disposition ne convient que pour des diodes intrinsèquement de grandes dimensions pour lesquelles la perte de lumière due aux languettes de contact n'est pas trop importante.This application describes an array of diodes for which the contacts connecting line by line one electrode of the diodes and the other electrode column by column are arranged on one face and have contact tabs located above the active emission regions. This arrangement is only suitable for intrinsically large diodes for which the loss of light due to the contact tabs is not too great.

Selon l'invention, les contacts sont disposés sur deux races opposées de la matrice et celle-ci présente une couche de localisation enterrée qui permet de limiter la zone d'émission de chaque diode. Les contacts peuvent alors être disposés en dehors de la zone d'émission, donc sans perte de rendement, et sur une partie substantielle, et ou le cas échéant, sur tout le pourtour de chaque diode. La matrice selon l'invention est dans ce but caractérisée en ce que chaque zone semi-isolante s'étend depuis la surface de la couche d'injection jusqu'à une zone de localisation en matériau III-V de composition binaire et du second type de conductivité, les zones de localisation présentant en section transversale chacune une partie supérieure et une partie inférieure, les parties supérieures délimitant un réseau à deux dimensions d'alvéoles remplies par des prolongements de la couche active, et les parties inférieures étant espacées par régions semi-conductrices de contact électrique à niveau de dopage élevé du premier type de conductivité, disposées parallèlement aux lignes de manière à interconnecter les diodes ligne par ligne au niveau desdits prolongements et en ce qu'elle comporte, sur la couche d'injection, des métallisations de contact électrique comprenant, pour chaque diode, des régions de contact délimitées intérieurement sensiblement jusqu'à l'aplomb des parties supérieures des zones de localisation et interconnectées colonne par colonne, les colonnes d'interconnexion ainsi constituées étant isolées électriquement les unes par rapport aux autres par les zones semi-isolantes disposées selon les colonnes.According to the invention, the contacts are arranged on two opposite races of the matrix and the latter has a buried localization layer which makes it possible to limit the emission zone of each diode. The contacts can then be placed outside the emission zone, therefore without loss of efficiency, and over a substantial part, and or if necessary, around the entire periphery of each diode. The matrix according to the invention is for this purpose characterized in that each semi-insulating zone extends from the surface of the injection layer to a localization zone made of III-V material of binary composition and of the second type of conductivity, the localization zones each having in cross section an upper part and a lower part, the upper parts delimiting a two-dimensional network of cells filled with extensions of the active layer, and the lower parts being spaced apart by semi regions -conductive electrical contact with high doping level of the first type of conductivity, arranged parallel to the lines so as to interconnect the diodes line by line at the level of said extensions and in that it comprises, on the injection layer, metallizations of electrical contact comprising, for each diode, contact regions delimited internally substantially up to the plumb of the upper parts location zones and interconnected column by column, the interconnection columns thus formed being electrically insulated from each other by the semi-insulating zones arranged according to the columns.

Les couches actives et d'injection peuvent être de composition binaire ou ternaire.The active and injection layers can be of binary or ternary composition.

L'invention s'applique tout particulièrement au cas où la composition binaire est le GaAs et la composition ternaire le GaAIAs.The invention applies very particularly to the case where the binary composition is GaAs and the ternary composition is GaAIAs.

Selon un mode préféré, les zones semi-isolantes s'étendent également selon les lignes de manière à produire une isolation électrique optimale entre les diodes adjacentes.According to a preferred mode, the semi-insulating zones also extend along the lines so as to produce optimal electrical insulation between the adjacent diodes.

L'invention concerne également un procédé de fabrication de la matrice précitée.The invention also relates to a method of manufacturing the above-mentioned matrix.

Dans ce procédé, conformément à l'art antérieur précité, une couche d'injection et une couche active du type Ill-V sont réalisées par hétéroé- pitaxie sur un substrat, et les diodes individuelles sont séparées au moins partiellement en bombardant des régions délimitées pour former au moins des colonnes de zones semi-isolantes sur l'épaisseur de la couche d'injection et de la couche active.In this method, in accordance with the aforementioned prior art, an injection layer and an active layer of the Ill-V type are produced by heteroepitaxy on a substrate, and the individual diodes are separated at least partially by bombarding delimited regions. to form at least columns of semi-insulating zones over the thickness of the injection layer and of the active layer.

Le procédé de l'art antérieur conduit à une structure dont les inconvénients ont été mentionnés plus haut. Le procédé selon l'invention met en oeuvre des opérations de décapage de certaines couches épitaxiées permettant d'enterrer des lignes de contact et des zones de localisation, ces dernières limitant l'émission lumineuse à des régions pour lesquelles la lumière émise n'est pas absorbée par des contacts électriques déposés, d'où un rendement optimal.The method of the prior art leads to a structure whose drawbacks have been mentioned above. The method according to the invention implements stripping operations of certain epitaxial layers making it possible to bury contact lines and localization zones, the latter limiting the light emission to regions for which the light emitted is not absorbed by deposited electrical contacts, resulting in optimal performance.

Dans ce but, le procédé comporte les étapes suivantes :

  • -dépôt épitaxique sur le substrat d'une première couche 111-V de composition binaire fortement dopée d'un premier type de conductivité.
  • -décapage dans ladite première couche d'un premier groupe d'ouvertures disposées parallèlement aux lignes selon un pas donné, les parties subsistantes de la première couche formant des régions semi-conductrices de contact électrique interconnectant les diodes ligne par ligne.
  • -dépôt épitaxique d'une deuxième couche III-V de composition binaire du second type de conductivité.
  • -dans le but de former une couche de localisation, décapage dans ladite deuxième couche III-V d'un second groupe d'ouvertures formant un réseau à deux dimensions décalé selon les lignes d'un demi-pas par rapport à celles du premier groupe, lesdites ouvertures de la deuxième couche étant ménagées à une partie supérieure de la couche de localisation qui recouvre en partie lesdites régions semi-conductrices de contact électrique.
  • -dépôt épitaxique successivement de la couche active du premier type de conductivité et de la couche d'injection du second type de conductivité.
  • -réalisation dudit bombardement,
  • -réalisation de métallisations de contact électrique sur. la couche d'injection lesquelles comportent pour chaque diode d'une part des régions de contact s'étendant intérieurement parallèlement aux lignes sensiblement jusqu'à l'aplomb des parties supérieures de la couche de localisation et interconnectées colonne par colonne, les colonnes d'interconnexion ainsi constituées étant isolées électriquement les unes par rapport aux autres par les zones semi-isolantes disposées selon les colonnes
To this end, the method comprises the following steps:
  • -epitaxial deposit on the substrate of a first layer 111-V of binary composition highly doped with a first type of conductivity.
  • stripping in said first layer of a first group of openings arranged parallel to the lines at a given pitch, the remaining parts of the first layer forming semiconductor regions of electrical contact interconnecting the diodes line by line.
  • -epitaxial deposit of a second III-V layer of binary composition of the second type of conductivity.
  • -with the aim of forming a localization layer, pickling in said second III-V layer of a second group of openings forming a two-dimensional network offset along the lines by half a step relative to those of the first group , said openings of the second layer being formed at an upper part of the localization layer which partly covers said semiconductor regions of electrical contact.
  • epitaxial deposition successively of the active layer of the first type of conductivity and of the injection layer of the second type of conductivity.
  • -realization of said bombing,
  • - realization of electrical contact metallizations on. the injection layer which compor tent for each diode on the one hand contact regions extending internally parallel to the lines substantially up to the plumb of the upper parts of the localization layer and interconnected column by column, the interconnection columns thus formed being electrically isolated relative to each other by the semi-insulating zones arranged according to the columns

L'étape de bombardement peut être telle qu'elle forme également des lignes de régions semi-isolantes de manière à produire une isolation électrique optimale entre les diodes adjacentes.The bombardment step can be such that it also forms lines of semi-insulating regions so as to produce optimal electrical insulation between the adjacent diodes.

La couche de composition binaire est avantageusement en As-Ga. Les couches actives et d'injection peuvent être de composition binaire, par exemple As-Ga, ou ternaire, par exemple GaAIAs.The binary composition layer is advantageously made of As-Ga. The active and injection layers can be of binary composition, for example As-Ga, or ternary, for example GaAIAs.

L'invention sera mieux comprise à la lecture de la description qui va suivre donnée à titre d'exemple non limitatif, en liaison avec les figures qui représentent :

  • Les figures 1a à 1e, en coupe verticale, et pour les figures 1a et 1c en perspective, les différentes étapes du procédé de fabrication ;
  • la figure 2, une vue de dessus de la figure 1e ; et la figure 3, une variante de la figure 2.
The invention will be better understood on reading the description which follows given by way of nonlimiting example, in conjunction with the figures which represent:
  • Figures 1a to 1e, in vertical section, and for Figures 1a and 1c in perspective, the different stages of the manufacturing process;
  • Figure 2, a top view of Figure 1e; and FIG. 3, a variant of FIG. 2.

Selon la figure 1a, un substrat 1 en GaAs semi- isolant ou bien de type n est revêtu par épitaxie liquide d'une couche 2 de GaAs de type p+ (dopée de l'ordre de 1019 cm-3 et d'une épaisseur eo de l'ordre de 4 à 6 microns. On dépose sur cette couche un masque dans lequel ont été ménagées des ouvertures disposées selon des lignes sensiblement équidistantes de pas donné de manière à permettre par décapage à l'aide d'une solution dont la composition en volume est de l'ordre de 96 H2SO4-2H2O2 -2H20, la réalisation d'ouvertures 3. Les parties subsistantes 4 de la couche 2 constituent des régions conductrices disposées selon des lignes.According to FIG. 1a, a semi-insulating or n-type GaAs substrate 1 is coated by liquid epitaxy with a layer 2 of p + type GaAs (doped on the order of 10 19 cm- 3 and with a thickness e o of the order of 4 to 6 microns. A mask is deposited on this layer in which openings have been made arranged in substantially equidistant lines of given pitch so as to allow by etching using a solution of which the volume composition is of the order of 96 H 2 SO 4 -2H 2 O 2 -2H 2 0, the production of openings 3. The remaining parts 4 of the layer 2 constitute conductive regions arranged in lines.

Selon la figure 1 b, on réalise ensuite par épitaxie le dépôt d'une couche 5 en GaAs de type n (dopage de l'ordre de 10 cm-3), d'une surépaisseur e1 d'environ 2 à 4 microns.According to FIG. 1 b, the deposition of a layer 5 of n-type GaAs (doping of the order of 10 cm- 3 ), with an extra thickness e 1 of approximately 2 to 4 microns, is then carried out by epitaxy.

Selon la figure 1c, cette couche 5 est revêtue d'un masque dans lequel ont été ménagées des ouvertures formant un réseau à deux dimensions lequel est, selon les lignes, de même pas que pour la figure 1a, mais décalé latéralement d'un demi-pas. A l'aide d'une solution de H2S04-H202 -H20 telle que mentionnée ci-dessus, on décape des ouvertures 6. Il subsiste alors de la couche 5 un réseau à deux dimensions de zones de localisation espacées les unes des autres et comprenant selon les lignes et les colonnes chacune une partie supérieure 7 et une partie inférieure 8.According to Figure 1c, this layer 5 is coated with a mask in which were formed openings forming a two-dimensional network which is, according to the lines, the same not as for Figure 1a, but offset laterally by half -not. Using a solution of H 2 S0 4 -H 2 0 2 -H 2 0 as mentioned above, openings 6 are stripped. Layer 5 then remains a two-dimensional network of zones of location spaced from each other and comprising, according to the rows and columns, an upper part 7 and a lower part 8.

Selon la figure 1d, on réalise par épitaxie une couche active 10 en Ga0,65Al0.5As de type p d'une surépaisseur e2 de 4 à 8 microns environ (dopage de 1 à 4· 1018cm-3) puis une couche d'injection 12 en Ga0.3Al0.7As de type n d'épaisseur e3 égale à 4 à 5 microns environ, ceci convenant pour une émission dans le rouge (environ 650 nm).According to Figure 1d, an active layer is carried out by epitaxy 10 Ga 0, 65 Al 0.5 As p-type a thickness e 2 of 4 8 microns approximately (doping of 1 to 4 · 10 18 cm -3) and an injection layer 12 in Ga 0.3 Al 0.7 As of type n of thickness e 3 equal to approximately 4 to 5 microns, this suitable for emission in the red (approximately 650 nm).

Selon la figure 1e, on réalise un bombardement de protons à travers un masque en polyimide ou bien encore métallique par exemple en or, de manière à rendre semi-isolantes des zones 14 disposées en lignes et en colonnes. Ces zones 14 réalisent la séparation entre les diodes individuelles de la matrice. Elles s'étendent depuis la surface de la couche 12 jusqu'au niveau des parties supérieures 7 des zones de localisation.According to FIG. 1e, a bombardment of protons is carried out through a polyimide or even metallic mask, for example made of gold, so as to make zones 14 arranged in rows and columns semi-insulating. These zones 14 carry out the separation between the individual diodes of the matrix. They extend from the surface of the layer 12 to the level of the upper parts 7 of the location zones.

La connexion ligne par ligne des diodes étant réalisée par les régions semi-conductrices fortement dopées 4, on réalise des métallisations 19, 20 destinées à connecter les diodes colonne par colonne. La partie active du contact au niveau de chaque diode est constituée latéralement par la région 19' et transversalement par la région 20 (voir fig. 2) ces repères désignant des régions de métallisation en surplomb des zones de localisation 9. Ces régions actives 19' et 20 s'étendent intérieurement parallèlement à la direction des lignes et des colonnes jusqu'à l'aplomb du bord 9' des zones de localisation 9.The line-by-line connection of the diodes being carried out by the heavily doped semiconductor regions 4, metallizations 19, 20 intended to connect the diodes column by column are produced. The active part of the contact at the level of each diode is formed laterally by the region 19 'and transversely by the region 20 (see fig. 2) these marks designating metallization regions overhanging localization zones 9. These active regions 19' and 20 extend internally parallel to the direction of the rows and columns to plumb with the edge 9 ′ of the location zones 9.

A la figure 2 constituant un mode de réalisation préféré on a représenté en pointillé le contour des zones semi-isolantes 14. A chaque pas, les bandes longitudinales présentent des bandes transversales 19 situées sur les zones semi-isolantes 14 disposées selon les lignes et qui se prolongent latéralement de part et d'autre par lesdites régions actives 19', de manière à réaliser ladite connexion des diodes colonne par colonne.In FIG. 2 constituting a preferred embodiment, the outline of the semi-insulating zones 14 is shown in dotted lines. At each step, the longitudinal bands have transverse bands 19 situated on the semi-insulating zones 14 arranged along the lines and which extend laterally on either side by said active regions 19 ′, so as to make said connection of the diodes column by column.

La structure ainsi obtenu se définit alors sur le plan fonctionnel de la manière suivante.The structure thus obtained is then defined on the functional level in the following manner.

Comme mentionné ci-dessus, les régions semi-conductrices fortement dopées 4 interconnectent les zones actives 10, 11 des diodes ligne par ligne sur la face inférieure de la matrice alors que les métallisations 19, 20 interconnectent les zones d'injection de celles-ci colonne par colonne sur la face supérieure ou face d'émission de la matrice, la prise de contact s'effectuant pour chaque diode dans les régions actives 19' et 20 entourant une ouverture 21 à l'aplomb des ouvertures 6 et de même dimensions (L, parallèlement aux colonnes et L2 parallèlement aux lignes). Les métallisations 19, 20 sont de ce fait situées en dehors de la zone active d'émission lumineuse de chaque diode, laquelle est délimitée par les zones de localisation 7, 9. Dans la direction des colonnes, les zones semi-isolantes 14 permettent d'isoler électriquement les unes des autres les métallisations reliant les diodes colonne par colonne.As mentioned above, the heavily doped semiconductor regions 4 interconnect the active zones 10, 11 of the diodes line by line on the underside of the matrix while the metallizations 19, 20 interconnect the injection zones thereof column by column on the upper face or emission face of the matrix, contact is made for each diode in the active regions 19 ′ and 20 surrounding an opening 21 directly above the openings 6 and of the same dimensions ( L, parallel to the columns and L 2 parallel to the lines). The metallizations 19, 20 are therefore located outside the active light emission zone of each diode, which is delimited by the localization zones 7, 9. In the direction of the columns, the semi-insulating zones 14 allow 'electrically isolate from each other the metallizations connecting the diodes column by column.

En ce qui concerne les caractéristiques dimensionnelles de la matrice, l'épaisseur eo de la couche 2 dépend (toutes choses égales par ailleurs) de la résistance série admissible. La largeur 1, des zones 8 est de préférence aussi réduite que possible, d'une part parce qu'elles ne remplissent qu'une fonction d'isolement électrique entre les régions 4 adjacentes (diode en inverse) et d'autre part parce que la couche de localisation 7 n'ayant pas besoin d'avoir une épaisseur supérieure à quelques microns, il ne se produit lors de l'épitaxie qu'une compensation imparfaite du gradin produit par les ouvertures 3, se traduisant par des inégalités de niveau à ta surface de la couche 5 qu'il est préférable de ne pas trop accentuer. On notera que ces inégalités de niveau sont sans influence sur le fonctionnement car intervenant à des endroits où les couches ultérieurement déposées sont rendues par la suite semi-isolantes.With regard to the dimensional characteristics of the matrix, the thickness e o of the layer 2 depends (all other things being equal) on the admissible series resistance. The width 1 of the zones 8 is preferably as small as possible, on the one hand because they only perform an electrical isolation function between the adjacent regions 4 (diode in reverse) and on the other hand because since the localization layer 7 does not need to have a thickness greater than a few microns, it only occurs during epitaxy that an imperfect compensation of the gra din produced by the openings 3, resulting in unevenness in the surface of the layer 5 which it is preferable not to accentuate too much. It will be noted that these level inequalities have no influence on the operation since they occur at places where the layers subsequently deposited are subsequently made semi-insulating.

La surépaisseur e2 de la couche 10 et l'épaisseur e3 de la couche 12 ainsi que le dopage de celles-ci sont choisis de manière classique. La largeur l2 des zones semi-isolantes 14 situées dans la direction des lignes est choisie de manière à assurer un bon isolement électrique entre les diodes, et leur largeur 13 dans la direction des colonnes pour qu'une isolation satisfaisante entre les métallisations puisse être obtenue. De même la largeur 14 et 15 des régions actives respectivement 19' et 20 des métallisations doit être suffisante pour une bonne prise de contact ; ce critère est aisé à satisfaire sans augmentation notable de l'écart entre les diodes étant donné que le contact a lieu sur tout le pourtour.The extra thickness e 2 of the layer 10 and the thickness e 3 of the layer 12 as well as the doping of these are chosen in a conventional manner. The width l 2 of the semi-insulating zones 14 located in the direction of the lines is chosen so as to ensure good electrical insulation between the diodes, and their width 1 3 in the direction of the columns so that satisfactory insulation between the metallizations can be obtained. Similarly, the width 1 4 and 1 5 of the active regions 19 ′ and 20 respectively of the metallizations must be sufficient for good contact; this criterion is easy to satisfy without a significant increase in the difference between the diodes since the contact takes place around the entire periphery.

En ce qui concerne les prises de contact, celles-ci sont obtenues à la face supérieure sur des plages 23 situées en bout de colonne à l'extrémité des métallisations 19, 20. En ce qui concerne les régions conductrices 4, la prise de contact est avantageusement obtenue à l'extrémité de chaque ligne à travers des ouvertures ménagées de manière connue en soi à partir d'une des faces de la matrice.As regards the contact points, these are obtained on the upper face on pads 23 situated at the end of the column at the end of the metallizations 19, 20. With regard to the conductive regions 4, the contact point is advantageously obtained at the end of each line through openings formed in a manner known per se from one of the faces of the matrix.

A titre d'exemple, et pour un pas du réseau de diodes de 50 X 100 microns au pas de 190 microns parallèlement aux lignes, et de 150 microns selon les colonnes ; avec L1 = 50 µ, et L2 = 100 w on pourra prendre l1, = 30 µ, 12 = 13 = 30 µ, l4 = 35 µ, et 15 = 30 p., la distance d séparant les métallisations des colonnes adjacentes étant alors égale à 13 soit 30 µ.For example, and for a pitch of the diode network of 50 X 100 microns with a pitch of 190 microns parallel to the lines, and 150 microns along the columns; with L 1 = 50 µ, and L2 = 100 w we can take l 1 , = 30 µ, 1 2 = 1 3 = 30 µ, l4 = 35 µ, and 1 5 = 30 p., the distance d separating the metallizations adjacent columns then being equal to 1 3 or 30 μ.

Selon la variante de la figure 3, chaque métallisation comporte une seule bande longitudinale 20 située sur les zones semi-isolantes 14 disposées selon les colonnes. A chaque pas, la bande 20 est prolongée par une bande transversale 22 de manière à entourer chaque diode individuelle sur trois côtés d'une ouverture 21' située à l'aplomb de l'ouverture 6 correspondante et de même dimensions que celle-ci. On remarquera que dans ce mode de réalisation, on n'a pas représenté de zones semi-isolantes 14 disposées selon les lignes. Une telle suppression pourrait être également effectuée dans le cas des figures précédentes. En effet, la seule fonction des zones semi-isolantes 14 disposées selon les lignes est d'apporter une isolation électrique optimale entre les diodes adjacentes. En fait, cette isolation n'est pas une nécessité absolue, et ce pour deux raisons. D'une part, la couche de localisation 7 d'une diode donnée dirige perpendiculairement au plan du substrat les lignes de courant entre la région 4 formant contact de ligne et la métallisation 19, 20 formant contact de colonne de la diode considérée, et d'autre part le chemin de fuite entre le contact de ligne 4 et une métallisation adjacentes est assez long du fait que le pas des diodes de la matrice est beaucoup plus important que la surépaisseur e2 de la couche 10 et l'épaisseur e3 de la couche 12 à travers lesquelles la conduction normale s'effectue. De ce fait, l'émission des zones semi-isolantes 14 disposées selon les lignes ne peut entraîner au pire qu'un faible éclairement parasite de deux diodes adjacentes à une diode normalement éclairée.According to the variant of FIG. 3, each metallization comprises a single longitudinal strip 20 situated on the semi-insulating zones 14 arranged according to the columns. At each step, the strip 20 is extended by a transverse strip 22 so as to surround each individual diode on three sides with an opening 21 'situated directly above the corresponding opening 6 and of the same dimensions as the latter. It will be noted that in this embodiment, semi-insulating zones 14 have not been shown arranged along the lines. Such a deletion could also be carried out in the case of the preceding figures. Indeed, the only function of the semi-insulating zones 14 arranged along the lines is to provide optimal electrical insulation between the adjacent diodes. In fact, this isolation is not an absolute necessity, for two reasons. On the one hand, the localization layer 7 of a given diode directs the current lines between the region 4 forming line contact and the metallization 19, 20 forming the column contact of the diode considered perpendicular to the plane of the substrate, and d on the other hand the leakage path between the line contact 4 and an adjacent metallization is quite long because the pitch of the diodes of the matrix is much greater than the excess thickness e 2 of the layer 10 and the thickness e 3 of layer 12 through which normal conduction takes place. As a result, the emission of the semi-insulating zones 14 arranged along the lines can at worst cause only a weak parasitic illumination of two diodes adjacent to a normally lit diode.

L'invention ne se limite pas aux modes de réalisation décrits et représentés. Ainsi, on pourra réaliser des couches actives et/ou des couches d'injection de composition binaire, par exemple en AsGa, ainsi qu'il est d'ailleurs connu.The invention is not limited to the embodiments described and shown. Thus, it will be possible to produce active layers and / or injection layers of binary composition, for example in AsGa, as is moreover known.

Claims (10)

1. A matrix of light-emitting diodes comprising at least one active layer (10) of a III-V material of a first conductivity type and a superficial injection layer (12) of a III-V material of the second opposite conductivity type and semi-insulating zones (14) arranged at least in columns and extending over the thickness of the injection layer (12) and of the active layer (10) so that they separate at least in part in the said layers the individual diodes from each other and comprise at least a part of the conducting contacts, characterized in that each semiinsulating zone (14) extends from the surface of the injection layer (12) to a localization zone (7, 8) of III-V material of a binary composition and of the second conductivity type, the localization zones each having in crosssection an upper part (7) and a lower part (8), the said upper parts (7) defining a bidimensional lattice of cells filled by prolonged parts (11) of the active layer (10), and said lower parts (8) being spaced apart by semiconducting electrical contact regions (4) at a high doping level of the first conductivity type arranged parallel to lines so that they interconnect the diodes linewise at the level of said prolonged parts (11) and in that it comprises on the injection layer (12) electrical contact metallizations (19, 20) having for each diode contact regions (19) extending internally substantially above the upper parts (7) of the localization zones and interconnected columnwise, the interconnection columns being electrically insulated from each other by the said semi-insulating zones (16) arranged in columns.
2. A matrix as claimed in Claim 1, characterized in that the active layer (10) is of a ternary composition.
3. A matrix as claimed in any one of Claims 1 or 2, characterized in that the injection layer (12) is of a ternary composition.
4. A matrix as claimed in any one of Claims 1 to 3, characterized in that it comprises a substrate layer (1) of a binary III-V composition.
5. A matrix as claimed in any one of the preceding Claims, characterized in that the binary composition is GaAs and the ternary composition is GaAIAs.
6. A matrix as claimed in any one of the preceding Claims, characterized in that the semi- insulating zones (14) also extend in lines so that they provide an electrical insulation between the adjacent diodes.
7. A method of manufacturing a matrix of lightemitting diodes as claimed in any one of the preceding Claims, in which an injection layer (12) and an active layer (10) of the Ill-V type are formed by hetero-epitaxy on a substrate (1) and in which the individual diodes are separated at least in part by bombarding regions defined so that at least columns of semi-insulating zones are formed over the thickness of the injection layer and of the active layer, characterized in that it comprises the following steps :
-epitaxially depositing on said substrate a first III-V semiconductor layer (4) of a highly doped binary composition of a first conductivity type (p) ;
-etching in said first III-V layer a first group of lines of openings (3) arranged parallel to the lines according to a given pitch, the subsisting parts of the first layer forming semiconducting electrical contact regions (4) interconnecting the diodes linewise ;
-epitaxially depositing a second III-V layer (5) of a binary composition of the second conductivity type (n) ;
-in order to obtain a localization layer, etching in said second III-V layer a second group of openings (6) forming a bidimensional lattice offset along the lines by half a pitch with respect to those of the first group (3), the said openings (6) of the second layer being formed in an upper part (7) of the localization layer which covers in part the said semiconducting electrical contact regions ;
-epitaxially depositing successively said active layer (10) of a first conductivity type and said injection layer (12) of a second conductivity type ;
-carrying out the said bombardment ;
-forming electrical contact metallizations (19, 20) on the injection layer (12), which comprise for each diode contact regions (19) extending internally parallel to the lines substantially above the upper parts (7) of the localization layer and interconnected columnwise, the interconnection columns thus constituted being electrically insulated from each other by the semi-insulating zones arranged in columns.
8. A method as claimed in Claim 7, characterized in that the bombardment step is such that also lines of semi-insulating regions (14) are formed so that an optimum electrical insulation is obtained between the adjacent diodes.
9. A method as claimed in any one of Claims 7 or 8, characterized in that the substrate (1) is a layer of a binary III-V composition which is intrinsic or of the second conductivity type (n).
10. A method as claimed in any one of Claims 7 to 9, characterized in that the active layer (10) and the injection layer (12) have compositions chosen from GaAs and GaAIAs.
EP85201836A 1984-11-23 1985-11-11 Light-emitting diodes array and method for its production Expired EP0182430B1 (en)

Applications Claiming Priority (2)

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FR8417894 1984-11-23
FR8417894A FR2573897B1 (en) 1984-11-23 1984-11-23 LIGHT EMITTING DIODE MATRIX AND MANUFACTURING METHOD THEREOF

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EP0182430B1 true EP0182430B1 (en) 1989-02-01

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CA1279394C (en) * 1985-07-26 1991-01-22 Naoki Chinone Multiple quantum well type semiconductor laser
JPH02127053A (en) * 1988-11-07 1990-05-15 Mitsubishi Electric Corp Led array
US5094970A (en) * 1988-11-07 1992-03-10 Mitsubishi Denki Kabushiki Kaisha Method of making a light emitting diode array
US5449926A (en) * 1994-05-09 1995-09-12 Motorola, Inc. High density LED arrays with semiconductor interconnects
SE509809C2 (en) * 1995-11-03 1999-03-08 Mitel Semiconductor Ab LED with divided light emitting area
JP4273237B2 (en) * 2005-01-05 2009-06-03 Ｄｏｗａホールディングス株式会社 Infrared light emitting diode and manufacturing method thereof

Family Cites Families (11)

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FR2079612A5 (en) * 1970-02-06 1971-11-12 Radiotechnique Compelec
DE2235865A1 (en) * 1972-07-21 1974-01-31 Licentia Gmbh Multi-element semiconductor device - having implanted semi-insulating zones separating (photodiode) elements
US3996492A (en) * 1975-05-28 1976-12-07 International Business Machines Corporation Two-dimensional integrated injection laser array
US4198251A (en) * 1975-09-18 1980-04-15 U.S. Philips Corporation Method of making polychromatic monolithic electroluminescent assembly utilizing epitaxial deposition of graded layers
GB1532286A (en) * 1976-10-07 1978-11-15 Elliott Bros Manufacture of electro-luminescent display devices
JPS53117174U (en) * 1977-02-15 1978-09-18
FR2413792A1 (en) * 1977-12-30 1979-07-27 Radiotechnique Compelec Monolithic semiconductor contg. matrix of electroluminescent elements - esp, using doped gallium arsenide substrate covered by epitaxial layers of doped gallium arsenide phosphide
EP0011418A1 (en) * 1978-11-20 1980-05-28 THE GENERAL ELECTRIC COMPANY, p.l.c. Manufacture of electroluminescent display devices
GB2035689B (en) * 1978-11-20 1983-04-13 Gen Electric Monolithic led array
US4309670A (en) * 1979-09-13 1982-01-05 Xerox Corporation Transverse light emitting electroluminescent devices
FR2491714A1 (en) * 1980-10-06 1982-04-09 Radiotechnique Compelec SEMICONDUCTOR DEVICE WITH LOCALIZED ELECTROLUMINESCENT DIODES AND METHOD OF MANUFACTURING THE SAME

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US4757357A (en) 1988-07-12
FR2573897B1 (en) 1987-03-20
FR2573897A1 (en) 1986-05-30
JPS61128581A (en) 1986-06-16
JPH0732267B2 (en) 1995-04-10
EP0182430A1 (en) 1986-05-28
DE3568109D1 (en) 1989-03-09

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