EP0122594A3 - Line circuit with echo compensation - Google Patents
Line circuit with echo compensation Download PDFInfo
- Publication number
- EP0122594A3 EP0122594A3 EP84104040A EP84104040A EP0122594A3 EP 0122594 A3 EP0122594 A3 EP 0122594A3 EP 84104040 A EP84104040 A EP 84104040A EP 84104040 A EP84104040 A EP 84104040A EP 0122594 A3 EP0122594 A3 EP 0122594A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- digital
- signals
- path
- line circuit
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
- H04B3/23—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
- H04B3/238—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers using initial training sequence
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Bidirectional Digital Transmission (AREA)
Abstract
A line circuit (1) interposed between two unidirectional
digital lines (3, 4) and a single bidirectional analog line (2) has
a first path (7) in which incoming digital signals are processed
and converted into analog signals, and a second path (14) in
which outgoing analog signals are converted into digital
signals. The two paths (7, 14) are connected to the bidirec
tional analog line (2) by a common junction (10, 11). A digital
hybrid (17) is interposed between the first and second paths
(7, 14) and provides compensation for the echo response
effects. The digital hybrid (17) is supplied with signals from
the first path (7) and with respective correction coefficients.
Resultant digital correction signals are combined with the
digital signals propagating in the second path (14). To establ
ish the values of the correction coefficients, a training pattern
is sent into the line circuit (1), and the responses to the training
pattern with the digital hybrid (17) out of operation as
obtained at the digital output of the line circuit (1) are then
used as the correction coefficients.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48598783A | 1983-04-18 | 1983-04-18 | |
US485987 | 1995-06-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0122594A2 EP0122594A2 (en) | 1984-10-24 |
EP0122594A3 true EP0122594A3 (en) | 1986-09-10 |
Family
ID=23930175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP84104040A Withdrawn EP0122594A3 (en) | 1983-04-18 | 1984-04-11 | Line circuit with echo compensation |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0122594A3 (en) |
JP (1) | JPS6035841A (en) |
AU (1) | AU2680084A (en) |
BE (1) | BE899447R (en) |
ES (1) | ES8507745A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6053336A (en) * | 1983-09-02 | 1985-03-27 | Nec Corp | Echo canceller |
JPH0720070B2 (en) * | 1985-08-14 | 1995-03-06 | 株式会社日立製作所 | PCM code decoder having digital balancing circuit |
US4811342A (en) * | 1985-11-12 | 1989-03-07 | Racal Data Communications Inc. | High speed analog echo canceller |
BE905760A (en) * | 1986-11-16 | 1987-05-18 | Electronique Et Telecomm Bell | ADJUSTABLE ECHO COMPENSATOR. |
NO180137C (en) * | 1986-11-17 | 1997-02-19 | Alcatel Nv | Echo canceling construction |
GB8719307D0 (en) * | 1987-08-14 | 1987-09-23 | Gen Electric Co Plc | Echo canceller |
ES2038887B1 (en) * | 1991-04-18 | 1995-05-01 | Aplicaciones Electronicas Quas | DIGITAL HYBRID FOR MULTI-CONFERENCE. |
EP0953234B1 (en) * | 1997-01-20 | 2001-11-21 | Infineon Technologies AG | Circuit for two-wire / four-wire conversion |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4268727A (en) * | 1979-03-14 | 1981-05-19 | International Telephone And Telegraph Corporation | Adaptive digital echo cancellation circuit |
GB2064902A (en) * | 1979-11-28 | 1981-06-17 | Int Standard Electric Corp | Telephone line circuit |
WO1981003728A1 (en) * | 1980-06-18 | 1981-12-24 | Advanced Micro Devices Inc | Subscriber line audio processing circuit apparatus |
EP0048979A2 (en) * | 1980-09-26 | 1982-04-07 | Nec Corporation | Echo canceller for a long-distance telephone network |
EP0065796A1 (en) * | 1981-05-07 | 1982-12-01 | Koninklijke Philips Electronics N.V. | Arrangement for cancelling echo signals |
-
1984
- 1984-04-11 EP EP84104040A patent/EP0122594A3/en not_active Withdrawn
- 1984-04-13 AU AU26800/84A patent/AU2680084A/en not_active Abandoned
- 1984-04-18 BE BE2/60393A patent/BE899447R/en not_active IP Right Cessation
- 1984-04-18 ES ES531763A patent/ES8507745A1/en not_active Expired
- 1984-04-18 JP JP7829784A patent/JPS6035841A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4268727A (en) * | 1979-03-14 | 1981-05-19 | International Telephone And Telegraph Corporation | Adaptive digital echo cancellation circuit |
GB2064902A (en) * | 1979-11-28 | 1981-06-17 | Int Standard Electric Corp | Telephone line circuit |
WO1981003728A1 (en) * | 1980-06-18 | 1981-12-24 | Advanced Micro Devices Inc | Subscriber line audio processing circuit apparatus |
EP0048979A2 (en) * | 1980-09-26 | 1982-04-07 | Nec Corporation | Echo canceller for a long-distance telephone network |
EP0065796A1 (en) * | 1981-05-07 | 1982-12-01 | Koninklijke Philips Electronics N.V. | Arrangement for cancelling echo signals |
Non-Patent Citations (1)
Title |
---|
IEEE TRANSACTIONS ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, vol. ASSP-22, no. 4, August 1974, pages 231-235, IEEE, New York, US; M.G. BELLANGER et al.: "Interpolation, extrapolation, and reduction of computation speed in digital filters" * |
Also Published As
Publication number | Publication date |
---|---|
BE899447R (en) | 1984-10-18 |
AU2680084A (en) | 1984-10-25 |
ES531763A0 (en) | 1985-08-16 |
ES8507745A1 (en) | 1985-08-16 |
JPS6035841A (en) | 1985-02-23 |
EP0122594A2 (en) | 1984-10-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IE801478L (en) | Subscriber set | |
EP0122594A3 (en) | Line circuit with echo compensation | |
US4731834A (en) | Adaptive filter including signal path compensation | |
EP0135066A3 (en) | Transfer device for digital signals | |
ES8704057A1 (en) | A method of reducing echo in a digital switching system and a digital hybrid therefor | |
GB1391434A (en) | Television standards conversion | |
DE3570030D1 (en) | INTERMEDIATE FREQUENCY TRANSVERSAL EQUALIZER | |
EP0132933A3 (en) | Adaptive line hybrids | |
JPS54117612A (en) | Mike remote control-system transceiver | |
JPS5779787A (en) | Spatial switch constituting system for digital exchanger | |
EP0177239A3 (en) | Adaptive filter including signal path compensation | |
SE9003661L (en) | PROCEDURE AND DEVICE TO REDUCE THE NECESSARY SIZE OF A DIGITAL FILTER IN CONNECTION WITH ECO-ELIMINATION IN A SUBSCRIPTION LINE | |
JPS5592028A (en) | Signal switching circuit | |
JPS642100A (en) | Digital distortion adding device | |
JPS55133121A (en) | Conversion circuit of two to four lines | |
JPS54109709A (en) | Verification system | |
JPS5728436A (en) | Line coupler for power line carrier communication device | |
JPS54130819A (en) | Two-way variable gain amplifier | |
JPS5531359A (en) | Hybrid circuit | |
JPS5493947A (en) | Resistance hybrid circuit | |
JPS5640318A (en) | Transversal filter | |
JPS54100211A (en) | Active 2-4 line converter circuit | |
JPS5759176A (en) | Surge receiving system in fault locator of transmission wire | |
JPS55133142A (en) | Estimation system for gain of communication line | |
JPS55134571A (en) | Subscriber's circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Designated state(s): AT DE FR GB NL SE |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT DE FR GB NL SE |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19870311 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: GINGELL, MICHAEL JOHN |