Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5385—Assembly of a plurality of insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates generally to the testing of semiconductor devices, and more particularly to a contact tape for electrically exercising and burning in multiple semiconductors concurrently before packaging.
• Semiconductor devices have several well known advantages including high reliability, long life, low power consumption, etc; however, an accompanying disadvantage involves the fact that a substantial percentage of such devices are defective when manufactured. Devices with marginal defects frequently test good under initial screening only to fail later under further testing or shortly after being put into service. It is therefore desirable to test semiconductor devices under conditions of stress as soon as possible after manufacture so that the defective ones can be identified and discarded. This is typically done by means of "burn-in" testing whereby the circuits in the device are exercised and cycled through their operational states under conditions of elevated voltage and temperature for an extended period of time.
• semiconductor devices have typically been burned-in as follows. After packaging, groups of semiconductors are connected to sockets on conventional circuit boards which are then placed in ovens. The semiconductors are then exercised under electrical and elevated stress conditions for several hours to cause failure of any marginal circuits therein. After burn-in, the semiconductor devices are again functionally tested to identify and discard devices caused to fail from burn-in stress conditions. Those semiconductors which pass this test are delivered to customers.
• This approach involves several drawbacks. A significant portion of the cost of a finished semiconductor is attributable to the labor, materials, equipment and specialized techniques required for packaging, as well as the cost of the package itself. When considering the volume and manufacturing rejects involved in mass producing semiconductors, it will be appreciated that this represents a substantial expense. Further, a considerable amount of space is required to accommodate the number of ovens, circuit boards, testers and other equipment necessary for large scale burn-in and testing of semiconductors after packaging.
• the present invention comprises a burn-in tape which overcomes the foregoing and other disadvantages associated with the prior art.
• a burn-in contact tape adapted for use with a device tape along which a number of semiconductors are mounted.
• the contact tape comprises an elongate, nonconductive backing with a layer of metallization thereon defining a plurality of separate conductors on one side of the tape.
• groups of pads at spaced intervals therealong adapted to mate with corresponding groups of pads on the device tape which in turn are connected to the semiconductor.
• the contact pads of each group are connected to the corresponding conductors on the contact tape so that multiple semiconductors simultaneously can be exercised and burned-in when the device tape and contact tape are engaged together.
• FIGURE 1 is a partially cutaway enlarged top view of a device tape overlaid with a burn-in contact tape incorporating the invention.
• FIGURE 2 is a sectional view taken along lines 2-2 of FIGURE 1 in the direction of the arrows.
• FIGURE 1 there is shown a burn-in contact tape 10 laid over a device tape 12 along which a number of semiconductor chips 14 are attached.
• Each chip 14 includes a plurality of bonding or contact pads 16-50 through which electrical connection is made to the circuitry within the chip.
• Chips 14 can comprise memory products, microprocessors or virtually any other type of semiconductor.
• device tape 12 provides the mounting and electrical connections to chips 14 while contact tape 10 provides the interface connections for appropriate control and power signals such that the entire row of unpackaged chips can be simultaneously burned-in while attached to the device tape.
• Contact tape 10 comprises a continuous strip of insulating, dielectric backing 52 together with a single layer of metallization which has been etched to define a plurality of separate conductor lines.
• Tape 10 includes continuous power bus lines 54 and 56 which are commonly known as the supply voltage bus and ground lines.
• pairs of laterally spaced apart openings 58 each of which are separated by a bridge portion 60 of the tape.
• Each chip 14 is positioned within a corresponding pair of openings 58 and across the bridge portion 60 on the side of tape 12 which is opposite to the layer of metallization.
• the metallization pattern on device tape 12 defines a plurality of conductive leads which extend into each pair of openings 58. One lead is provided for each of the contact pads 16-50 on a chip 14. Leads 62-68 are connected to pads 16-32, respectively, while leads 80-96
• OMFI are likewise connected to pads 34-50 of each chip 14.
• the contact pad 24 of each chip 14 is connected by lead 70 to power line 54.
• the contact pad 42 of each chip 14 is connected by lead 88 to line 56 on the other side of tape 12.
• Pads 24 and 42 and leads 70 and 88 thus represent the path by which each chip 14 is connected between a suitable supply voltage and ground as repre ⁇ sented by lines 54 and 56.
• the remaining signal conducting leads 62-68, 72-78, 80-86 and 90-96 extend respectively to corresponding sets of test pads 62a-68a, 72a-78a, 80a-86a and 90a-96a provided on tape 12 for each chip 14.
• Device tape 12 further includes a plurality of sprocket holes 98 uniformly spaced along the longitudinal sides thereof by which the tape can be accurately advanced into position for bonding leads 62-96 to each chip 14, and for aligning the device relative to contact tape 10.
• leads 62-96 are cut along lines 100 and 102 after connection to each chip 14 to disconnect the chip from tape 12 and thereby provide the chip with leads for subsequent connection to the external, relatively heavier leads of a protective chip package.
• tape bonding procedures heretofore have typically been used only as a means for providing chips 14 with such leads, the provision of test pads 62a-68a, 72a-78a, 80a-86a and 90a-96a on the device tape enables individual testing of the chips.
• the present invention represents a further advancement in that contact tape 10 enables simultaneous exercise and complete dynamic burn-in of all the chips 14 on tape 12. * ⁇
• the contact tape 10 comprises a layer of insulating backing 104 of dielectric material together with a layer of metallization on each side thereof which has been etched to define a plurality of conductor lines and contact pads adapted to mate with those device tape 12.
• contact tape 10 includes continuous power bus lines 106 and 108 extending along opposite sides of the tape. Conductor lines 106 and 108 engage lines 54 and 56, respectively, of device tape 12 when the two tapes are clamped or otherwise secured together. As illustrated, the power ' lines 106 and 108 extend continuously along opposite edges of backing 104 on both sides of tape 10; however, it will be understood that the power lines need only be provided on that side of the tape which is to contact tape 12.
• Tape 10 further includes a plurality of signal conductor lines 110-140 corresponding to lines 62-68; 72-78, 80-88 and 90-96 of tape 12. Sixteen conductor lines 110-140 are thus provided on tape 10, it being understood that the exact number thereof depends upon the particular semiconductor chips 14. Conductor lines 110-140 are located on that side of dielectric backing 104 which faces away.from device tape 12.
• a plurality of sprocket holes 142 are provided at uniform intervals along the longitudinal sides " of contact tape 10 for advancement and alignment purposes.
• a plurality of sets of corresponding contact pads 110a-140a are provided on the underside of backing 104.
• Contact pads 110a-140a comprise small projections of metallization chemically or mechanically produced which extend through small holes or vias punched or chemically formed in backing 104 to connection with lines 110-140, respectively.
• the contact pads 110a-140a are arranged to engage test pads 62a-68a, 72a-78a, 80a-86a and 90a-96a, respectively, when tapes 10 and 12 are clamped or otherwise secured together ' so that an entire strip of semiconductor chips 14 can be simultaneously burned-in.
• Contact tape 10 and device tape 12 are utilized as follows. After chips 14 have been bonded to their corresponding sets of leads 62-96 on device tape 12, the tapes are aligned by means of sprocket holes 98 and 142 before being resiliently clamped together in contacting engagement. The tapes 10 and 12 along with the chips 14 thereon are then placed in a heated medium simulating stress conditions. For example, tapes 10 and 12 and chips 14 can be clamped together in a jig and immersed in liquid perfluorocarbon at a temperature of about 120°C. Suitable connectors and drivers (not shown) are coupled to the ends of tape 10 and 12. Power is conducted to the row of chips 14 by way of lines 104 and 106 of tape 10 and lines 54 and 56 of tape 12.
• Controlled electronic signals suitable for burning in chips 14 are transmitted thereto via lines 110-140 of contact tape 10 and leads 62-96 of device tape 12 together with their corresponding test and contact pads. All of the chips 14 connected to the device tape 12 can thus be simultaneously exercised and burned-in in this fashion. Those chips 14 which fail the burn-in test are discarded after functional testing.
• the present invention comprises a complete dynamic burn-in contact tape having several advantages over the prior art.
• the tape herein permits concurrent testing of all of the semiconductors connected to a device tape, thereby avoiding the waste and expense associated with such testing after packaging. Besides these efficiencies, the tape herein requires less space to burn-in a relatively larger number of chips. Other advantages will be evident to those skilled in the art.

Landscapes

• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Testing Of Individual Semiconductor Devices (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=22154640

Family Applications (1)

Country Status (2)

Families Citing this family (4)

Family Cites Families (10)

• 1980
  • 1980-11-07 EP EP19810901371 patent/EP0064496A1/de not_active Withdrawn
  • 1980-11-07 WO PCT/US1980/001496 patent/WO1982001803A1/en unknown

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events