EP0000743A1 - Method for fabricating tantalum contacts on a N-type conducting silicon semiconductor substrate - Google Patents

Method for fabricating tantalum contacts on a N-type conducting silicon semiconductor substrate Download PDF

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Publication number
EP0000743A1
EP0000743A1 EP7878100525A EP78100525A EP0000743A1 EP 0000743 A1 EP0000743 A1 EP 0000743A1 EP 7878100525 A EP7878100525 A EP 7878100525A EP 78100525 A EP78100525 A EP 78100525A EP 0000743 A1 EP0000743 A1 EP 0000743A1
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European Patent Office
Prior art keywords
tantalum
layer
substrate
aluminum
deposited
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EP7878100525A
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German (de)
French (fr)
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EP0000743B1 (en
Inventor
Hormazdyar Minocher Dalal
Majid Ghafghaichi
Lucian Alexander Kasprzak
Hans Wimpfheimer
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International Business Machines Corp
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International Business Machines Corp
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Definitions

  • the invention relates to a method of tantalum contacts in the production of metallizations in the contacting of silicon semiconductors for the representation of ohmic contacts and Schottky barrier layer contacts.
  • the literature contains a large number of other metallurgical systems that perform one or more functions of metallic contacts.
  • the most successful system of this type is a titanium-tungsten alloy, which has been widely used in industry as a barrier between aluminum and silicon.
  • DTL diode transistor logic
  • the potential threshold of the input diodes is approximately 0.5 eV.
  • the DTL circuit known under the short designation C 3 L is particularly useful when Schottk diodes, which operate as an AND gate on the input side, have this potential threshold.
  • the C 3 L circuit is, for example, in a publication by AW Peltier entitled "Advances in Solid-State Logic - A New Approach to Bipolar LSI: C 3 L" in the 1975 IEEE International Solid-State Circuits Conference, Digest of Technical Papers , Pages 168-169. Peltier states that either titanium, tungsten or titanium-tungsten alloys meet this requirement.
  • the object of the invention is therefore to provide semiconductor circuits which have improved contacts and connecting lines, which in particular consist of an improved single metallurgical system which is suitable both for ohmic contacts and for Schottky blocking contacts with high and low potential thresholds.
  • the process used for the precipitation of tantalum layers should preferably be suitable for the formation of Schottky junction contacts with a precisely controlled potential threshold, while at the same time ensuring compatibility with the connecting lines made of aluminum.
  • This object on which the invention is based is achieved by a novel method for depositing tantalum on silicon, as a result of which a diode structure with a low potential threshold can be precisely controlled.
  • tantalum is directly deposited on N-conducting silicon, and a potential threshold of 0.5 eV is achieved.
  • the diode remains exceptionally stable during extensive voltage tests.
  • a tantalum layer deposited in this way is suitable as an ohmic contact when it is applied to the top of a metal-silicon layer formed in N + -conducting silicon and also as a Schottky barrier diode (SBD) with a high potential threshold, if the layer is deposited on top of a metallic silicide layer formed in N-type silicon.
  • SBD Schottky barrier diode
  • chrome layer must be deposited between the tantalum layer and the aluminum layer.
  • the chrome layer is formed by introducing water vapor during the evaporation or sputtering of elemental chromium. The long-term reliability of this metallurgical system is exceptionally good.
  • the part-Fig. 1A shows the part of a semiconductor die which is to contain the Schottky junction diodes constructed according to the invention. It is obvious that normally within the same die Thousands of such diodes and other semiconductor devices, such as transistors, resistors, etc., can be arranged.
  • the substrate of the semiconductor die consists, for example, of P-type silicon, which has a resistivity of 10 ohm-cm.
  • an N - -type layer 3 is attached, preferably having a conductivity ke it from 1 x 10 16 to 8 x 10 16 atoms / cm 3.
  • two buried zones 4 and 6 are easily seen, which are led out via connection zones 5 and 7 to the surface of the substrate.
  • the substrate also contains a P + -conducting sub-isolation zone 2 which, in conjunction with a P + -conductive isolation zone 8, separates the N + -conducting zones from one another.
  • Zones 2, 4 and 6 are advantageously produced by diffusing these zones through openings provided in the layer covering the surface of the substrate.
  • An interference element causing an N line is arsenic or phosphorus
  • a interference element causing a P + conductivity is boron.
  • the mask layer is then removed from the substrate 1 by conventional etching methods, and a layer 3 is grown epitaxially, the zones 2, 4 and 6 penetrating into the layer 3 by diffusion.
  • a mask layer which is normally composed of a silicon dioxide layer 9 and a silicon nitride layer 10, is then formed on the surface of the layer 3, and openings are then produced in this mask layer, through which openings the N + conductivity or P + - Conducting interference elements to form the contact zones 5 and 7 or the isolation zone 8 are diffused.
  • a platinum layer 15 preferably by evaporation or sputtering, applied to a thickness of 40 nm.
  • the silicon dioxide layer 9 lying in the opening 13 prevents the platinum in this opening from coming into contact with the substrate.
  • the semiconductor die is then sintered for about 20 minutes at a temperature of 550 ° C. in a nitrogen atmosphere, as a result of which the platinum reacts with the silicon and forms platinum-silicide layers 15 ′ in the openings 12, 13 and 14.
  • the unreacted platinum, including the platinum layer overlying the silicon dioxide layer 10 is then removed by etching with aqua regia.
  • other metals such as palladium, nickel or hafnium can also be used instead of platinum.
  • the part of the silicon dioxide layer 9 lying in the opening 13 is removed by a wet or dry etching process, whereby this part of the substrate is exposed, which is then to form the anode of a Schottky junction diode with a low potential threshold.
  • the new metallization system is then deposited in openings 11 to 14.
  • the preferred detachment method is described in detail in applicant's U.S. Patent 4,004,044. This method is intended to be abbreviated based on the partial fig. 1D - 1F.
  • Other methods of forming the metallization are wet or reactive ion (plasma) etching methods that are generally available to those skilled in the art.
  • plasma reactive ion
  • polyether sulphone is now applied, which facilitates the detachment process.
  • the use of polyether sulphone, or polysulphone for short, is a modification of the method mentioned in the above-mentioned patent and was described in IBM Technical Disclosure Bulletin, Volume 19, No. 4, September 1976, on page 1226.
  • a layer 22 of an organic polymer is applied over the polysulphone layer 20, such as positive photoresist based on Novalak resin, which is subsequently baked or cured at 210-230 ° C. so that the photoresist is no longer photosensitive .
  • a barrier layer 24 consisting of a methyl siloxane resin is applied over the photoresist layer 22 and then a layer 26 of a radiation-sensitive photoresist.
  • the photoresist layer 26 is then used to create a relief-like pattern corresponding to the openings 11, 12, 13 and 14 in the partial FIG. 1C exposed and developed.
  • the photoresist mask 26 is then used for the selective removal of the layers 20, 22 and 24 underneath to expose the openings 11 ', 12', 13 'and 14' in the part of FIG. 1D used, which the in Fig. 1C corresponding openings shown.
  • the exposed substrate including the platinum-silicide layer 15 is subjected to a pre-cleaning under closely monitored radiation conditions with a mixture of 15: 1 or less of water and hydrofluoric acid etchant. A mixing ratio of 5: 1 is most advantageous.
  • the out Pressure "closely monitored radiation conditions" is intended to mean that no noticeable amount of light with a wavelength shorter than 500 nm may be present during this etching process step.
  • the applicant has tried to clean the surface using chemical etching agents under white light in accordance with customary methods. With this known method, however, it was not possible to achieve such a low potential threshold; rather, a potential threshold of approximately 0.61 eV was reached. The applicant has also attempted to clean the semiconductor surface in situ in a sputtering chamber by sputtering. Although this method resulted in a potential threshold of about 0.5 eV, the ideality factor of 1.15 was too high. In addition, this potential threshold could not be repeated exactly.
  • a tantalum layer 28 is applied over the substrate and the release mask. So that a Schottky junction contact with a low potential threshold can actually be achieved, this precipitation of the tantalum layer must likewise be carried out using a very carefully carried out process.
  • the precipitation is best carried out with an electron beam evaporation source, such as that from Airco-Temescal Corp. is supplied as model FC1800. Similar embodiments of evaporation systems are described by others other manufacturers.
  • the highest pressure in the evaporation chamber during the process is 2.5 x 10 6 TORR, the initial pressure in the chamber being less than 4 x 10-7 TORR.
  • the maximum temperature of the substrate is 200 ° C.
  • the pressure specified here is important for the amount of moisture, hydrocarbons and other gaseous contaminants present in the chamber.
  • the precipitation process which runs at a speed of about 0.2 nm per second, continues until a layer thickness of 60 + 15 nm is reached.
  • the tantalum layer produced under these conditions consists of f body-centered cubic crystals.
  • tantalum can also be applied under high pressure and temperature conditions using high frequency sputtering.
  • DC voltage sputtering is not suitable, since tantalum layers applied with DC voltage sputtering consist of body-centered tetragonal crystals, while high-frequency sputtered tantalum is deposited as body-centered cubic crystals.
  • the chrome layer is preferably deposited to a thickness of 60-100 nm. Water vapor must be introduced into the chamber during this evaporation process.
  • the substrate is kept at a maximum temperature of 160 ° C, with no heat being supplied to the substrate.
  • a small amount of chromium is introduced into the boat and water vapor is introduced into the evaporation chamber, the pressure of which is kept at about 10 -5 TORR.
  • the pure chromium in the boat When heated by an electron beam, the pure chromium in the boat is evaporated and converted to commercially available chromium, which is critical for the formation of the barrier layer.
  • the chromium precipitated with the addition of water vapor has chromium oxide at the grain boundaries.
  • the aluminum is preferably deposited down to a layer thickness of 850-1000 nm. One with one. A small amount of copper-doped aluminum is preferable to pure aluminum.
  • the term aluminum is to be used here in such a way that it is also to be understood as meaning copper-doped aluminum and also copper-doped aluminum silicon. The resulting structure shows part-Fig. 1E.
  • the remaining release structure and the overlying metal layer are quickly lifted off using N-methylpyrrolidone or other suitable solvent so that a metallic pattern remains on the surface of the substrate or oxide layer 10 as shown in part-Fig. 1F shows.
  • this structure is sintered for about 1 hour at 400 ° C and then again for another 2 hours at 450 ° C.
  • This sintering process step is important because it at least reduces the interface charges and films between the silicon substrate and the tantalum, but mostly eliminates them. Although these times and temperatures are the most advantageous, other values can also be determined by normal experiments, which may be just as effective. This sintering is necessary in order to reach the potential threshold of 0.5 eV, even if only tantalum is used as the contact material, i.e. H. would have been used without chrome and aluminum.
  • the anode and cathode of the Schottky junction diode with high potential threshold are indicated by reference numerals 34 and 35 in part-Fig. 1F.
  • the anode and cathode of the Schottky junction diode with low potential threshold are denoted by reference numerals 36 and 37, respectively.
  • the cathodes of both diodes are the ohmic contacts leading to the N + -conducting zones 5 and 7 in layer 3.
  • the anode 34 of the Schottky junction diode with a high potential threshold uses a chromium-tantalum metallization between the platinum-silicide layer 15 and the aluminum layer 32, which acts as a diffusion barrier, while the platinum-silicide layer gives an increased potential threshold compared with the anode 36 of the Schottky junction diode with a low potential threshold, where there is no platinum-silicide layer.
  • zone 36 the tantalum layer directly contacts the N-type silicon substrate 3.
  • the tantalum layer is not required when manufacturing a Schottky junction diode with a high potential threshold.
  • a contact made of aluminum, chrome and platinum silicide is completely satisfactory.
  • the chromium layer 30 is critical in that it, as a barrier layer, prevents an interaction between aluminum and tantalum. It is well known that aluminum reacts in an unacceptable manner with silicon and also penetrates platinum silicide for interaction or reaction with silicon. Contrary to all expectations, tantalum and aluminum react with one another in such a way that a film of high resistance is formed during sintering. It is therefore necessary to provide a chrome barrier layer between the aluminum and tantalum layers. As a result, the series resistance is greatly reduced and decreases from about 1 megohm to about 100 ohms. It has also been found that platinum is not suitable as a barrier between aluminum and tantalum because platinum reacts with aluminum, with the result that the aluminum penetrates into the tantalum.
  • Fig. 2 The critical nature of the chromium barrier layer between tantalum and aluminum is very clearly shown in Fig. 2.
  • the diagrams show in percent the change in forward voltage (AVF%) over time for a Schottky barrier diode a composite layer of tantalum and copper-doped aluminum compared to a composite layer of tantalum, chrome and copper-doped aluminum. It can be seen that the latter metallization is four to six times more stable than the former.
  • FIG. 3 shows a diagram of the measured current-voltage characteristic in the forward direction of Schottky junction diodes with high or low potential thresholds, which are constructed according to the invention on the same semiconductor wafer.
  • the anode areas of both Schottky junction diodes are the same.
  • the potential threshold ⁇ B of the Schottky junction diode with a low potential threshold is approximately 0.5 eV.
  • the ideality factor n is approximately 1.10.
  • the potential threshold ⁇ B of the Schottky junction diode with a high potential threshold is approximately 0.8 eV.
  • the ideality factor n is approximately 1.06.
  • the invention is particularly advantageous for integrated circuits in which Schottky junction diodes with a low potential threshold are required.
  • a circuit shown in FIG. 4 is a DTL circuit according to the prior art, which represents a NAND gate.
  • This circuit does not form part of the invention per se and is well known to the person skilled in the art from semiconductor circuit technology. It should be noted here that the invention is in no way limited to this particular circuit or to the arrangement on a semiconductor die. Rather, the invention is applicable to various circuit systems, such as TTL, standard DTL, etc.
  • the circuit contains a single transistor T1 with two bias resistors, which are denoted by RB and RC, and are connected to the base and collector of the transistor T1, and a Schottky junction diode DO acting as a holding diode with a high potential threshold.
  • the circuit has six connectable outputs, in the form of Schottky junction diodes D1, D2, D3, D4, D5 and D6 with a low potential threshold and an ohmic contact on the collector electrode, which is denoted by C.
  • FIG. 5 shows a cross-sectional view of a DTL cell.
  • Each of these cells is present in the same form on a semiconductor wafer several hundred times, as is known to the person skilled in the art of semiconductor technology.
  • Transistor T1 consists of an elongated sub-collector zone 104, a base zone 123 and an emitter zone 124.
  • the Schottky junction diodes D1, D2 ... D6 are arranged symmetrically on each side of the transistor T1 in the epitaxial layer 103.
  • the collector contact C completes the transistor T1.
  • the resistors RB and RC are not shown. As shown in FIG. 5, only those diodes that are actually switched on in the circuit have the novel metallization required to represent these diodes. Therefore, the number of zones actually used, doped with interference elements, is smaller than the maximum number of possible diodes, and the locations of the unused diodes D2 and D6 are shown in broken lines.
  • Diodes D1, D3, D4 and D5 are Schottky junction diodes with a low potential threshold constructed according to the invention. They consist of N-conducting silicon 103, a tantalum layer 128, a chrome layer 130 and an aluminum-copper connection metallization 132 for a ⁇ B of approximately 0.5 eV.
  • the holding diode DO also contains a platinum-silicide layer 115 and delivers a ⁇ B of approximately 0.8 eV.
  • a positive pattern is defined by a positive photoresist, as it is marketed for example by Shipley under the names AZ1350 or AZ111.
  • the now exposed, unnecessary metal layers are removed by conventional wet etching processes for metals in a subtractive process or by placing the substrate in a plasma etching chamber which contains a gas mixture of CCl 4 -Ar for a plasma etching process.

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Abstract

Das Verfahren zum Herstellen von Tantalkontakten auf Siliciumhalbleitersubstraten eignet sich besonders für die Herstellung von Schottky - Sperrschicht - Dioden mit niedriger Potentialschwelle. Das Substrat wird vor dem Aufbringen der Tantalschicht gereinigt. Dann wird die Tantalschicht (28) bie niedrigem Druck und niedriger Substrattemperatur aufgebracht, wodurch eine Oxidation der Tantalschicht vermieden wird. Anschliessend wird der Kontakt gesintert, wodurch Grenzflächenladungen und zwischen Tantal und Substrat vorhandene Filme beseitigt werden. Wenn während der Verarbeitung ein Metall verwendet wird, das mit Silicium reagiert, wie zum Beispiel Aluminium für Verbindungsleitungen, dann muss zwischen der Tantalschicht (28) und der Aluminiumschicht (32) eine Chromschicht (30) niedergeschlagen werden.The method for producing tantalum contacts on silicon semiconductor substrates is particularly suitable for the production of Schottky junction diodes with a low potential threshold. The substrate is cleaned before the tantalum layer is applied. Then the tantalum layer (28) is applied at low pressure and low substrate temperature, whereby oxidation of the tantalum layer is avoided. The contact is then sintered, eliminating interface charges and films between tantalum and substrate. If a metal that reacts with silicon, such as aluminum for connecting lines, is used during processing, then a chrome layer (30) must be deposited between the tantalum layer (28) and the aluminum layer (32).

Description

Die Erfindung betrifft ein Verfahren von Tantal-Kontakten beim Herstellen von Metallisierungen bei der Kontaktierung von Silicium-Halbleitern zur Darstellung von ohmschen Kontakten und von Schottky-SperrschichtKontakten.The invention relates to a method of tantalum contacts in the production of metallizations in the contacting of silicon semiconductors for the representation of ohmic contacts and Schottky barrier layer contacts.

Die Anforderungen an ein Material oder an eine Kombination von Materialien für ohmsche oder Schottky-Kontakte an Halbleitersubstrate sind vom elektrischen und auch vom chemischen Standpunkt aus außerordentlich streng.The requirements for a material or for a combination of materials for ohmic or Schottky contacts on semiconductor substrates are extremely strict from the electrical and also from the chemical point of view.

Zahlreiche beim Entwurf von Halbleiterschaltungen bekannte metallurgische Systeme wurden als ohmsche Kontakte und als Schottky-Sperrschichtdioden-Kontakte vorgeschlagen und benutzt. Das wohl am meisten und mit dem größten Erfolg bei MetalLisierungsverbindungen von Silicium-Planartransistoren und integrierten Schaltungen verwendete Metall ist Aluminium oder mit einer geringen Menge Kupfer dotiertes Aluminium. Mit Aluminium lassen sich an Silicium und den umgebenden Isolierschichten gute ohmsche und mechanische Kontakte herstellen. Aluminium kann durch Verdampfung oder Kathodenzerstäubung leicht niedergeschlagen werden und läßt sich durch Ätzung oder ähnliche Verfahren leicht zu Leitungsmustern umwandeln. Während der Verarbeitung, insbesondere bei hohen Temperaturen zeigt Aluminium jedoch eine Neigung, mit Silici zu reagieren. Außerdem bildet Aluminium zusammen mit Silicium keine Schottky-Sperrschicht-Kontakte, weder mit hoher Potentialschwelle, noch mit niedriger Potentialschwelle.Numerous metallurgical systems known in the design of semiconductor circuits have been proposed and used as ohmic contacts and as Schottky junction diode contacts. The metal that is used most and with the greatest success in metalizing connections of silicon planar transistors and integrated circuits is aluminum or aluminum doped with a small amount of copper. With aluminum, good ohmic and mechanical contacts can be made on silicon and the surrounding insulating layers. Aluminum can easily be deposited by evaporation or sputtering and can be easily converted to lead patterns by etching or similar processes. However, aluminum tends to react with silici during processing, especially at high temperatures. In addition, aluminum together with silicon does not form Schottky junction contacts, neither with a high potential threshold nor with a low potential threshold.

In der Literatur findet man eine große Zahl anderer metallurgischer Systeme, die eine oder mehrere Funktionen metallischer Kontakte erfüllen. Wohl das erfolgreichste System dieser Art ist eine Titan-Wolfram-Legierung, die in der Industrie weitgehende Anwendung als Sperrschicht zwischen Aluminium und Silicium gefunden hat. Es ist jedoch nicht möglich, eine Titän-Wolfram-Legierung auf ein Halbleitersubstrat aufzudampfen. Sie muß vielmehr durch Kathodenzerstäubung aufgebracht werden. Diese Legierung kann ebensowenig durch ein Ablöseverfahren zu einem Muster umgestaltet werden.The literature contains a large number of other metallurgical systems that perform one or more functions of metallic contacts. The most successful system of this type is a titanium-tungsten alloy, which has been widely used in industry as a barrier between aluminum and silicon. However, it is not possible to vapor-deposit a titanium-tungsten alloy on a semiconductor substrate. Rather, it must be applied by sputtering. Neither can this alloy be transformed into a pattern by a detachment process.

Seit einiger Zeit bestand Bedarf nach einer Schottky-Sperrschichtdiode mit einer geringen Potentialschwelle von beispielsweise 0.5 eV. Beispielsweise ist es bei Dioden-Transistor-Logik (DTL) erwünscht, daß die Potentialschwelle der Eingangsdioden bei etwa 0.5 eV liegt. Insbesondere die unter der Kurzbezeichnung C3L bekannte DTL-Schaltung ist dann besonders brauchbar, wenn Schottk-Dioden, die eingangsseitig als UND-Glied arbeiten, diese Potentialschwelle aufweisen. Die C3 L-Schaltung ist beispielsweise in einer Veröffentlichung von A. W. Peltier mit dem Titel "Advances in Solid-State Logic - A New Approach to Bipolar LSI: C3L" in 1975 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Seiten 168-169 beschrieben. Peltier gibt dabei an, daß entweder Titan, Wolfram oder Titan-Wolfram-Legierungen diese Forderung erfüllen.For some time there has been a need for a Schottky junction diode with a low potential threshold of, for example, 0.5 eV. For example, in diode transistor logic (DTL) it is desirable that the potential threshold of the input diodes is approximately 0.5 eV. In particular, the DTL circuit known under the short designation C 3 L is particularly useful when Schottk diodes, which operate as an AND gate on the input side, have this potential threshold. The C 3 L circuit is, for example, in a publication by AW Peltier entitled "Advances in Solid-State Logic - A New Approach to Bipolar LSI: C 3 L" in the 1975 IEEE International Solid-State Circuits Conference, Digest of Technical Papers , Pages 168-169. Peltier states that either titanium, tungsten or titanium-tungsten alloys meet this requirement.

Diese Kontakte haben jedoch die bereits oben besprochenen; Nachteile.However, these contacts have those already discussed above; Disadvantage.

Gesamtdarstellung der ErfindungOverall presentation of the invention

Aufgabe der Erfindung ist es also, Halbleiterschaltungen anzugeben, die verbesserte Kontakte und Verbindungsleitungen aufweisen, die insbesondere aus einem ver- besserten einzigen metallurgischen System bestehen, das sich sowohl für ohmsche Kontakte als auch für Schottky-Sperrschiohtkontakte mit hoher und mit niedriger Potentialschwelle eignet. Vorzugsweise soll das dafür angewandte Verfahren zum Niederschlag von Tantal-Schichten für die Bildung von Schottky-Sperrschichtkontakten mit genau gesteuerter Potentialschwelle geeignet sein, wobei gleichzeitig die Verträglichkeit mit den aus Aluminium bestehenden Verbindungsleitungen sichergestellt werden soll.The object of the invention is therefore to provide semiconductor circuits which have improved contacts and connecting lines, which in particular consist of an improved single metallurgical system which is suitable both for ohmic contacts and for Schottky blocking contacts with high and low potential thresholds. The process used for the precipitation of tantalum layers should preferably be suitable for the formation of Schottky junction contacts with a precisely controlled potential threshold, while at the same time ensuring compatibility with the connecting lines made of aluminum.

Diese der Erfindung zugrunde liegende Aufgabe wird durch ein neuartiges Verfahren zum Niederschlagen von Tantal auf Silicium gelöst, wodurch man genau steuerbar eine Diodenstruktur mit niedriger Potentialschwelle erhält. Insbesondere wird dabei Tantal unmittelbar auf N-leitendem Silioium niedergeschlagen, und man erzielt eine Potentialschwelle von 0.5 eV. Während ausgiebiger Spannungsprüfungen bleibt die Diode außergewöhnlich stabil.This object on which the invention is based is achieved by a novel method for depositing tantalum on silicon, as a result of which a diode structure with a low potential threshold can be precisely controlled. In particular, tantalum is directly deposited on N-conducting silicon, and a potential threshold of 0.5 eV is achieved. The diode remains exceptionally stable during extensive voltage tests.

Das neue Verfahren besteht dabei aus folgenden Verfahrensschritten:

  • Vorbereiten der Oberfläche des Siliciums zur Verhinderung der Bildung von amorphem Silicium, vorzugsweise durch Reinigen des Siliciumsubstrats in wässeriger Flußsäure unter genau überwachten Strahlungsbedingungen vor Niederschlagen des Tantals,
  • Niederschlagen des Tantals im Vacuum bei niedrigem Druck und niedriger Substrattemperatur, um eine Oxidation des Tantals zu vermeiden,
  • Sintern des Kontakts zur Verringerung der Grenzflächen- ladungen und evtl. zwischen Silicium und Tantal befindlichen Filmen.
The new process consists of the following process steps:
  • Preparing the surface of the silicon to prevent the formation of amorphous silicon, preferably by cleaning the silicon substrate in aqueous hydrofluoric acid under carefully monitored radiation conditions before the tantalum is precipitated,
  • Precipitation of the tantalum in a vacuum at low pressure and low substrate temperature to avoid oxidation of the tantalum,
  • Sintering of the contact to reduce the interfacial charges and possibly films between silicon and tantalum.

Der Niederschlag von Tantal kann beispielsweise durch Elektronenstrahlverdampfung in einem Vakuum von maximal 2.5 x 10-6 TORR und bei einer Substrattemperatur von maximal 200°C durchgeführt werden. Dieser Niederschlag kann auch durch Hochfrequenzzerstäubung in einer Kammer durchgeführt werden, die vor dem Zerstäubungsvorgang ein Anfangsvakuum von 4 x 10-7 TORR aufweist. (1 TORR = 1,333224 mbar)The precipitation of tantalum can be carried out, for example, by electron beam evaporation in a vacuum of 2.5 x 10 -6 TORR and at a substrate temperature of 200 ° C or less. This precipitation can also be carried out by high frequency atomization in a chamber which has an initial vacuum of 4 x 10 -7 TORR before the atomization process. (1 TORR = 1.333224 mbar)

Eine auf diese Weise niedergeschlagene Tantal-Schicht eignet sich einmal als ohmscher Kontakt dann, wenn sie auf der Oberseite einer in N+-leitendem Silicium gebildeten Metall-Silicid-Schicht aufgetragen wird und auch als Schottky-Sperrschichtdiode (SBD) mit hoher Potentialschwelle, wenn die Schicht auf der Oberseite einer in N-leitenden Silicium gebildeten metallischen Silicid-Schicht niedergeschlagen wird.A tantalum layer deposited in this way is suitable as an ohmic contact when it is applied to the top of a metal-silicon layer formed in N + -conducting silicon and also as a Schottky barrier diode (SBD) with a high potential threshold, if the layer is deposited on top of a metallic silicide layer formed in N-type silicon.

Wenn Aluminium als Leitungsmetallisierung verwendet wird, dann muß zwischen der Tantalschicht und der Aluminium- schicht eine Chromschicht niedergeschlagen werden. Die Chromschicht wird dadurch gebildet, daß während der Verdampfung oder der Kathodenzerstäubung von elementarem Chrom ein Wasserdampf eingeleitet wird. Die Langzeitzuverlässigkeit dieses metallurgischen Systems ist außergewöhnlich gut.If aluminum is used as the line metallization, then a chrome layer must be deposited between the tantalum layer and the aluminum layer. The chrome layer is formed by introducing water vapor during the evaporation or sputtering of elemental chromium. The long-term reliability of this metallurgical system is exceptionally good.

Die Erfindung wird nunmehr anhand von Ausführungsbeispielen in Verbindung mit den beigefügten Zeichnungen im einzelnen beschrieben. Die unter Schutz zu stellenden Merkmale der Erfindung sind den ebenfalls beigefügten Patentansprüchen im einzelnen zu entnehmen.The invention will now be described on the basis of exemplary embodiments in conjunction with the accompanying drawings described in detail. The features of the invention to be protected are to be found in detail in the attached patent claims.

Dabei zeigt

  • Fig. 1 in den Teilfiguren 1A - 1F Teilschnittansichten einer Halbleitervorrichtung gemäß der Erfindung während der verschiedenen Fertigungsverfahrensschritte, j
  • Fig. 2 ein Diagramm der Spannungskennlinie über der Zeit unter Belastung einer Chrom-Tantal-Schottky-Sperrschichtdiode im Vergleich mit einer Tantal-Sperrschicht- diode, wenn Aluminium darauf niedergeschlagen ist,
  • Fig. 3 ein Diagramm der Durchlaß-Stromspannungskennlinien von gemäß der Erfindung aufgebauten Schottky-Sperrschichtdioden mit niedriger und hoher Potentialschwelle,
  • Fig. 4 eine logische DTL-Schaltung und
  • Fig. 5 eine Querschnittsansicht einer Halbleiterschaltung mit Schottky-Sperrschichtdioden gemäß der Erfindung.
It shows
  • 1 in the partial figures 1A - 1F partial sectional views of a semiconductor device according to the invention during the various manufacturing process steps, j
  • 2 shows a diagram of the voltage characteristic curve over time under load of a chromium-tantalum-Schottky junction diode in comparison with a tantalum junction diode when aluminum is deposited thereon,
  • 3 shows a diagram of the forward current-voltage characteristics of Schottky junction diodes constructed according to the invention with low and high potential threshold,
  • Fig. 4 shows a logical DTL circuit and
  • 5 shows a cross-sectional view of a semiconductor circuit with Schottky junction diodes according to the invention.

EinzelbeschreibungIndividual description

Die Teil-Fig. 1A zeigt den Teil eines Halbleiterplättchens, welcher die erfindungsgemäß aufgebauten Schottky-Sperrschichtdioden enthalten soll. Es ist einleuchtend, daß normalerweise innerhalb des gleichen Halbleiterplättchens tausende solcher Dioden und anderer Halbleitervorrichtungen, wie zum Beispiel Transistoren, Widerstände usw. angeordnst sein konnen. Das Substrat des Halbleiterplättchens besteht beispielsweise aus P-leitendem Silicium, das einen spezifischen Widerstand von 10 Ohm-cm aufweist. Auf diesem Substrat 1 ist eine N--leitende Schicht 3 angebracht, die vorzugsweise eine Leitfähig- keit von 1 x 1016 bis 8 x 1016 Atome/cm3 aufweist. In dem Substrat sind zwei vergrabene Zonen 4 und 6 vorge sehen, die über Anschlußzonen 5 und 7 an die Oberfläche des Substrats herausgeführt sind. Das Substrat enthält außerdem eine P+-leitende Subisolationszone 2, die in Verbindung mit einer P+-leitenden Isolationszone 8 die N+-leitenden Zonen gegeneinander abtrennt.The part-Fig. 1A shows the part of a semiconductor die which is to contain the Schottky junction diodes constructed according to the invention. It is obvious that normally within the same die Thousands of such diodes and other semiconductor devices, such as transistors, resistors, etc., can be arranged. The substrate of the semiconductor die consists, for example, of P-type silicon, which has a resistivity of 10 ohm-cm. On this substrate 1, an N - -type layer 3 is attached, preferably having a conductivity ke it from 1 x 10 16 to 8 x 10 16 atoms / cm 3. In the substrate, two buried zones 4 and 6 are easily seen, which are led out via connection zones 5 and 7 to the surface of the substrate. The substrate also contains a P + -conducting sub-isolation zone 2 which, in conjunction with a P + -conductive isolation zone 8, separates the N + -conducting zones from one another.

Die Zonen 2, 4 und 6 werden vorteilhafterweise durch Eindiffundieren dieser Zonen durch öffnungen hergestellt, die in der die Oberfläche des Substrats bedeckenden Schicht vorgesehen sind. Ein eine N -Leitung hervorrufen des Störelement ist Arsen oder Phosphor, ein eine P+-Leitfähigktit hervorrufendes Störelement ist Bor.Zones 2, 4 and 6 are advantageously produced by diffusing these zones through openings provided in the layer covering the surface of the substrate. An interference element causing an N line is arsenic or phosphorus, a interference element causing a P + conductivity is boron.

Die Maskenschicht wird dann durch übliche Ätzverfahren vom Substrat 1 abgezogen, und es wird dabei epitaxial eine Schicht 3 aufgewachsen, wobei die Zonen 2, 4 und 6 durch Ausdiffusion in die Schicht 3 eindringen. Eine Maskenschicht, die normalerweise aus einer Siliciumdioxid-Schicht 9 und einer Siliciumnitrid-Schicht 10 zusammengesetzt ist, wird dann auf der Oberfläche der Schicht 3 gebildet und in dieser zusammengesetzten Masken schicht werden dann Öffnungen hergestellt, durch die die eine N+-Leitfähigkeit bzw. P+-Leitfähigkeit erzeugenden Störelemente zur Bildung der Kontaktzonen 5 und 7 bzw. der Isolationszone 8 eindiffundiert werden.The mask layer is then removed from the substrate 1 by conventional etching methods, and a layer 3 is grown epitaxially, the zones 2, 4 and 6 penetrating into the layer 3 by diffusion. A mask layer, which is normally composed of a silicon dioxide layer 9 and a silicon nitride layer 10, is then formed on the surface of the layer 3, and openings are then produced in this mask layer, through which openings the N + conductivity or P + - Conducting interference elements to form the contact zones 5 and 7 or the isolation zone 8 are diffused.

Anschließend wird dann, alles überdeckend, auf der Siliciumnitrid-Schicht und innerhalb der öffnungen 11, ! 12, 13 und 14 eine Platin-Schicht 15, vorzugsweise durch Verdampfen oder Kathodenzerstäubung, bis zu einer Dicke von 40 nm aufgetragen. Die in der öffnung 13 liegende Siliciumdioxid-Schicht 9 verhindert, daß das Platin in dieser öffnung mit dem Substrat in Berührung kommt.Then, covering everything, on the silicon nitride layer and within the openings 11,! 12, 13 and 14, a platinum layer 15, preferably by evaporation or sputtering, applied to a thickness of 40 nm. The silicon dioxide layer 9 lying in the opening 13 prevents the platinum in this opening from coming into contact with the substrate.

In der Teil-Fig. 1B wird das Halbleiterplättchen dann für etwa 20 Minuten bei einer Temperatur von 550°C in einer Stickstoffatmosphäre gesintert, wodurch das Platin mit dem Silicium reagiert und in den öffnungen 12, 13 und 14 Platin-Silicid-Schichten 15' bildet. Das nicht umgesetzte Platin, einschließlich der über der Siliciumdioxid-Schicht 10 liegenden Platin-Schicht wird dann durch Ätzen mit Königswasser entfernt. Bekanntlich können auch andere Metalle, wie Palladium, Nickel oder Hafnium anstelle von Platin verwendet werden. Im nächsten Verfahrensschritt gemäß Teil-Fig. 1C wird der in der Öffnung 13 liegende Teil der Siliciumdioxid-Schicht 9 durch ein nasses oder trockenes Ätzverfahren entfernt, wodurch dieser Teil des Substrats freigelegt wird, welcher dann die Anode einer Schottky-Sperrschichtdiode mit niedriger Potentialschwelle bilden soll.In the part-Fig. 1B, the semiconductor die is then sintered for about 20 minutes at a temperature of 550 ° C. in a nitrogen atmosphere, as a result of which the platinum reacts with the silicon and forms platinum-silicide layers 15 ′ in the openings 12, 13 and 14. The unreacted platinum, including the platinum layer overlying the silicon dioxide layer 10, is then removed by etching with aqua regia. As is known, other metals such as palladium, nickel or hafnium can also be used instead of platinum. In the next process step according to part-Fig. 1C, the part of the silicon dioxide layer 9 lying in the opening 13 is removed by a wet or dry etching process, whereby this part of the substrate is exposed, which is then to form the anode of a Schottky junction diode with a low potential threshold.

Das Niederschlagen des neuen Metallisierungssystems wird dann in den öffnungen 11 bis 14 vorgenommen. Das bevorzugte Ablöseverfahren ist in der der Anmelderin gehörenden US-Patentschrift 4 004 044 eingehend beschrieben. Dieses Verfahren soll in abgekürzter Form anhand der Teil-Fign. 1D - 1F beschrieben werden. Andere Verfahren zum Bilden der Metallisierung sind nasse oder reaktive Ionen- (Plasma-) Ätzverfahren, die dem Fachmann allgemein zugängig sind. Das Ablöseverfahren gestattet jedoch eine wesentlich bessere Definition der Metallisierung, wodurch die für die Verdrahtung erforderliche Fläche wesentlich herabgesetzt wird.The new metallization system is then deposited in openings 11 to 14. The preferred detachment method is described in detail in applicant's U.S. Patent 4,004,044. This method is intended to be abbreviated based on the partial fig. 1D - 1F. Other methods of forming the metallization are wet or reactive ion (plasma) etching methods that are generally available to those skilled in the art. However, the replacement procedure allows a much better definition of the Metallization, which significantly reduces the area required for wiring.

Gemäß der Teil-Fig. 1D wird nunmehr, alles überdeckend, eine dünne Schicht aus Polyäthersulphon aufgebracht, die das Ablöseverfahren erleichtert. Die Verwendung von Polyäthersulphon oder kurz Polysulphon ist eine Abänderung des in dem oben genannten Patent erwähnten Verfahrens un wurde in IBM Technical Disclosure Bulletin, Band 19, Nr. 4, vom September 1976, auf Seite 1226 beschrieben. über der Polysulphon-Schicht 20 wird eine Schicht 22 aus einem organischen Polymeren aufgebracht, wie zum Beispiel auf Novalak-Harz-Basis aufgebauter positiver Photolack, der anschließend bei 210 - 230°C gebrannt oder gehärtet wird, so daß der Photolack nicht mehr photoempfindlich ist. über der Photolackschicht 22 wird eine aus einem Methyl-Siloxan-Harz bestehende Sperrschicht 24 aufgebracht und anschließend eine Schicht 26 aus einem strahlungsempfindlichen Photolack.According to the part-Fig. 1D, covering everything, a thin layer of polyether sulphone is now applied, which facilitates the detachment process. The use of polyether sulphone, or polysulphone for short, is a modification of the method mentioned in the above-mentioned patent and was described in IBM Technical Disclosure Bulletin, Volume 19, No. 4, September 1976, on page 1226. A layer 22 of an organic polymer is applied over the polysulphone layer 20, such as positive photoresist based on Novalak resin, which is subsequently baked or cured at 210-230 ° C. so that the photoresist is no longer photosensitive . A barrier layer 24 consisting of a methyl siloxane resin is applied over the photoresist layer 22 and then a layer 26 of a radiation-sensitive photoresist.

Die Photolackschicht 26 wird dann zur Erstellung eines reliefartigen Musters entsprechend den öffnungen 11, 12, 13 und 14 in der Teil-Fig. 1C belichtet und entwickelt. Die Photolackmaske 26 wird dann für die selektive Entfernung der darunter liegenden Schichten 20, 22 und 24 zum Freilegen der öffnungen 11', 12', 13' und 14' in der Teil-Fig. 1D verwendet, die den in Teil-Fig. 1C gezeigten öffnungen entsprecher.The photoresist layer 26 is then used to create a relief-like pattern corresponding to the openings 11, 12, 13 and 14 in the partial FIG. 1C exposed and developed. The photoresist mask 26 is then used for the selective removal of the layers 20, 22 and 24 underneath to expose the openings 11 ', 12', 13 'and 14' in the part of FIG. 1D used, which the in Fig. 1C corresponding openings shown.

Nach Herstellen der Öffnungen wird das freiliegende Substrat einschließlich der Platin-Silicid-Schicht 15 einer Vorreinigung unter genau überwachten Strahlungsbedingungen mit einer Mischung 15 : 1 oder weniger von Wasser und Flußsäure-Ätzmitteln unterzogen. Ein Mischungs verhältnis von 5 : 1 ist am vorteilhaftesten. Der Ausdruck "genau überwachte Strahlungsbedingungen" soll bedeuten, daß während dieses Ätzverfahrensschrittes keine merkliche Lichtmenge mit einer Wellenlänge kürzer als 500 nm vorhanden sein darf. Durch diese vorbereitenden Verfahrensschritte wird in dem Kontaktbereich die Bildung einer aus amorphem Silicium bestehenden Schicht verhindert, die sich sonst sehr nachteilig auswirken könnte, da sie die Potentialschwelle erhöht. Diese Vorbereitung der Silicium-Oberfläche ist zur Erzielung einer Schottky-Sperrschichtdiode mit niedriger Potentialschwelle von etwa 0.5 Volt erforderlich. Die Anmelderin hat versucht, die Oberfläche gemäß üblicher Verfahren mit chemischen Ätzmitteln unter weißem Licht zu reinigen. Mit diesem bekannten Verfahren war es jedoch nicht möglich, eine so niedrige Potentialschwelle zu erzielen, man hat vielmehr nur eine Potentialschwelle von etwa 0.61 eV erreicht. D.a Anmelderin hat außerdem versucht, die Halbleiteroberfläche in situ in einer Zerstäubungskammer durch Kathodenzerstäubung zu reinigen. Dieses i Verfahren ergab zwar eine Potentialschwelle von etwa 0.5 eV, jedoch war der Idealitätsfaktor mit 1.15 zu hoch. Außerdem ließ sich diese Potentialschwelle exakt nicht wiederholen.After the openings have been made, the exposed substrate including the platinum-silicide layer 15 is subjected to a pre-cleaning under closely monitored radiation conditions with a mixture of 15: 1 or less of water and hydrofluoric acid etchant. A mixing ratio of 5: 1 is most advantageous. The out Pressure "closely monitored radiation conditions" is intended to mean that no noticeable amount of light with a wavelength shorter than 500 nm may be present during this etching process step. These preparatory process steps prevent the formation of an amorphous silicon layer in the contact area, which could otherwise have a very disadvantageous effect, since it increases the potential threshold. This preparation of the silicon surface is necessary to achieve a Schottky junction diode with a low potential threshold of about 0.5 volts. The applicant has tried to clean the surface using chemical etching agents under white light in accordance with customary methods. With this known method, however, it was not possible to achieve such a low potential threshold; rather, a potential threshold of approximately 0.61 eV was reached. The applicant has also attempted to clean the semiconductor surface in situ in a sputtering chamber by sputtering. Although this method resulted in a potential threshold of about 0.5 eV, the ideality factor of 1.15 was too high. In addition, this potential threshold could not be repeated exactly.

Gemäß Teil-Fig. 1E wird, alles überdeckend, eine aus Tantal bestehende Schicht 28 über dem Substrat und der Ablösemaske aufgebracht. Damit tatsächlich ein Schottky-Sperrschichtkontakt mit niedriger Potentialschwelle erzielt werden kann, muß dieser Niederschlag der Tantal- Schicht ebenfalls mit einem sehr sorgfältig durchgeführten Verfahren erfolgen. Der Niederschlag erfolgt am besten mit einer Elektronenstrahl-Verdampfungsquelle, wie sie beispielsweise von der Firma Airco-Temescal Corp. als Modell FC1800 geliefert wird. Ähnliche Ausführungsformen von Verdampfungssystemen werden von anderen Herstellern angeboten. Der höchste in der Verdampfungskammer herrschende Druck beträgt während des Verfahrens 2.5 x 10 6 TORR, wobei der Anfangsdruck in der Kammer weniger als 4 x 10-7 TORR ist. Die Maximaltemperatur des Substrats beträgt 200°C. Der hier angegebene Druckes ist für die Menge der in der Kammer vorhandenen Feuchtigkeit, Kohlenwasserstoffe und anderer gasförmiger Verunreinigungen von Bedeutung. Je höher der Druck, umso höher die Feuchtigkeit und der Anteil an Verunreinigungen, die eine leichte Oxidation der Tantal- Schicht hervorrufen können, so daß sich eine Potentialschwelle von etwas mehr als 0.5 eV ergibt. Wenn eine Potentialschwelle dieser Größe annehmbar ist, dann ist der Druck in der Kammer von geringerer Bedeutung und man könnte übliche Verfahren einsetzen. Das Niederschlagsverfahren, das mit einer Geschwindigkeit von etwa 0.2 nm je Sekunde abläuft, wird fortgesetzt, bis eine Schichtdicke von 60 + 15 nm erreicht ist. Die unter diesen Bedingungen erzeugte Tantal-Schicht besteht aus f kubisch-raumzentrierten Kristallen.According to part-Fig. 1E, covering everything, a tantalum layer 28 is applied over the substrate and the release mask. So that a Schottky junction contact with a low potential threshold can actually be achieved, this precipitation of the tantalum layer must likewise be carried out using a very carefully carried out process. The precipitation is best carried out with an electron beam evaporation source, such as that from Airco-Temescal Corp. is supplied as model FC1800. Similar embodiments of evaporation systems are described by others other manufacturers. The highest pressure in the evaporation chamber during the process is 2.5 x 10 6 TORR, the initial pressure in the chamber being less than 4 x 10-7 TORR. The maximum temperature of the substrate is 200 ° C. The pressure specified here is important for the amount of moisture, hydrocarbons and other gaseous contaminants present in the chamber. The higher the pressure, the higher the moisture and the proportion of impurities that can cause a slight oxidation of the tantalum layer, so that a potential threshold of slightly more than 0.5 eV results. If a potential threshold of this size is acceptable, then the pressure in the chamber is of less importance and conventional methods could be used. The precipitation process, which runs at a speed of about 0.2 nm per second, continues until a layer thickness of 60 + 15 nm is reached. The tantalum layer produced under these conditions consists of f body-centered cubic crystals.

Statt durch Verdampfung kann Tantal auch unter gleichen Druck- und Temperaturbedingungen durch Hochfrequenzzerstäubung aufgebracht werden. Gleichspannungszerstäubung ist nicht geeignet, da bei Gleichspannungszerstäubung aufgebrachte Tantal-Schichten aus raumzentrierten tetragonalen Kristallen bestehen, während durch Hochfrequenz zerstäubtes Tantal sich als kubisch-raumzentrierte Kristalle niederschlägt.Instead of evaporation, tantalum can also be applied under high pressure and temperature conditions using high frequency sputtering. DC voltage sputtering is not suitable, since tantalum layers applied with DC voltage sputtering consist of body-centered tetragonal crystals, while high-frequency sputtered tantalum is deposited as body-centered cubic crystals.

Nach der Verdampfung der Tantal-Schicht 28 wird eine Schicht 30 aus Chrom und eine Schicht 32 aus Aluminium oder aus mit Kupfer dotiertem Aluminium bzw. mit Kupfer dotiertem Aluminium-Silicium, vorzugsweise in der gleichen Verdampfungskammer niedergeschlagen.After the evaporation of the tantalum layer 28, a layer 30 made of chrome and a layer 32 made of aluminum or of aluminum doped with copper or aluminum-doped with copper, is preferably deposited in the same evaporation chamber.

Die Chrom-Schicht wird vorzugsweise bis zu einer Dicke von 60 - 100 nm niedergeschlagen. Während dieses Ver- dampfungsvorgangs muß Wasserdampf in die Kammer eingeleitet werden. Das Substrat wird dabei auf einer Maximaltemperatur von 160°C gehalten, wobei dem Substrat keinerlei Wärme zugeführt wird. In dem Verfahren wird eine geringe Menge Chrom in das Schiffchen eingebracht und Wasserdampf wird in die Verdampfungskammer eingeleitet, deren Druck bei etwa 10-5 TORR gehalten wird.The chrome layer is preferably deposited to a thickness of 60-100 nm. Water vapor must be introduced into the chamber during this evaporation process. The substrate is kept at a maximum temperature of 160 ° C, with no heat being supplied to the substrate. In the process, a small amount of chromium is introduced into the boat and water vapor is introduced into the evaporation chamber, the pressure of which is kept at about 10 -5 TORR.

Bei Erwärmung durch einen Elektronenstrahl wird das reine Chrom in dem Schiffchen verdampft und zu handelsüblichem Chrom umgewandelt, was für die Bildung der Sperr- schicht kritisch ist. Das mit Wasserdampfzufuhr niedergeschlagene Chrom weist an den Korngrenzen Chromoxid auf. Wir haben festgestellt, daß reines Chrom, d. h. elementares Chrom als Sperrschicht zwischen Aluminium und Tantal wirkungslos ist.When heated by an electron beam, the pure chromium in the boat is evaporated and converted to commercially available chromium, which is critical for the formation of the barrier layer. The chromium precipitated with the addition of water vapor has chromium oxide at the grain boundaries. We have found that pure chromium, i.e. H. elemental chrome as a barrier between aluminum and tantalum is ineffective.

Das Aluminium wird vorzugsweise bis zu einer Schicht- dicke von 850 - 1000 nm niedergeschlagen. Ein mit einer. geringen Menge Kupfer dotiertes Aluminium ist reinem Aluminium vorzuziehen. Es soll hier der Ausdruck Aluminium in der Weise verwendet werden, daß auch mit Kupfe dotiertes Aluminium und auch mit Kupfer dotiertes Aluminium-Silicium darunter verstanden werden soll. Die sich dabei ergebende Struktur zeigt Teil-Fig. 1E.The aluminum is preferably deposited down to a layer thickness of 850-1000 nm. One with one. A small amount of copper-doped aluminum is preferable to pure aluminum. The term aluminum is to be used here in such a way that it is also to be understood as meaning copper-doped aluminum and also copper-doped aluminum silicon. The resulting structure shows part-Fig. 1E.

Die verbleibende Ablösestruktur und die darüberliegende Metallschicht werden unter Verwendung von N-Methyl- pyrrolidon oder einem anderen geeigneten Lösungsmittel rasch abgehoben, so daß ein metallisches Muster auf der Oberfläche des Substrats oder der Oxidschicht 10 verbleibt, wie dies Teil-Fig. 1F zeigt.The remaining release structure and the overlying metal layer are quickly lifted off using N-methylpyrrolidone or other suitable solvent so that a metallic pattern remains on the surface of the substrate or oxide layer 10 as shown in part-Fig. 1F shows.

Dann wird diese Struktur für etwa 1 Stunde bei 400°C und dann erneut für weitere 2 Stunden bei 450°C gesintert. Dieser Sinter-Verfahrensschritt ist wichtig, da er die Grenzflächen-Ladungen und Filme zwischen Silicium Substrat und dem Tantal zumindest verringert, meist aber beseitigt. Obgleich diese Zeiten und Temperaturangaben vorteilhaftesten sind, können auch andere Werte durch normale Versuche ermittelt werden, die ebenso wirksam sein mögen. Diese Sinterung ist erforderlich, um die Höhe der Potentialschwelle von 0.5 eV zu erzielen, selbst dann, wenn nur Tantal als Kontaktmaterial, d. h. ohne Chrom und Aluminium verwendet worden wäre.Then this structure is sintered for about 1 hour at 400 ° C and then again for another 2 hours at 450 ° C. This sintering process step is important because it at least reduces the interface charges and films between the silicon substrate and the tantalum, but mostly eliminates them. Although these times and temperatures are the most advantageous, other values can also be determined by normal experiments, which may be just as effective. This sintering is necessary in order to reach the potential threshold of 0.5 eV, even if only tantalum is used as the contact material, i.e. H. would have been used without chrome and aluminum.

Damit ist das Grundverfahren beendet, und man hat Schottky-Sperrschichtdioden mit hoher Potentialschwelle und mit niedriger Potentialschwelle. Die Anode und die Kathode der Schottky-Sperrschichtdiode mit hoher Potentialschwelle sind durch die Bezugszeichen 34 bzw. 35 in Teil-Fig. 1F bezeichnet. Anode und Kathode der Schottky-Sperrschichtdiode mit niedriger Potentialschwelle sind durch die Bezugszeichen 36 bzw. 37 bezeichnet.This concludes the basic process and you have Schottky junction diodes with a high potential threshold and a low potential threshold. The anode and cathode of the Schottky junction diode with high potential threshold are indicated by reference numerals 34 and 35 in part-Fig. 1F. The anode and cathode of the Schottky junction diode with low potential threshold are denoted by reference numerals 36 and 37, respectively.

Unter Verwendung der gleichen Metallisierung wurden drei verschiedene Arten von Kontakten hergestellt. Die Kathoden beider Dioden sind die nach den N+-leitenden Zonen 5 und 7 in der Schicht 3 führenden ohmschen Kontakte. Die Anode 34 der Schottky-Sperrschichtdiode mit hoher Potentialschwelle verwendet eine Chrom-Tantal-Metallisierung zwischen der Platin-Silicid-Schicht 15 und der Aluminium-Schicht 32, welche als Diffusionssperre wirkt, während die Platin-Silicid-Schicht eine erhöhte Potentialschwelle ergibt, verglichen mit der Anode 36 der Schottky-Sperrschichtdiode mit niedriger Potentialschwelle, wo keine Platin-Silicid-Schicht vorhanden ist. In der Zone 36 berührt die Tantal-Schicht das N-leitende Silicium-Substrat 3 unmittelbar.Three different types of contacts were made using the same metallization. The cathodes of both diodes are the ohmic contacts leading to the N + -conducting zones 5 and 7 in layer 3. The anode 34 of the Schottky junction diode with a high potential threshold uses a chromium-tantalum metallization between the platinum-silicide layer 15 and the aluminum layer 32, which acts as a diffusion barrier, while the platinum-silicide layer gives an increased potential threshold compared with the anode 36 of the Schottky junction diode with a low potential threshold, where there is no platinum-silicide layer. In zone 36, the tantalum layer directly contacts the N-type silicon substrate 3.

In der Praxis ist bei der Herstellung einer Schottky- Sperrschichtdiode mit hoher Potentialschwelle die Tantal- Schicht nicht erforderlich. Ein aus Aluminium, Chrom und Platin-Silicid bestehender Kontakt ist völlig zufriedenstellend. Es ist jedoch bei der praktischen Herstellung wesentlich besser, das Tantal, alles überdeckend, innerhalb aller Kontaktöffnungen niederzuschlagen. !In practice, the tantalum layer is not required when manufacturing a Schottky junction diode with a high potential threshold. A contact made of aluminum, chrome and platinum silicide is completely satisfactory. However, in practical production, it is much better to deposit the tantalum, covering everything, within all contact openings. !

Es wurde dabei festgestellt, daß die Chrom-Schicht 30 insofern kritisch ist, da sie als Sperrschicht eine Wechselwirkung zwischen Aluminium und Tantal verhindert. Es ist allgemein bekannt, daß Aluminium in einer unzu- träglichen Weise mit Silicium reagiert und auch Platin-Silicid für eine Wechselwirkung oder Reaktion mit Silicium durchdringt. Entgegen allen Erwartungen reagieren Tantal und Aluminium jedoch miteinander in der Weise, daß beim Sintern ein Film hoher Widerstandsfähigkeit gebildet wird. Es ist daheß notwendig, zwischen der Aluminium- und der Tantal-Schicht eine aus Chrom bestehende Sperrschicht vorzusehen. Das hat zur Folge, daß der Serienwiderstand stark verringert wird und von etwa 1 Megohm auf etwa 100 Ohm zurückgeht. Es wurde ferner festgestellt, daß Platin als Sperrschicht zwischen Aluminium und Tantal nicht geeignet ist, weil Platin mit Aluminium reagiert, was zur Folge hat, daß das Aluminium in das Tantal eindringt.It was found that the chromium layer 30 is critical in that it, as a barrier layer, prevents an interaction between aluminum and tantalum. It is well known that aluminum reacts in an unacceptable manner with silicon and also penetrates platinum silicide for interaction or reaction with silicon. Contrary to all expectations, tantalum and aluminum react with one another in such a way that a film of high resistance is formed during sintering. It is therefore necessary to provide a chrome barrier layer between the aluminum and tantalum layers. As a result, the series resistance is greatly reduced and decreases from about 1 megohm to about 100 ohms. It has also been found that platinum is not suitable as a barrier between aluminum and tantalum because platinum reacts with aluminum, with the result that the aluminum penetrates into the tantalum.

Die kritische Natur der zwischen Tantal und Aluminium liegenden aus Chrom bestehenden Sperrschicht wird sehr schön deutlich aus Fig. 2. Die Diagramme zeigen in Prozenten die Veränderung der Durchlaßspannung (AVF%) über die Zeit für eine Schottky-Sperrschichtdiode mit einer zusammengesetzten Schicht aus Tantal und mit Kupfer dotiertem Aluminium, im Vergleich mit einer zusammengesetzten Schicht aus Tantal, Chrom und mit Kupfer dotiertem Aluminium. Man sieht, daß die letztgenannte Metallisierung vier- bis sechsmal stabiler ist, als die erstgenannte.The critical nature of the chromium barrier layer between tantalum and aluminum is very clearly shown in Fig. 2. The diagrams show in percent the change in forward voltage (AVF%) over time for a Schottky barrier diode a composite layer of tantalum and copper-doped aluminum compared to a composite layer of tantalum, chrome and copper-doped aluminum. It can be seen that the latter metallization is four to six times more stable than the former.

Fig. 3 zeigt ein Diagramm der gemessenen Stromspannungskennlinie in Durchlaßrichtung von erfindungsgemäß auf dem gleichen Halbleiterplättchen aufgebauten Schottky-Sperrschichtdioden mit hoher bzw. niedriger Potentialschwelle. Die Anodenflächen beider Schottky-Sperrschicht dioden sind die gleichen. Die Potentialschwelle ØB der Schottky-Sperrschichtdiode mit niedriger Potentialschwelle beträgt angenähert 0.5 eV. Der Idealitätsfaktor n ist angenähert 1.10.FIG. 3 shows a diagram of the measured current-voltage characteristic in the forward direction of Schottky junction diodes with high or low potential thresholds, which are constructed according to the invention on the same semiconductor wafer. The anode areas of both Schottky junction diodes are the same. The potential threshold Ø B of the Schottky junction diode with a low potential threshold is approximately 0.5 eV. The ideality factor n is approximately 1.10.

Die Potentialschwelle ØB der Schottky-Sperrschichtdiode mit hoher Potentialschwelle liegt bei angenähert 0.8 eV. Der Idealitätsfaktor n beträgt angenähert 1.06.The potential threshold Ø B of the Schottky junction diode with a high potential threshold is approximately 0.8 eV. The ideality factor n is approximately 1.06.

Wie bereits erwähnt, ist die Erfindung insbesondere für integrierte Schaltungen von Vorteil, bei der Schottky-Sperrschichtdioden mit niedriger Potentialschwelle erforderlich sind. Eine solche in Fig. 4 dargestellte Schaltung ist eine DTL-Schaltung gemäß dem Stande der Technik, die ein NAND-Glied darstellt. Diese Schaltung bildet keinen Teil der Erfindung an sich und ist dem Fachmann aus der Halbleiterschaltungstechnik gut bekannt. Es sei hier angemerkt, daß die Erfindung in keiner Weise auf diese bestimmte Schaltung oder auf die Anordnung auf einem Halbleiterplättchen beschränkt ist. Vielmehr ist die Erfindung auf verschiedene Schaltungssysteme, wie zum Beispiel TTL, Standard DTL usw. anwendbar .As already mentioned, the invention is particularly advantageous for integrated circuits in which Schottky junction diodes with a low potential threshold are required. Such a circuit shown in FIG. 4 is a DTL circuit according to the prior art, which represents a NAND gate. This circuit does not form part of the invention per se and is well known to the person skilled in the art from semiconductor circuit technology. It should be noted here that the invention is in no way limited to this particular circuit or to the arrangement on a semiconductor die. Rather, the invention is applicable to various circuit systems, such as TTL, standard DTL, etc.

Diese Art von Schaltung und ihre Abwandlungen sind in einem Aufsatz von Peltier mit dem Titel "A New Approach to Bipolar SLI: C3L" in 1975 IEEE International Solid- State Circuits Conference, Digest of Technical Papers, Seiten 168 - 169 beschrieben. Die Schaltung enthält einen einzigen Transistor T1 mit zwei Vorspannungswiderständen, die mit RB bzw. RC bezeichnet sind, und an Basis bzw. Kollektor des Transistors T1 angeschlossen sind, und aus einer als Haltediode wirkenden Schottky-Sperrschichtdiode DO mit hoher Potentialschwelle. Die Schaltung hat sechs anschließbare Ausgänge, in Form von Schottky-Sperrschichtdioden D1, D2, D3, D4, D5 und D6 mit niedriger Potentialschwelle und einen ohmschen Kontakt an der Kollektorelektrode, der mit C bezeichnet ist.This type of circuit and its modifications are described in a Peltier article entitled "A New Approach to Bipolar SLI: C 3 L" in the 1975 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 168-169. The circuit contains a single transistor T1 with two bias resistors, which are denoted by RB and RC, and are connected to the base and collector of the transistor T1, and a Schottky junction diode DO acting as a holding diode with a high potential threshold. The circuit has six connectable outputs, in the form of Schottky junction diodes D1, D2, D3, D4, D5 and D6 with a low potential threshold and an ohmic contact on the collector electrode, which is denoted by C.

Fig. 5 zeigt eine Querschnittsansicht einer DTL-Zelle. Jede dieser Zellen ist in gleicher Form auf einem Halbleiterplättchen mehrere hundert mal vorhanden, wie dies dem Fachmann der Halbleitertechnik bekannt ist.5 shows a cross-sectional view of a DTL cell. Each of these cells is present in the same form on a semiconductor wafer several hundred times, as is known to the person skilled in the art of semiconductor technology.

Transistor T1 besteht aus einer langgestreckten Subkollektorzone 104, einer Basiszone 123 und einer Emitterzone 124. Die Schottky-Sperrschichtdioden D1, D2 ... D6 sind symmetrisch auf jeder Seite des Transistors T1 in der Epitaxialschicht 103 angeordnet. Der Kollektorkontakt C vervollständigt den Transistor T1. Die Widerstände RB und RC sind nicht gezeigt. Wie in Fig. 5 dargestellt, weisen nur diejenigen Dioden, die tatsächlich in die Schaltung eingeschaltet sind, die zur Darstellung dieser Dioden erforderliche neuartige Metallisierung auf. Daher ist die Anzahl der tatsächlich verwendeten, mit Störelementen dotierten Zonen kleiner als die maximale Anzahl der möglichen Dioden, und die Orte der nicht benutzten Dioden D2 und D6 sind in gestrichelten Linien gezeigt.Transistor T1 consists of an elongated sub-collector zone 104, a base zone 123 and an emitter zone 124. The Schottky junction diodes D1, D2 ... D6 are arranged symmetrically on each side of the transistor T1 in the epitaxial layer 103. The collector contact C completes the transistor T1. The resistors RB and RC are not shown. As shown in FIG. 5, only those diodes that are actually switched on in the circuit have the novel metallization required to represent these diodes. Therefore, the number of zones actually used, doped with interference elements, is smaller than the maximum number of possible diodes, and the locations of the unused diodes D2 and D6 are shown in broken lines.

Die Dioden D1, D3, D4 und D5 sind erfindungsgemäß aufgebaute Schottky-Sperrschichtdioden mit niedriger Potentialschwelle. Sie bestehen aus N-leitendem Silicium 103, einer Tantal-Schicht 128, einer Chrom-Schicht 130 und einer Aluminium-Kupfer-Verbindungsmetallisierung 132 für ein ØB von angenähert 0.5 eV. Die Haltediode DO enthält ebenfalls eine Platin-Silicid-Schicht 115 und liefert ein ØB von angenähert 0.8 eV.Diodes D1, D3, D4 and D5 are Schottky junction diodes with a low potential threshold constructed according to the invention. They consist of N-conducting silicon 103, a tantalum layer 128, a chrome layer 130 and an aluminum-copper connection metallization 132 for a Ø B of approximately 0.5 eV. The holding diode DO also contains a platinum-silicide layer 115 and delivers a Ø B of approximately 0.8 eV.

Als Alternative zu dem bei der Herstellung des Metallisierungsmusters verwendeten Ablöseverfahrens kann auch subtraktives oder reaktives Ionen- (Plasma) oder chemisches Ätzen eingesetzt werden. Dieselben kritischen Verfahrensschritte der Vorreinigung, die Betriebsbedingungen der Vakuumkammer und der Sinterung müssen eingehalten werden. Wie bereits erwähnt,-sind diese Verfahren nicht so vorteilhaft wie das Ablöseverfahren.As an alternative to the stripping process used in the production of the metallization pattern, subtractive or reactive ion (plasma) or chemical etching can also be used. The same critical process steps of pre-cleaning, the operating conditions of the vacuum chamber and the sintering must be observed. As previously mentioned, these processes are not as advantageous as the peel process.

Bei jedem dieser Ätzverfahren werden alles überdeckende Schichten aus Tantal, Chrom und Kupfer dotiertem Aluminium oder Kupfer dotiertem Aluminium-Silicium in den öffnungen 11, 12, 13 und 14 in Fig. 1 niedergeschlagen. Ein positives Muster wird durch einen positiven Photolack definiert, wie er beispielsweise unter den Bezeichnungen AZ1350 oder AZ111 durch die Firma Shipley auf den Markt gebracht wird.In each of these etching processes, all covering layers of tantalum, chromium and copper-doped aluminum or copper-doped aluminum-silicon are deposited in the openings 11, 12, 13 and 14 in FIG. 1. A positive pattern is defined by a positive photoresist, as it is marketed for example by Shipley under the names AZ1350 or AZ111.

Die nun freiliegenden, nicht benötigten Metallschichten werden durch übliche, nasse Ätzverfahren für Metalle in einem subtraktiven Verfahren oder dadurch entfernt, daß man das Substrat in eine Plasma-Ätzkammer einbringt, das für ein Plasma-Ätzverfahren eine Gasmischung aus CCl4-Ar enthält.The now exposed, unnecessary metal layers are removed by conventional wet etching processes for metals in a subtractive process or by placing the substrate in a plasma etching chamber which contains a gas mixture of CCl 4 -Ar for a plasma etching process.

Bei dem chemischen Ätzverfahren wird das freiliegende Aluminium durch eine Mischung aus H3PO4-HNO3-H2O ent- fernt. Die freiliegende Chrom-Oberfläche wird durch eine Mischung aus 50 Gramm KMnO4 und einem Liter eines Entwicklers mit der Typenbezeichnung AZ1350 entfernt. Dann wird das Tantal durch Zerstäubungsätzen entfernt, wobei die restliche Aluminium-Schicht als Maske dient. Ist die Breite der Metallisierungs-Leitungszüge des Musters größer als 0.0127 mm, dann kann das Tantal durch eine Mischung aus einem Teil HF, 20 Teilen HN03 und 20 Teilen H20 entfernt werden.In the chemical etching process, this becomes exposed Remove aluminum with a mixture of H 3 PO 4 -HNO 3 -H 2 O. The exposed chrome surface is removed by a mixture of 50 grams of KMnO 4 and one liter of a developer with the type designation A Z1350. The tantalum is then removed by sputter etching, with the remaining aluminum layer serving as a mask. If the width of the metallization lines of the pattern is greater than 0.0127 mm, the tantalum can be removed by a mixture of one part HF, 20 parts HN0 3 and 20 parts H 2 0.

Die Erfindung wurde zwar in Verbindung mit einer integrierten Schaltung beschrieben, bei der ohmsche Kontakte und Schottky-Sperrschichtkontakte mit hoher und niedriger Potentialschwelle hergestellt werden, es ist dabei jedoch nicht erforderlich, daß alle solche Kontakte gemäß der Erfindung hergestellt sein müssen.Although the invention has been described in connection with an integrated circuit in which ohmic contacts and Schottky junction contacts are produced with high and low potential thresholds, it is not necessary that all such contacts have to be made according to the invention.

Claims (18)

1. Verfahren zum Herstellen eines Tantal-Kontaktes auf einem aus Silicium bestehenden Halbleitersubstrat, gekennzeichnet durch folgenden Verfahrensablauf: Vorbereiten mindestens eines Teils der Substratoberfläche zur Verhinderung der Bildung von amorphem Silicium, Niederschlagen von Tantal auf diesem Teil der Oberfläche des Substrats in einer Vakuumkammer bei niedrigem Druck und niedriger Substrattemperatur zur Vermeidung einer Oxidation des Tantals und Sintern des Substrats über eine solche Zeit und bei einer solchen Temperatur, daß dabei die zwischen der Substratoberfläche und der Tantalschicht vorhandenen Grenzflächenladungen und Filme entfernt werden. 1. A method for producing a tantalum contact on a semiconductor substrate consisting of silicon, characterized by the following procedure: preparing at least a part of the substrate surface to prevent the formation of amorphous silicon, Precipitation of tantalum on this part of the surface of the substrate in a vacuum chamber at low pressure and low substrate temperature to avoid oxidation of the tantalum and Sintering the substrate for a time and at a temperature such that the interface charges and films present between the substrate surface and the tantalum layer are removed. 2. Verfahren nach Anspruch 1,
gekennzeichnet durch die Verwendung eines N-leitenden Substrats zur Bildung eines eine Schottky-Sperrschicht-Diode mit niedriger Potentialschwelle darstellenden Kontakts.2. The method according to claim 1,
characterized by the use of an N-type substrate to form a contact representing a Schottky junction diode with a low potential threshold. 3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß auf dem Teil der Oberfläche des Substrats vor dem Niederschlagen von Tantal ein metallisches Silicid gebildet wird.3. The method according to claim 1, characterized in that a metallic silicide is formed on the part of the surface of the substrate before tantalum is deposited. 4. Verfahren nach Anspruch 3, gekennzeichnet durch Verwendung eines N-leitenden Substrats zur Bildung eines ohmschen Kontaktes.4. The method according to claim 3, characterized by using an N-type substrate to form an ohmic contact. 5. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Tantal mittels Elektronenstrahl-Verdampfung bei einem Druck von nicht mehr als 2.5 x 10-6 TORR und einer Temperatur von nicht mehr als 200°C niedergeschlagen wird (1 TORR = 1.333224 mbar).5. The method according to claim 1, characterized in that the tantalum is deposited by means of electron beam evaporation at a pressure of not more than 2.5 x 10 -6 TORR and a temperature of not more than 200 ° C (1 TORR = 1.333224 mbar). 6. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Tantal mittel HF-Kathodenzerstäubung bei einem Anfangsdruck von nicht mehr als 4 x 10-7 TORR niedergeschlagen wird.6. The method according to claim 1, characterized in that the tantalum medium HF cathode sputtering is deposited at an initial pressure of not more than 4 x 10 -7 TORR. 7. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Tantal-Muster auf jenem Teil der Substratoberfläche durch ein Ablöseverfahren definiert wird und
daß das Tantal durch Elektronenstrahl-Verdampfung niedergeschlagen wird.7. The method according to claim 1, characterized in that the tantalum pattern is defined on that part of the substrate surface by a release process and
that the tantalum is deposited by electron beam evaporation. 8. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß zur Vorbereitung der Oberfläche des Siliciumsubstrats diese Oberfläche mit einer verdünnten HF-Ätzlösung unter solchen Bedingungen gereinigt wird, daß dabei kein Licht einer Wellenlänge von weniger als 500 nm auftritt.8. The method according to claim 1, characterized in that to prepare the surface of the silicon substrate, this surface is cleaned with a dilute HF etching solution under such conditions that no light of a wavelength of less than 500 nm occurs. 9. Verfahren nach Anspruch 1, dadurch gekennzeichnet,
daß die Sinterung für eine Stunde bei 400°C und für weitere zwei Stunden bei 45°C durchgeführt wird.9. The method according to claim 1, characterized in
that the sintering is carried out at 400 ° C for one hour and at 45 ° C for a further two hours. 10. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß auf dem Tantal eine aus Chrom bestehende Schicht niedergeschlagen wird. 10th A method according to claim 1, characterized in that a layer consisting of chromium is deposited on the tantalum. 11. Verfahren nach Anspruch 10, dadurch gekennzeichnet, daß das Chrom in der Weise verdampft wird, daß das Chrom in den Tiegel einer Verdampfungskammer eingebracht, diese auf einen Druck von etwa 10-6 TORR ausgepumpt und während der Verdampfung des Chroms Wasserdampf in die Verdampfungskammer bis zu einem Druck von etwa 10-5 TORR eingeleitet wird, wodurch Chrom auf der Oberfläche des Tantals niedergeschlagen wird.11. The method according to claim 10, characterized in that the chromium is evaporated in such a way that the chromium is introduced into the crucible of an evaporation chamber, this is pumped out to a pressure of approximately 10 -6 TORR and water vapor is evaporated into the evaporation chamber during the evaporation of the chromium up to a pressure of about 10 -5 TORR is initiated, whereby chrome is deposited on the surface of the tantalum. 12. Verfahren nach Anspruch 11, dadurch gekennzeichnet, daß über dem Chrom eine Schicht aus Aluminium niedergeschlagen wird, wodurch das Chrom als Sperrschicht zwischen dem Tantal und dem Aluminium wirkt.12. The method according to claim 11, characterized in that a layer of aluminum is deposited over the chrome, whereby the chrome acts as a barrier layer between the tantalum and the aluminum. 13. Verfahren nach Anspruch 12, dadurch gekennzeichnet, daß das Tantal-Chrom-Aluminium-Muster auf jenem Teil der Substratoberfläche durch ein Ablöseverfahren definiert wird und
daß das Tantal und das Aluminium durch Elektronenstrahl-Verdampfung niedergeschlagen wird.13. The method according to claim 12, characterized in that the tantalum-chrome-aluminum pattern is defined on that part of the substrate surface by a detachment process and
that the tantalum and aluminum are deposited by electron beam evaporation. 14. Halbleiterkontakt hergestellt nach einem Verfahren gemäß Anspruch 1 mit einem aus Silicium bestehenden Halbleitersubstrat, dadurch gekennzeichnet,
daß auf dem Substrat ein Muster aus einer Tantal- Schicht, einer darüber liegenden Chromschicht und einer über dieser liegenden Aluminiumschicht niedergeschlagen ist.14. Semiconductor contact produced by a method according to claim 1 with a semiconductor substrate consisting of silicon, characterized in that
that a pattern of a tantalum layer, an overlying chrome layer and an overlying aluminum layer is deposited on the substrate. 15. Halbleiterkontakt nach Anspruch 14, dadurch gekennzeichnet,
daß zwischen der Tantal-Schicht und dem Substrat eine aus einem Metall-Silicid bestehende Schicht liegt, so daß damit ein ohmscher Kontakt gebildet ist.15. The semiconductor contact according to claim 14, characterized in that
that between the tantalum layer and the substrate is a layer consisting of a metal silicide, so that an ohmic contact is formed. 16. Halbleiterkontakt nach Anspruch 14, dadurch gekennzeichnet,
daß zwischen der Tantal-Schicht und dem Substrat eine aus einem Metall-Silicid bestehende Schicht liegt, so daß damit ein ohmscher Kontakt gebildet ist.16. The semiconductor contact according to claim 14, characterized in that
that between the tantalum layer and the substrate is a layer consisting of a metal silicide, so that an ohmic contact is formed. 17. Halbleiterkontakt nach Anspruch 16, dadurch ge- kennzeichnet,
daß die Dicke der Tantal-Schicht etwa 60 nm und die Dicke der Chromschicht etwa 80 nm beträgt.17. The semiconductor contact as claimed in claim 16, characterized in
that the thickness of the tantalum layer is about 60 nm and the thickness of the chrome layer is about 80 nm. 18. Halbleiterkontakt als Schottky-Sperrschicht-Diode mit einer Potentialschwelle von etwa 0.5 eV, dadurch gekennzeichnet, daß die Störelementkonzentration des N-leitenden Siliciumsubstrats etwa 1 x 10 16 bis 8 x 10 16 Atome/ cm3 beträgt und daß über dem Substrat eine Schicht aus Tantal, darüber eine Schicht aus Chrom und darüber eine Schicht aus Aluminium liegt. 18. Semiconductor contact as a Schottky junction diode with a potential threshold of approximately 0.5 eV, characterized in that that the Störelementkonzentration of the N-type silicon substrate is about 1 m x 1 is 0 16 to 8 × 1 0 16 atoms / c 3 and that there is a layer of tantalum over the substrate, a layer of chrome over it and a layer of aluminum over it.
EP78100525A 1977-08-06 1978-07-27 Method for fabricating tantalum contacts on a n-type conducting silicon semiconductor substrate Expired EP0000743B1 (en)

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US05/827,912 US4215156A (en) 1977-08-26 1977-08-26 Method for fabricating tantalum semiconductor contacts

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0017021A1 (en) * 1979-03-30 1980-10-15 International Business Machines Corporation Method of making a semiconductor device including complementary transistors
EP0100999A2 (en) * 1982-08-12 1984-02-22 Siemens Aktiengesellschaft Integrated semiconductor circuit comprising bipolar elements, and schottkydiodes so as method of producing the same
EP0194569A1 (en) * 1985-03-13 1986-09-17 Siemens Aktiengesellschaft Thin-film layer structure with a reactive intermediate layer for integrated circuits
US6183685B1 (en) 1990-06-26 2001-02-06 Littlefuse Inc. Varistor manufacturing method

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4307132A (en) * 1977-12-27 1981-12-22 International Business Machines Corp. Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer
US4412376A (en) * 1979-03-30 1983-11-01 Ibm Corporation Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation
CA1138795A (en) * 1980-02-19 1983-01-04 Goodrich (B.F.) Company (The) Escape slide and life raft
US4379832A (en) * 1981-08-31 1983-04-12 International Business Machines Corporation Method for making low barrier Schottky devices of the electron beam evaporation of reactive metals
JPS59175763A (en) * 1983-03-25 1984-10-04 Fujitsu Ltd Semiconductor device
JPS6113779U (en) * 1984-06-29 1986-01-27 有限会社 東京巧作所 Magnetic catcher for opening and closing doors
JPH0315737Y2 (en) * 1984-10-30 1991-04-05
JPS6143360U (en) * 1984-08-24 1986-03-20 有限会社 東京巧作所 Magnetic catcher for opening and closing doors
JPS6116568A (en) * 1984-07-03 1986-01-24 Matsushita Electronics Corp Schottky barrier type semiconductor device
EP0252667B1 (en) * 1986-06-30 1996-03-27 Nihon Sinku Gijutsu Kabushiki Kaisha Chemical vapour deposition methods
US4994301A (en) * 1986-06-30 1991-02-19 Nihon Sinku Gijutsu Kabusiki Kaisha ACVD (chemical vapor deposition) method for selectively depositing metal on a substrate
JP2620240B2 (en) * 1987-06-10 1997-06-11 株式会社日立製作所 Liquid crystal display
US5155565A (en) * 1988-02-05 1992-10-13 Minnesota Mining And Manufacturing Company Method for manufacturing an amorphous silicon thin film solar cell and Schottky diode on a common substrate
US5116464A (en) * 1989-06-02 1992-05-26 Massachusetts Institute Of Technology Cesium hydroxide etch of a semiconductor crystal
US5402254B1 (en) * 1990-10-17 1998-09-22 Hitachi Ltd Liquid crystal display device with tfts in which pixel electrodes are formed in the same plane as the gate electrodes with anodized oxide films before the deposition of silicon
US5221638A (en) * 1991-09-10 1993-06-22 Sanken Electric Co., Ltd. Method of manufacturing a Schottky barrier semiconductor device
US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
JP3562588B2 (en) * 1993-02-15 2004-09-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6326601B1 (en) * 1999-07-19 2001-12-04 Agilent Technologies, Inc. Optical barrier
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
DE10011886A1 (en) * 2000-03-07 2001-09-20 Infineon Technologies Ag Method for producing a conductor structure for an integrated circuit
US6271068B1 (en) * 2001-01-08 2001-08-07 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon emitters for bipolar transistors on BiCMOS integrated circuits
US6852167B2 (en) 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US6844203B2 (en) * 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US6900122B2 (en) * 2001-12-20 2005-05-31 Micron Technology, Inc. Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
US6953730B2 (en) * 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US6767795B2 (en) * 2002-01-17 2004-07-27 Micron Technology, Inc. Highly reliable amorphous high-k gate dielectric ZrOXNY
US6812100B2 (en) * 2002-03-13 2004-11-02 Micron Technology, Inc. Evaporation of Y-Si-O films for medium-k dielectrics
US7589029B2 (en) 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7045430B2 (en) 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7135421B2 (en) 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US6804136B2 (en) * 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
US7193893B2 (en) 2002-06-21 2007-03-20 Micron Technology, Inc. Write once read only memory employing floating gates
US7221017B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6790791B2 (en) 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US6884739B2 (en) * 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US20040036129A1 (en) * 2002-08-22 2004-02-26 Micron Technology, Inc. Atomic layer deposition of CMOS gates with variable work functions
US6967154B2 (en) * 2002-08-26 2005-11-22 Micron Technology, Inc. Enhanced atomic layer deposition
US7199023B2 (en) 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US6958302B2 (en) 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
US6955932B2 (en) * 2003-10-29 2005-10-18 International Business Machines Corporation Single and double-gate pseudo-FET devices for semiconductor materials evaluation
US20050233477A1 (en) * 2004-03-05 2005-10-20 Tokyo Electron Limited Substrate processing apparatus, substrate processing method, and program for implementing the method
US7498247B2 (en) 2005-02-23 2009-03-03 Micron Technology, Inc. Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US20070013014A1 (en) * 2005-05-03 2007-01-18 Shuwen Guo High temperature resistant solid state pressure sensor
US7628309B1 (en) * 2005-05-03 2009-12-08 Rosemount Aerospace Inc. Transient liquid phase eutectic bonding
US7400042B2 (en) * 2005-05-03 2008-07-15 Rosemount Aerospace Inc. Substrate with adhesive bonding metallization with diffusion barrier
US7538401B2 (en) * 2005-05-03 2009-05-26 Rosemount Aerospace Inc. Transducer for use in harsh environments
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
EP1949437B2 (en) * 2005-11-02 2021-08-04 Second Sight Medical Products, Inc. Implantable microelectronic device and method of manufacture
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2029236A1 (en) * 1969-06-20 1971-01-07 Texas Instruments Ine , Dallas, Tex (V St A) Av alanche diode with a Schottky barrier layer and process for its manufacture
DE2104672A1 (en) * 1970-02-02 1971-08-19 Ibm Planar semiconductor device, in particular special integrated semiconductor circuit, with metallic connecting conductor strips built into the semiconductor body or the semiconductor substrate
US3662458A (en) * 1969-06-20 1972-05-16 Westinghouse Electric Corp Electrical contact for silicon carbide members
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
US3906540A (en) * 1973-04-02 1975-09-16 Nat Semiconductor Corp Metal-silicide Schottky diode employing an aluminum connector
FR2324124A1 (en) * 1975-09-09 1977-04-08 Philips Nv PROCESS FOR THE REALIZATION OF A CHARGE TRANSMISSION DEVICE AND CHARGING DEVICE THUS REALIZED

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3442012A (en) * 1967-08-03 1969-05-06 Teledyne Inc Method of forming a flip-chip integrated circuit
US3567508A (en) * 1968-10-31 1971-03-02 Gen Electric Low temperature-high vacuum contact formation process
US3820236A (en) * 1969-06-20 1974-06-28 Texas Instruments Inc Method of making metal semiconductor diodes having plated heat sink members
US3663279A (en) * 1969-11-19 1972-05-16 Bell Telephone Labor Inc Passivated semiconductor devices
US3641402A (en) * 1969-12-30 1972-02-08 Ibm Semiconductor device with beta tantalum-gold composite conductor metallurgy
US3967371A (en) * 1970-01-06 1976-07-06 Sescosem- Societe Europeenne Des Semi-Conducteurs Et De Microelectronique Methods of manufacturing multilayer interconnections for integrated circuits and to integrated circuits utilizing said method
US3652905A (en) * 1970-05-26 1972-03-28 Westinghouse Electric Corp Schottky barrier power rectifier
DE2057204C3 (en) * 1970-11-20 1975-02-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen Process for the production of metal-semiconductor contacts
JPS557020B2 (en) * 1971-11-15 1980-02-21
US3939047A (en) * 1971-11-15 1976-02-17 Nippon Electric Co., Ltd. Method for fabricating electrode structure for a semiconductor device having a shallow junction
NL163370C (en) * 1972-04-28 1980-08-15 Philips Nv METHOD FOR MANUFACTURING A SEMI-CONDUCTOR DEVICE WITH A CONDUCTOR PATTERN
US3923975A (en) * 1973-10-09 1975-12-02 Cutler Hammer Inc Tantalum-gallium arsenide schottky barrier semiconductor device
US4035208A (en) * 1974-09-03 1977-07-12 Texas Instruments Incorporated Method of patterning Cr-Pt-Au metallization for silicon devices
JPS5136878A (en) * 1974-09-14 1976-03-27 Tokyo Shibaura Electric Co Handotaisochi no seizohoho

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2029236A1 (en) * 1969-06-20 1971-01-07 Texas Instruments Ine , Dallas, Tex (V St A) Av alanche diode with a Schottky barrier layer and process for its manufacture
US3662458A (en) * 1969-06-20 1972-05-16 Westinghouse Electric Corp Electrical contact for silicon carbide members
DE2104672A1 (en) * 1970-02-02 1971-08-19 Ibm Planar semiconductor device, in particular special integrated semiconductor circuit, with metallic connecting conductor strips built into the semiconductor body or the semiconductor substrate
US3906540A (en) * 1973-04-02 1975-09-16 Nat Semiconductor Corp Metal-silicide Schottky diode employing an aluminum connector
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
FR2324124A1 (en) * 1975-09-09 1977-04-08 Philips Nv PROCESS FOR THE REALIZATION OF A CHARGE TRANSMISSION DEVICE AND CHARGING DEVICE THUS REALIZED

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 14, April 1972, New York: M. REVITZ et al: "Metallurgy barrier for Au and Pb", Seite 3358 *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, April 1974, New York: T.M. REITH et al.: "Al/Pt Si Schottky Barrier Diodes with a diffusion Barrier", Seite 3586 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0017021A1 (en) * 1979-03-30 1980-10-15 International Business Machines Corporation Method of making a semiconductor device including complementary transistors
EP0100999A2 (en) * 1982-08-12 1984-02-22 Siemens Aktiengesellschaft Integrated semiconductor circuit comprising bipolar elements, and schottkydiodes so as method of producing the same
EP0100999A3 (en) * 1982-08-12 1986-05-14 Siemens Aktiengesellschaft Integrated semiconductor circuit comprising bipolar elements, and method of producing the same
EP0194569A1 (en) * 1985-03-13 1986-09-17 Siemens Aktiengesellschaft Thin-film layer structure with a reactive intermediate layer for integrated circuits
US6183685B1 (en) 1990-06-26 2001-02-06 Littlefuse Inc. Varistor manufacturing method

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IT7826099A0 (en) 1978-07-26
JPS5436178A (en) 1979-03-16
IT1158954B (en) 1987-02-25
DE2860169D1 (en) 1980-12-18
JPS5932069B2 (en) 1984-08-06
EP0000743B1 (en) 1980-09-17
US4215156A (en) 1980-07-29
CA1111570A (en) 1981-10-27

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