DE69932665D1 - Verfahren zur Herstellung einer Verbindungsstruktur - Google Patents

Verfahren zur Herstellung einer Verbindungsstruktur

Info

Publication number
DE69932665D1
DE69932665D1 DE69932665T DE69932665T DE69932665D1 DE 69932665 D1 DE69932665 D1 DE 69932665D1 DE 69932665 T DE69932665 T DE 69932665T DE 69932665 T DE69932665 T DE 69932665T DE 69932665 D1 DE69932665 D1 DE 69932665D1
Authority
DE
Germany
Prior art keywords
producing
connection structure
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69932665T
Other languages
English (en)
Other versions
DE69932665T2 (de
Inventor
Nobuo Aoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=13688026&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69932665(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69932665D1 publication Critical patent/DE69932665D1/de
Publication of DE69932665T2 publication Critical patent/DE69932665T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69932665T 1998-03-26 1999-03-24 Verfahren zur Herstellung einer Verbindungsstruktur Expired - Lifetime DE69932665T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7937198 1998-03-26
JP7937198 1998-03-26

Publications (2)

Publication Number Publication Date
DE69932665D1 true DE69932665D1 (de) 2006-09-21
DE69932665T2 DE69932665T2 (de) 2006-12-14

Family

ID=13688026

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69932665T Expired - Lifetime DE69932665T2 (de) 1998-03-26 1999-03-24 Verfahren zur Herstellung einer Verbindungsstruktur

Country Status (3)

Country Link
US (2) US6197696B1 (de)
EP (1) EP0945900B1 (de)
DE (1) DE69932665T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197696B1 (en) * 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
TW437040B (en) * 1998-08-12 2001-05-28 Applied Materials Inc Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6071809A (en) * 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
JP3888794B2 (ja) * 1999-01-27 2007-03-07 松下電器産業株式会社 多孔質膜の形成方法、配線構造体及びその形成方法
TW444252B (en) * 1999-03-19 2001-07-01 Toshiba Corp Semiconductor apparatus and its fabricating method
US6461955B1 (en) * 1999-04-29 2002-10-08 Texas Instruments Incorporated Yield improvement of dual damascene fabrication through oxide filling
US6329280B1 (en) * 1999-05-13 2001-12-11 International Business Machines Corporation Interim oxidation of silsesquioxane dielectric for dual damascene process
JP4094174B2 (ja) 1999-06-04 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
CN1192427C (zh) 1999-08-25 2005-03-09 因芬尼昂技术股份公司 制造具有至少一个金属化平面的集成电路的方法
JP3348706B2 (ja) * 1999-09-29 2002-11-20 日本電気株式会社 半導体装置の製造方法
JP2001102447A (ja) * 1999-09-30 2001-04-13 Mitsubishi Electric Corp コンタクト構造の製造方法
US6329281B1 (en) * 1999-12-03 2001-12-11 Agere Systems Guardian Corp. Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer
WO2001084626A1 (en) * 2000-04-28 2001-11-08 Tokyo Electron Limited Semiconductor device having a low dielectric film and fabrication process thereof
EP1292978A2 (de) * 2000-06-21 2003-03-19 Infineon Technologies North America Corp. Doppeldamaszen-verfahren in einem doppeldielektrikum mit niedriger dielektrizitätskonstante
JP4659329B2 (ja) * 2000-06-26 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6472332B1 (en) * 2000-11-28 2002-10-29 Xerox Corporation Surface micromachined structure fabrication methods for a fluid ejection device
US6677680B2 (en) * 2001-02-28 2004-01-13 International Business Machines Corporation Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
TW544855B (en) * 2001-06-25 2003-08-01 Nec Electronics Corp Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer
US6992391B2 (en) * 2001-09-28 2006-01-31 Intel Corporation Dual-damascene interconnects without an etch stop layer by alternating ILDs
JP2004186439A (ja) * 2002-12-03 2004-07-02 Sanken Electric Co Ltd 半導体装置およびその製造方法
US7147767B2 (en) * 2002-12-16 2006-12-12 3M Innovative Properties Company Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor
US6884338B2 (en) * 2002-12-16 2005-04-26 3M Innovative Properties Company Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
US6858124B2 (en) * 2002-12-16 2005-02-22 3M Innovative Properties Company Methods for polishing and/or cleaning copper interconnects and/or film and compositions therefor
JP3715626B2 (ja) * 2003-01-17 2005-11-09 株式会社東芝 半導体装置の製造方法および半導体装置
US20050082089A1 (en) * 2003-10-18 2005-04-21 Stephan Grunow Stacked interconnect structure between copper lines of a semiconductor circuit
JP2006130868A (ja) * 2004-11-09 2006-05-25 Canon Inc インクジェット記録ヘッド及びその製造方法
KR100641553B1 (ko) * 2004-12-23 2006-11-01 동부일렉트로닉스 주식회사 반도체 소자에서 패턴 형성 방법
US7531448B2 (en) * 2005-06-22 2009-05-12 United Microelectronics Corp. Manufacturing method of dual damascene structure
DE102006048740A1 (de) * 2006-10-12 2008-04-17 Henkel Kgaa Tönungsschaum
KR102068677B1 (ko) 2013-04-10 2020-01-22 삼성전자 주식회사 반도체 소자 제조 방법
US20140342553A1 (en) * 2013-05-14 2014-11-20 United Microelectronics Corp. Method for Forming Semiconductor Structure Having Opening
CN105789111B (zh) * 2014-12-18 2019-03-12 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5110712A (en) 1987-06-12 1992-05-05 Hewlett-Packard Company Incorporation of dielectric layers in a semiconductor
EP0425787A3 (en) 1989-10-31 1993-04-14 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal lines to contact windows
US5651855A (en) 1992-07-28 1997-07-29 Micron Technology, Inc. Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits
JPH06291193A (ja) 1993-04-02 1994-10-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2773613B2 (ja) 1993-11-30 1998-07-09 日本電気株式会社 半導体装置の製造方法
JPH08139194A (ja) 1994-04-28 1996-05-31 Texas Instr Inc <Ti> 半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス
KR970007174B1 (ko) * 1994-07-07 1997-05-03 현대전자산업 주식회사 반도체 소자의 금속배선 형성방법
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
JPH0964034A (ja) 1995-08-18 1997-03-07 Toshiba Corp 半導体装置およびその製造方法
JPH09153545A (ja) 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
US6107191A (en) * 1997-11-07 2000-08-22 Lucent Technologies Inc. Method of creating an interconnect in a substrate and semiconductor device employing the same
TW368741B (en) * 1998-02-26 1999-09-01 United Microelectronics Corp Manufacturing method for dual damascene
US6197696B1 (en) * 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
US6083822A (en) * 1999-08-12 2000-07-04 Industrial Technology Research Institute Fabrication process for copper structures

Also Published As

Publication number Publication date
US6197696B1 (en) 2001-03-06
DE69932665T2 (de) 2006-12-14
US20010001739A1 (en) 2001-05-24
EP0945900A1 (de) 1999-09-29
EP0945900B1 (de) 2006-08-09
US6287973B2 (en) 2001-09-11

Similar Documents

Publication Publication Date Title
DE69932665D1 (de) Verfahren zur Herstellung einer Verbindungsstruktur
DE69906491D1 (de) VERFAHREN ZUR HERSTELLUNG EINER SiCOI-STRUKTUR
ATE259315T1 (de) Verfahren zur herstellung einer stossanfängeranordnung
DE69730940D1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE69826934D1 (de) Verfahren zur Herstellung einer Doppel-Damaszener Struktur
DE69823027D1 (de) Verfahren zur herstellung einer waschmittelzusammensetzung
DE69935810D1 (de) Verfahren zur herstellung einer laminierten struktur
DE60030949D1 (de) Verfahren zur herstellung einer karte
DE69619691D1 (de) Verfahren zur herstellung einer beugungsstruktur
ATA186898A (de) Verfahren zur herstellung einer cellulosecarbamatlösung
DE69840399D1 (de) Verfahren zur Herstellung einer Gate-Elektrode
DE69801560D1 (de) Verfahren zur herstellung einer katalysatorzusammenstellung
DE60031761D1 (de) Verfahren zur herstellung einer harzzusammensetzung
DE59914827D1 (de) Verfahren zur herstellung einer bond-draht-verbindung
DE69701890D1 (de) Verfahren zur herstellung einer abbindenden zusammensetzung
DE69940737D1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE69607546D1 (de) Verfahren zur Herstellung einer Schaltungsanordnung
ATE205201T1 (de) Verfahren zur herstellung einer benzimidazolverbindung
DE69701731D1 (de) Verfahren zur herstellung einer waschmittelzusammensetzung
DE69934680D1 (de) Verfahren zur herstellung einer schicht
DE69827966D1 (de) Verfahren zur herstellung einer querfaserbahn
DE69840320D1 (de) Verfahren zur Herstellung einer Gateelektrode
DE60032660D1 (de) Verfahren zur Herstellung einer planaren Heterostruktur
DE69942186D1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE69707359D1 (de) Verfahren zur Herstellung einer keramischen Membranstruktur

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP