DE69831918D1 - Speicherschaltung mit DMA Prüfung und sein Prüfverfahren - Google Patents

Speicherschaltung mit DMA Prüfung und sein Prüfverfahren

Info

Publication number
DE69831918D1
DE69831918D1 DE69831918T DE69831918T DE69831918D1 DE 69831918 D1 DE69831918 D1 DE 69831918D1 DE 69831918 T DE69831918 T DE 69831918T DE 69831918 T DE69831918 T DE 69831918T DE 69831918 D1 DE69831918 D1 DE 69831918D1
Authority
DE
Germany
Prior art keywords
pipe line
data
output
test
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69831918T
Other languages
English (en)
Other versions
DE69831918T2 (de
Inventor
Joon-Wan Chai
Kye-Hyun Kyung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE69831918D1 publication Critical patent/DE69831918D1/de
Publication of DE69831918T2 publication Critical patent/DE69831918T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69831918T 1997-12-03 1998-05-12 Speicherschaltung mit DMA Prüfung und sein Prüfverfahren Expired - Lifetime DE69831918T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR9765539 1997-12-03
KR1019970065539A KR100238256B1 (ko) 1997-12-03 1997-12-03 직접 억세스 모드 테스트를 사용하는 메모리 장치 및 테스트방법

Publications (2)

Publication Number Publication Date
DE69831918D1 true DE69831918D1 (de) 2005-11-24
DE69831918T2 DE69831918T2 (de) 2006-07-20

Family

ID=36643425

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831918T Expired - Lifetime DE69831918T2 (de) 1997-12-03 1998-05-12 Speicherschaltung mit DMA Prüfung und sein Prüfverfahren

Country Status (6)

Country Link
US (1) US6046947A (de)
EP (1) EP0921528B1 (de)
JP (1) JP3822367B2 (de)
KR (1) KR100238256B1 (de)
DE (1) DE69831918T2 (de)
TW (1) TW396344B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7643354B2 (en) * 1999-07-30 2010-01-05 University Of Kentucky Research Foundation Neural network model for instruments that store and retrieve sequential information
JP2001043700A (ja) * 1999-08-02 2001-02-16 Fujitsu Ltd 半導体記憶装置
DE10064478B4 (de) * 2000-12-22 2005-02-24 Atmel Germany Gmbh Verfahren zur Prüfung einer integrierten Schaltung und Schaltungsanordnung
DE10136703C1 (de) * 2001-07-27 2003-04-17 Infineon Technologies Ag Logikvorrichtung zum Testen einer integrierten Schaltung
KR100406543B1 (ko) 2001-12-24 2003-11-20 주식회사 하이닉스반도체 동기식 메모리의 파이프 래치 제어회로
US20030182609A1 (en) * 2002-01-31 2003-09-25 Shirish Agrawal Pass gate multiplexer
US7010733B2 (en) * 2002-10-09 2006-03-07 International Business Machines Corporation Parametric testing for high pin count ASIC
US7372752B2 (en) * 2005-09-29 2008-05-13 Hynix Semiconductor Inc. Test mode controller
CN101226777B (zh) * 2007-01-15 2011-10-26 华邦电子股份有限公司 存储装置和减少测试针脚装置及其测试方法
JP2008311164A (ja) * 2007-06-18 2008-12-25 Panasonic Corp 非水電解質二次電池および非水電解質二次電池用電極の製造方法
JP2010003388A (ja) * 2008-06-23 2010-01-07 Elpida Memory Inc 半導体記憶装置およびそのテスト方法
KR102076858B1 (ko) * 2013-12-24 2020-02-12 에스케이하이닉스 주식회사 반도체장치 및 이를 포함하는 반도체시스템
US10643735B1 (en) * 2017-10-27 2020-05-05 Pdf Solutions, Inc. Passive array test structure for cross-point memory characterization
CN114460447B (zh) * 2021-01-19 2023-03-28 沐曦集成电路(上海)有限公司 锁存器的自测试电路及其自测试方法
US11526453B1 (en) * 2021-08-13 2022-12-13 Micron Technology, Inc. Apparatus including parallel pipelines and methods of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254940A (en) * 1990-12-13 1993-10-19 Lsi Logic Corporation Testable embedded microprocessor and method of testing same
GR920100088A (el) * 1992-03-05 1993-11-30 Consulting R & D Corp Koloni S Διαφανής έλεγχος ολοκληρωμένων κυκλωμάτων.
JP2845713B2 (ja) * 1993-03-12 1999-01-13 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
JP3076185B2 (ja) * 1993-12-07 2000-08-14 日本電気株式会社 半導体メモリ装置及びその検査方法
US5506499A (en) * 1995-06-05 1996-04-09 Neomagic Corp. Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad
US5574692A (en) * 1995-06-07 1996-11-12 Lsi Logic Corporation Memory testing apparatus for microelectronic integrated circuit
JP2833563B2 (ja) * 1996-01-23 1998-12-09 日本電気株式会社 半導体記憶装置
JPH09213072A (ja) * 1996-02-09 1997-08-15 Nec Corp Ｄｒａｍリフレッシュ制御方式
US5668815A (en) * 1996-08-14 1997-09-16 Advanced Micro Devices, Inc. Method for testing integrated memory using an integrated DMA controller
US5877987A (en) * 1997-02-14 1999-03-02 Micron Technology, Inc. Method and circuit for self-latching data read lines in the data output path of a semiconductor memory device

Also Published As

Publication number Publication date
DE69831918T2 (de) 2006-07-20
KR19990047220A (ko) 1999-07-05
JPH11176199A (ja) 1999-07-02
JP3822367B2 (ja) 2006-09-20
KR100238256B1 (ko) 2000-01-15
EP0921528A1 (de) 1999-06-09
EP0921528B1 (de) 2005-10-19
TW396344B (en) 2000-07-01
US6046947A (en) 2000-04-04

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Legal Events

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