DE69830867D1 - Halbleiteranordnung mit einer leitenden Schutzschicht - Google Patents

Halbleiteranordnung mit einer leitenden Schutzschicht

Info

Publication number
DE69830867D1
DE69830867D1 DE69830867T DE69830867T DE69830867D1 DE 69830867 D1 DE69830867 D1 DE 69830867D1 DE 69830867 T DE69830867 T DE 69830867T DE 69830867 T DE69830867 T DE 69830867T DE 69830867 D1 DE69830867 D1 DE 69830867D1
Authority
DE
Germany
Prior art keywords
semiconductor device
protective layer
conductive protective
conductive
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69830867T
Other languages
English (en)
Other versions
DE69830867T2 (de
Inventor
Kazuyuki Kusaba
Makoto Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69830867D1 publication Critical patent/DE69830867D1/de
Publication of DE69830867T2 publication Critical patent/DE69830867T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69830867T 1997-04-22 1998-04-22 Halbleiteranordnung mit einer leitenden Schutzschicht Expired - Fee Related DE69830867T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9104531A JP3037191B2 (ja) 1997-04-22 1997-04-22 半導体装置
JP10453197 1997-04-22

Publications (2)

Publication Number Publication Date
DE69830867D1 true DE69830867D1 (de) 2005-08-25
DE69830867T2 DE69830867T2 (de) 2006-04-20

Family

ID=14383084

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69830867T Expired - Fee Related DE69830867T2 (de) 1997-04-22 1998-04-22 Halbleiteranordnung mit einer leitenden Schutzschicht

Country Status (6)

Country Link
US (1) US5986284A (de)
EP (1) EP0874401B1 (de)
JP (1) JP3037191B2 (de)
KR (1) KR100281206B1 (de)
CN (1) CN1157787C (de)
DE (1) DE69830867T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879340B1 (en) * 1998-08-19 2005-04-12 Micron Technology Inc. CMOS imager with integrated non-volatile memory
US6289455B1 (en) * 1999-09-02 2001-09-11 Crypotography Research, Inc. Method and apparatus for preventing piracy of digital content
FR2801999A1 (fr) * 1999-12-01 2001-06-08 Gemplus Card Int Procede de protection physique de puces electroniques et dispositifs electroniques ainsi proteges
JP4212255B2 (ja) * 2001-03-30 2009-01-21 株式会社東芝 半導体パッケージ
DE10140045B4 (de) 2001-08-16 2006-05-04 Infineon Technologies Ag IC-Chip mit Schutzstruktur
US7525330B2 (en) * 2001-11-28 2009-04-28 Nxp, B.V. Semiconductor device, card, system, and methods of initializing and checking the authenticity and the identity of the semiconductor device
US6940111B2 (en) * 2002-11-29 2005-09-06 Infineon Technologies Aktiengesellschaft Radiation protection in integrated circuits
CN100365786C (zh) * 2002-12-31 2008-01-30 上海贝岭股份有限公司 双极集成电路中硅材料质量的检测方法
JP2004221234A (ja) * 2003-01-14 2004-08-05 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6998654B2 (en) * 2003-02-04 2006-02-14 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device
JP4748929B2 (ja) * 2003-08-28 2011-08-17 パナソニック株式会社 保護回路および半導体装置
JP4758621B2 (ja) * 2003-08-28 2011-08-31 パナソニック株式会社 基本セル、端部セル、配線形状、配線方法、シールド線の配線構造
FR2864667B1 (fr) 2003-12-29 2006-02-24 Commissariat Energie Atomique Protection d'une puce de circuit integre contenant des donnees confidentielles
JP3956143B2 (ja) 2004-09-10 2007-08-08 セイコーエプソン株式会社 半導体装置
JP2006228910A (ja) * 2005-02-16 2006-08-31 Matsushita Electric Ind Co Ltd 半導体装置
CN202855734U (zh) * 2012-10-23 2013-04-03 北京同方微电子有限公司 用于智能卡的有源防护装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856355A (ja) * 1981-09-30 1983-04-04 Hitachi Ltd 半導体集積回路装置
US4519050A (en) * 1982-06-17 1985-05-21 Intel Corporation Radiation shield for an integrated circuit memory with redundant elements
JPS62143476A (ja) * 1985-12-18 1987-06-26 Fujitsu Ltd 半導体記憶装置
JPH0691176B2 (ja) * 1989-12-07 1994-11-14 株式会社東芝 大電力用半導体装置
JPH0538915A (ja) * 1991-02-13 1993-02-19 Atsugi Unisia Corp 電磁サスペンシヨン装置
US5818095A (en) * 1992-08-11 1998-10-06 Texas Instruments Incorporated High-yield spatial light modulator with light blocking layer
DE4434894C2 (de) * 1994-09-29 1998-07-02 Siemens Ag Leistungshalbleiterbauelement mit monolithisch integrierter Sensoranordnung sowie seine Herstellung und Verwendung
US5889410A (en) * 1996-05-22 1999-03-30 International Business Machines Corporation Floating gate interlevel defect monitor and method
KR100227625B1 (ko) * 1996-11-04 1999-11-01 김영환 반도체 소자의 테스트 패턴 제조방법

Also Published As

Publication number Publication date
KR19980081584A (ko) 1998-11-25
DE69830867T2 (de) 2006-04-20
EP0874401B1 (de) 2005-07-20
CN1157787C (zh) 2004-07-14
JP3037191B2 (ja) 2000-04-24
US5986284A (en) 1999-11-16
CN1201259A (zh) 1998-12-09
JPH10294444A (ja) 1998-11-04
KR100281206B1 (ko) 2001-02-01
EP0874401A3 (de) 1999-10-27
EP0874401A2 (de) 1998-10-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee