DE69811760D1 - Prüfbare Schaltung mit geringer Zahl von Anschlüssen - Google Patents

Prüfbare Schaltung mit geringer Zahl von Anschlüssen

Info

Publication number
DE69811760D1
DE69811760D1 DE69811760T DE69811760T DE69811760D1 DE 69811760 D1 DE69811760 D1 DE 69811760D1 DE 69811760 T DE69811760 T DE 69811760T DE 69811760 T DE69811760 T DE 69811760T DE 69811760 D1 DE69811760 D1 DE 69811760D1
Authority
DE
Germany
Prior art keywords
connections
small number
testable circuit
testable
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69811760T
Other languages
English (en)
Other versions
DE69811760T2 (de
Inventor
Jacques Prunier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of DE69811760D1 publication Critical patent/DE69811760D1/de
Application granted granted Critical
Publication of DE69811760T2 publication Critical patent/DE69811760T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69811760T 1997-04-29 1998-04-28 Prüfbare Schaltung mit geringer Zahl von Anschlüssen Expired - Lifetime DE69811760T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9705592A FR2762683B1 (fr) 1997-04-29 1997-04-29 Circuit testable a faible nombre de broches
FR9705592 1997-04-29

Publications (2)

Publication Number Publication Date
DE69811760D1 true DE69811760D1 (de) 2003-04-10
DE69811760T2 DE69811760T2 (de) 2004-02-19

Family

ID=9506639

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69811760T Expired - Lifetime DE69811760T2 (de) 1997-04-29 1998-04-28 Prüfbare Schaltung mit geringer Zahl von Anschlüssen

Country Status (4)

Country Link
US (1) US6321354B1 (de)
EP (1) EP0875830B1 (de)
DE (1) DE69811760T2 (de)
FR (1) FR2762683B1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6363501B1 (en) * 1998-12-10 2002-03-26 Advanced Micro Devices, Inc. Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path
US6954879B1 (en) 1998-12-10 2005-10-11 Advanced Micro Devices, Inc. Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path
GB2370364B (en) * 2000-12-22 2004-06-30 Advanced Risc Mach Ltd Testing integrated circuits
US7216276B1 (en) 2003-02-27 2007-05-08 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US7444571B1 (en) 2003-02-27 2008-10-28 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US7496818B1 (en) 2003-02-27 2009-02-24 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US7596699B2 (en) * 2004-02-24 2009-09-29 Intersil Americas Inc. Battery authentication system
US7729427B2 (en) * 2004-02-24 2010-06-01 Intersil Americas Inc. Pseudo-synchronous one wire bidirectional bus interface
DE102004016387A1 (de) * 2004-04-02 2005-10-27 Texas Instruments Deutschland Gmbh Schnittstellenschaltung für einen einzelnen Logik-Eingangspin eines elektronischen Systems
US7493434B1 (en) * 2005-05-25 2009-02-17 Dafca, Inc. Determining the value of internal signals in a malfunctioning integrated circuit
JP2009505304A (ja) * 2005-08-22 2009-02-05 エヌエックスピー ビー ヴィ 埋設式メモリのアクセス制御
US7526693B1 (en) * 2006-03-09 2009-04-28 Semiconductor Components Industries, Llc Initial decision-point circuit operation mode
EP2608039B1 (de) * 2011-12-22 2014-05-21 Nxp B.V. Sichere Abtastung mit niedriger Pinzahl
US9759765B2 (en) 2014-05-28 2017-09-12 Nxp Usa, Inc. Input/output cell, integrated circuit device and methods of providing on-chip test functionality
KR20160080586A (ko) * 2014-12-30 2016-07-08 삼성전자주식회사 집적 회로의 설계 방법 및 집적 회로의 설계를 위한 컴퓨팅 시스템
FR3108441A1 (fr) * 2020-03-18 2021-09-24 Idemia Starchip Procédé et circuit intégré pour le test du circuit intégré disposé sur une galette de silicium.

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623888A (en) * 1983-12-08 1986-11-18 At&T Bell Laboratories Multi-function control interface circuit
JP2725258B2 (ja) * 1987-09-25 1998-03-11 三菱電機株式会社 集積回路装置
US5157781A (en) * 1990-01-02 1992-10-20 Motorola, Inc. Data processor test architecture
US5561761A (en) * 1993-03-31 1996-10-01 Ylsi Technology, Inc. Central processing unit data entering and interrogating device and method therefor
EP0636976B1 (de) 1993-07-28 1998-12-30 Koninklijke Philips Electronics N.V. Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Boundary-Scanverfahren
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5784382A (en) * 1995-03-01 1998-07-21 Unisys Corporation Method and apparatus for dynamically testing a memory within a computer system
US5898701A (en) * 1995-12-21 1999-04-27 Cypress Semiconductor Corporation Method and apparatus for testing a device
US5970510A (en) * 1996-04-10 1999-10-19 Northrop Grumman Corporation Distributed memory addressing system
US5936977A (en) * 1997-09-17 1999-08-10 Cypress Semiconductor Corp. Scan path circuitry including a programmable delay circuit
US5953285A (en) * 1997-09-17 1999-09-14 Cypress Semiconductor Corp. Scan path circuitry including an output register having a flow through mode

Also Published As

Publication number Publication date
US6321354B1 (en) 2001-11-20
FR2762683A1 (fr) 1998-10-30
DE69811760T2 (de) 2004-02-19
FR2762683B1 (fr) 1999-07-16
EP0875830A1 (de) 1998-11-04
EP0875830B1 (de) 2003-03-05

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Legal Events

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