DE69637314D1 - Eingangspufferschaltkreis, der mit einem hochfrequenten Taktsignal zurechtkommt - Google Patents

Eingangspufferschaltkreis, der mit einem hochfrequenten Taktsignal zurechtkommt

Info

Publication number
DE69637314D1
DE69637314D1 DE69637314T DE69637314T DE69637314D1 DE 69637314 D1 DE69637314 D1 DE 69637314D1 DE 69637314 T DE69637314 T DE 69637314T DE 69637314 T DE69637314 T DE 69637314T DE 69637314 D1 DE69637314 D1 DE 69637314D1
Authority
DE
Germany
Prior art keywords
handle
clock signal
buffer circuit
input buffer
frequency clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69637314T
Other languages
English (en)
Other versions
DE69637314T2 (de
Inventor
Yoshinori Okajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69637314D1 publication Critical patent/DE69637314D1/de
Application granted granted Critical
Publication of DE69637314T2 publication Critical patent/DE69637314T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Static Random-Access Memory (AREA)
DE69637314T 1996-07-09 1996-12-16 Eingangspufferschaltkreis, der mit einem hochfrequenten Taktsignal zurechtkommt Expired - Lifetime DE69637314T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP17955096 1996-07-09
JP17955096A JP3612634B2 (ja) 1996-07-09 1996-07-09 高速クロック信号に対応した入力バッファ回路、集積回路装置、半導体記憶装置、及び集積回路システム

Publications (2)

Publication Number Publication Date
DE69637314D1 true DE69637314D1 (de) 2007-12-20
DE69637314T2 DE69637314T2 (de) 2008-08-21

Family

ID=16067713

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69637314T Expired - Lifetime DE69637314T2 (de) 1996-07-09 1996-12-16 Eingangspufferschaltkreis, der mit einem hochfrequenten Taktsignal zurechtkommt

Country Status (6)

Country Link
US (2) US5793680A (de)
EP (2) EP1437661A3 (de)
JP (1) JP3612634B2 (de)
KR (1) KR100199547B1 (de)
DE (1) DE69637314T2 (de)
TW (1) TW321742B (de)

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US5767709A (en) * 1996-01-19 1998-06-16 Sgs-Thomson Microelectronics, Inc. Synchronous test mode initalization
JP2988392B2 (ja) * 1996-08-09 1999-12-13 日本電気株式会社 半導体メモリ集積回路
JP3972414B2 (ja) * 1997-06-20 2007-09-05 ソニー株式会社 データ判定回路およびデータ判定方法
US6215725B1 (en) * 1997-07-23 2001-04-10 Sharp Kabushiki Kaisha Clock-synchronized memory
KR100261215B1 (ko) * 1997-07-29 2000-07-01 윤종용 클럭 버퍼 및 이를 포함하는 메모리 로직 복합 반도체장치
JPH11122232A (ja) * 1997-10-17 1999-04-30 Fujitsu Ltd 位相検出回路及び位相検出回路を用いたタイミング抽出回路
JP3788867B2 (ja) * 1997-10-28 2006-06-21 株式会社東芝 半導体記憶装置
US6433607B2 (en) * 1998-01-21 2002-08-13 Fujitsu Limited Input circuit and semiconductor integrated circuit having the input circuit
US6289400B1 (en) * 1998-04-15 2001-09-11 Infineon Technologies Ag Electrical control device with configurable control modules
KR100305646B1 (ko) * 1998-05-29 2001-11-30 박종섭 클럭보정회로
JP4034886B2 (ja) * 1998-10-13 2008-01-16 富士通株式会社 半導体装置
US6275086B1 (en) * 1998-11-19 2001-08-14 Fujitsu Limited Clock signal generator for an integrated circuit
KR100287186B1 (ko) * 1999-03-29 2001-04-16 윤종용 반도체 메모리 장치의 상보형 차동 입력 버퍼
KR100358121B1 (ko) 1999-05-13 2002-10-25 주식회사 하이닉스반도체 반도체장치의 신호 입력회로
KR100340863B1 (ko) 1999-06-29 2002-06-15 박종섭 딜레이 록 루프 회로
JP4822572B2 (ja) 1999-09-02 2011-11-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6240024B1 (en) * 2000-04-10 2001-05-29 Motorola, Inc. Method and apparatus for generating an echo clock in a memory
US6222791B1 (en) * 2000-06-15 2001-04-24 Artisan Components, Inc. Slew tolerant clock input buffer and a self-timed memory core thereof
US6807613B1 (en) * 2000-08-21 2004-10-19 Mircon Technology, Inc. Synchronized write data on a high speed memory bus
US6333893B1 (en) * 2000-08-21 2001-12-25 Micron Technology, Inc. Method and apparatus for crossing clock domain boundaries
JP2002171164A (ja) * 2000-11-30 2002-06-14 Mitsubishi Electric Corp 半導体装置の入力バッファ
JP2002245778A (ja) * 2001-02-16 2002-08-30 Fujitsu Ltd 半導体装置
JP4606628B2 (ja) * 2001-03-26 2011-01-05 ルネサスエレクトロニクス株式会社 入力回路
US6670836B1 (en) * 2002-08-15 2003-12-30 Micron Technology, Inc. Differential buffer having bias current gated by associated signal
JP4366914B2 (ja) 2002-09-25 2009-11-18 日本電気株式会社 表示装置用駆動回路及びそれを用いた表示装置
KR100891322B1 (ko) * 2002-09-25 2009-03-31 삼성전자주식회사 데이터 입력 마진을 개선할 수 있는 동시 양방향 입출력회로
KR100495916B1 (ko) * 2002-11-20 2005-06-17 주식회사 하이닉스반도체 클럭인에이블 버퍼를 구비한 반도체 장치
DE102004015318B3 (de) * 2004-03-30 2005-09-01 Infineon Technologies Ag Eingangsschaltung für eine elektronische Schaltung
US7161846B2 (en) * 2004-11-16 2007-01-09 Seiko Epson Corporation Dual-edge triggered multiplexer flip-flop and method
KR100812600B1 (ko) * 2005-09-29 2008-03-13 주식회사 하이닉스반도체 주파수가 다른 복수의 클럭을 사용하는 반도체메모리소자
JP4792354B2 (ja) * 2006-09-08 2011-10-12 大崎電気工業株式会社 位相調整機能付きシングルビット乗算回路
US7558125B2 (en) * 2006-12-15 2009-07-07 Micron Technology, Inc. Input buffer and method with AC positive feedback, and a memory device and computer system using same
JP2008277941A (ja) * 2007-04-26 2008-11-13 Nec Electronics Corp インタフェース回路
CN104246891B (zh) * 2012-03-20 2018-01-26 英特尔公司 响应用于操作控制的装置命令的存储器装置
CN106021151A (zh) * 2016-05-09 2016-10-12 浪潮电子信息产业股份有限公司 一种信号增强板、信号增强方法以及***
US11595033B2 (en) * 2020-11-17 2023-02-28 Texas Instruments Incorporated Comparator architecture for reduced delay and lower static current
US20230188038A1 (en) * 2021-12-09 2023-06-15 Renesas Electronics America Inc. Regulator booster

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US4504747A (en) * 1983-11-10 1985-03-12 Motorola, Inc. Input buffer circuit for receiving multiple level input voltages
US4783607A (en) * 1986-11-05 1988-11-08 Xilinx, Inc. TTL/CMOS compatible input buffer with Schmitt trigger
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
US5065054A (en) * 1990-11-21 1991-11-12 Advanced Micro Devices, Inc. Input buffer with noise filter for eliminating short-pulse-width noise
JP2999845B2 (ja) * 1991-04-25 2000-01-17 沖電気工業株式会社 シリアルアクセスメモリの倍速コントロール方式
US5487038A (en) * 1994-08-15 1996-01-23 Creative Integrated Systems, Inc. Method for read cycle interrupts in a dynamic read-only memory
JPH09148907A (ja) * 1995-11-22 1997-06-06 Nec Corp 同期式半導体論理装置

Also Published As

Publication number Publication date
TW321742B (en) 1997-12-01
EP0818735A2 (de) 1998-01-14
EP1437661A2 (de) 2004-07-14
JPH1028041A (ja) 1998-01-27
US5793680A (en) 1998-08-11
JP3612634B2 (ja) 2005-01-19
US5838630A (en) 1998-11-17
KR100199547B1 (ko) 1999-06-15
DE69637314T2 (de) 2008-08-21
EP0818735A3 (de) 2000-02-09
KR980010795A (ko) 1998-04-30
EP0818735B1 (de) 2007-11-07
EP1437661A3 (de) 2009-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE