DE69631879D1 - Herstellungsverfahren für einen integrierten Dickoxydtransistor - Google Patents
Herstellungsverfahren für einen integrierten DickoxydtransistorInfo
- Publication number
- DE69631879D1 DE69631879D1 DE69631879T DE69631879T DE69631879D1 DE 69631879 D1 DE69631879 D1 DE 69631879D1 DE 69631879 T DE69631879 T DE 69631879T DE 69631879 T DE69631879 T DE 69631879T DE 69631879 D1 DE69631879 D1 DE 69631879D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing process
- thick oxide
- oxide transistor
- integrated thick
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96830244A EP0805479B1 (de) | 1996-04-30 | 1996-04-30 | Herstellungsverfahren für einen integrierten Dickoxydtransistor |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69631879D1 true DE69631879D1 (de) | 2004-04-22 |
Family
ID=8225892
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69631879T Expired - Lifetime DE69631879D1 (de) | 1996-04-30 | 1996-04-30 | Herstellungsverfahren für einen integrierten Dickoxydtransistor |
Country Status (3)
Country | Link |
---|---|
US (2) | US6156610A (de) |
EP (1) | EP0805479B1 (de) |
DE (1) | DE69631879D1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1104021A1 (de) * | 1999-11-29 | 2001-05-30 | STMicroelectronics S.r.l. | Herstellungsverfahren von integrierten Schaltkreisen mit Niederspannungstransistoren, EPROM-Zellen und Hochspannungstransistoren |
WO2001047012A1 (en) * | 1999-12-21 | 2001-06-28 | Koninklijke Philips Electronics N.V. | Non-volatile memory cells and periphery |
US6624027B1 (en) | 2002-05-09 | 2003-09-23 | Atmel Corporation | Ultra small thin windows in floating gate transistors defined by lost nitride spacers |
US6777764B2 (en) * | 2002-09-10 | 2004-08-17 | Macronix International Co., Ltd. | ONO interpoly dielectric for flash memory cells and method for fabricating the same using a single wafer low temperature deposition process |
JP2004363443A (ja) * | 2003-06-06 | 2004-12-24 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US8338887B2 (en) * | 2005-07-06 | 2012-12-25 | Infineon Technologies Ag | Buried gate transistor |
CN105448842B (zh) * | 2014-08-29 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制作方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56120166A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
IT1213249B (it) * | 1984-11-26 | 1989-12-14 | Ates Componenti Elettron | Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori. |
US5104819A (en) * | 1989-08-07 | 1992-04-14 | Intel Corporation | Fabrication of interpoly dielctric for EPROM-related technologies |
US5057449A (en) * | 1990-03-26 | 1991-10-15 | Micron Technology, Inc. | Process for creating two thicknesses of gate oxide within a dynamic random access memory |
JP3548984B2 (ja) * | 1991-11-14 | 2004-08-04 | 富士通株式会社 | 半導体装置の製造方法 |
JP2924622B2 (ja) * | 1993-12-28 | 1999-07-26 | 日本電気株式会社 | 半導体装置の製造方法 |
-
1996
- 1996-04-30 EP EP96830244A patent/EP0805479B1/de not_active Expired - Lifetime
- 1996-04-30 DE DE69631879T patent/DE69631879D1/de not_active Expired - Lifetime
-
1997
- 1997-04-28 US US08/840,327 patent/US6156610A/en not_active Expired - Lifetime
-
2000
- 2000-09-29 US US09/675,753 patent/US6570216B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6156610A (en) | 2000-12-05 |
EP0805479A1 (de) | 1997-11-05 |
US6570216B1 (en) | 2003-05-27 |
EP0805479B1 (de) | 2004-03-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |