DE69616416D1 - Verfahren zur Simulation einer Schaltung - Google Patents

Verfahren zur Simulation einer Schaltung

Info

Publication number
DE69616416D1
DE69616416D1 DE69616416T DE69616416T DE69616416D1 DE 69616416 D1 DE69616416 D1 DE 69616416D1 DE 69616416 T DE69616416 T DE 69616416T DE 69616416 T DE69616416 T DE 69616416T DE 69616416 D1 DE69616416 D1 DE 69616416D1
Authority
DE
Germany
Prior art keywords
simulating
procedure
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69616416T
Other languages
English (en)
Other versions
DE69616416T2 (de
Inventor
David Sharrit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Application granted granted Critical
Publication of DE69616416D1 publication Critical patent/DE69616416D1/de
Publication of DE69616416T2 publication Critical patent/DE69616416T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
DE69616416T 1995-05-12 1996-03-27 Verfahren zur Simulation einer Schaltung Expired - Lifetime DE69616416T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/440,204 US5588142A (en) 1995-05-12 1995-05-12 Method for simulating a circuit

Publications (2)

Publication Number Publication Date
DE69616416D1 true DE69616416D1 (de) 2001-12-06
DE69616416T2 DE69616416T2 (de) 2002-06-06

Family

ID=23747862

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69616416T Expired - Lifetime DE69616416T2 (de) 1995-05-12 1996-03-27 Verfahren zur Simulation einer Schaltung

Country Status (4)

Country Link
US (1) US5588142A (de)
EP (1) EP0742526B1 (de)
JP (1) JP3894375B2 (de)
DE (1) DE69616416T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838949A (en) * 1995-12-28 1998-11-17 Design Acceleration Inc. System and method for execution-sequenced processing of electronic design simulation results
US6151698A (en) * 1996-04-30 2000-11-21 Cadence Design Systems, Inc. Method for determining the steady state behavior of a circuit using an iterative technique
CN1043256C (zh) * 1996-11-05 1999-05-05 中国科学院物理研究所 一种有序排列的碳纳米管及其制备方法和专用装置
US5808915A (en) * 1996-11-08 1998-09-15 Hewlett-Packard Company Method for reducing the memory required to simulating a circuit on a digital computer
US5946211A (en) * 1997-02-28 1999-08-31 The Whitaker Corporation Method for manufacturing a circuit on a circuit substrate
US6367064B1 (en) 1998-05-22 2002-04-02 Micron Technology, Inc. Verification of sensitivity list integrity in a hardware description language file
US6237007B1 (en) 1998-07-02 2001-05-22 Micron Technology, Inc. Verification of port list integrity in a hardware description language file
US6154716A (en) * 1998-07-29 2000-11-28 Lucent Technologies - Inc. System and method for simulating electronic circuits
US6195623B1 (en) 1998-09-15 2001-02-27 Lucent Technologies Inc. Time-frequency method and apparatus for simulating the initial transient response of quartz oscillators
US7493240B1 (en) * 2000-05-15 2009-02-17 Cadence Design Systems, Inc. Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithm
US7085700B2 (en) * 2001-06-20 2006-08-01 Cadence Design Systems, Inc. Method for debugging of analog and mixed-signal behavioral models during simulation
US7038468B2 (en) * 2003-06-11 2006-05-02 Jan Verspecht Method and a test setup for measuring large-signal S-parameters that include the coefficients relating to the conjugate of the incident waves
DE10343346B4 (de) 2003-09-12 2011-01-27 Qimonda Ag Verfahren zum Prüfen einer elektrischen Schaltung und Einrichtung zur Durchführung des Verfahrens
US7299428B2 (en) * 2004-02-06 2007-11-20 Cadence Design Systems, Inc Model stamping matrix check technique in circuit simulator
US7403884B2 (en) * 2004-06-08 2008-07-22 International Business Machines Corporation Transient simulation using adaptive piecewise constant model
US7325210B2 (en) * 2005-03-10 2008-01-29 International Business Machines Corporation Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
US8478573B2 (en) * 2005-06-23 2013-07-02 Synopsys, Inc. Modeling circuit cells for waveform propagation
US8200467B1 (en) * 2007-05-31 2012-06-12 Cadence Design Systems, Inc. Adaptive solver for cyclic behavior of a circuit
FR2946166A1 (fr) * 2009-05-29 2010-12-03 Inst Nat Rech Inf Automat Simulateur de circuit electrique ameliore
US9002692B2 (en) * 2012-03-13 2015-04-07 Synopsys, Inc. Electronic circuit simulation method with adaptive iteration
JP6077476B2 (ja) * 2014-02-05 2017-02-08 日本電信電話株式会社 光デバイスシミュレーション方法
US10423744B1 (en) * 2015-01-28 2019-09-24 Cadence Design Systems, Inc. Reduced resource harmonic balance circuit simulations
CN113094887B (zh) * 2021-03-31 2024-05-03 清华大学 移频电磁暂态仿真的优化方法、装置和电子设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2578668B1 (fr) * 1985-03-08 1989-06-02 Hennion Bernard Systeme de simulation d'un circuit electronique
US4918643A (en) * 1988-06-21 1990-04-17 At&T Bell Laboratories Method and apparatus for substantially improving the throughput of circuit simulators
JP2765888B2 (ja) * 1988-12-02 1998-06-18 株式会社日立製作所 プログラム生成方法および実行方法
US5025402A (en) * 1989-04-07 1991-06-18 Northern Telecom Limited Method of transient simulation of transmission line networks using a circuit simulator
US5233628A (en) * 1991-05-29 1993-08-03 Virginia Polytechnic Institute And State University Computer-based bit error simulation for digital wireless communications
US5467291A (en) * 1991-09-09 1995-11-14 Hewlett-Packard Company Measurement-based system for modeling and simulation of active semiconductor devices over an extended operating frequency range
US5349539A (en) * 1991-10-28 1994-09-20 Zeelan Technology, Inc. Behavioral model parameter extractor
US5335191A (en) * 1992-03-27 1994-08-02 Cadence Design Systems, Inc. Method and means for communication between simulation engine and component models in a circuit simulator
US5379231A (en) * 1992-05-29 1995-01-03 University Of Texas System Method and apparatus for simulating a microelectric interconnect circuit
US5369594A (en) * 1992-06-18 1994-11-29 International Business Machines Corporation Conjugate gradient method in computer-aided circuit design
US5469366A (en) * 1993-09-20 1995-11-21 Lsi Logic Corporation Method and apparatus for determining the performance of nets of an integrated circuit design on a semiconductor design automation system

Also Published As

Publication number Publication date
DE69616416T2 (de) 2002-06-06
EP0742526A1 (de) 1996-11-13
JP3894375B2 (ja) 2007-03-22
EP0742526B1 (de) 2001-10-31
JPH0916660A (ja) 1997-01-17
US5588142A (en) 1996-12-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US