DE69423266D1 - Bus-Master-Rechnersystem und Verfahren - Google Patents
Bus-Master-Rechnersystem und VerfahrenInfo
- Publication number
- DE69423266D1 DE69423266D1 DE69423266T DE69423266T DE69423266D1 DE 69423266 D1 DE69423266 D1 DE 69423266D1 DE 69423266 T DE69423266 T DE 69423266T DE 69423266 T DE69423266 T DE 69423266T DE 69423266 D1 DE69423266 D1 DE 69423266D1
- Authority
- DE
- Germany
- Prior art keywords
- computer system
- bus master
- master computer
- bus
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/081,080 US5546560A (en) | 1993-06-22 | 1993-06-22 | Device and method for reducing bus activity in a computer system having multiple bus-masters |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69423266D1 true DE69423266D1 (de) | 2000-04-13 |
DE69423266T2 DE69423266T2 (de) | 2000-10-12 |
Family
ID=22161980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69423266T Expired - Lifetime DE69423266T2 (de) | 1993-06-22 | 1994-05-05 | Bus-Master-Rechnersystem und Verfahren |
Country Status (4)
Country | Link |
---|---|
US (1) | US5546560A (de) |
EP (1) | EP0631236B1 (de) |
JP (1) | JPH0756844A (de) |
DE (1) | DE69423266T2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002123479A (ja) | 2000-10-17 | 2002-04-26 | Hitachi Ltd | ディスク制御装置およびそのキャッシュ制御方法 |
DE102004006485A1 (de) * | 2004-02-10 | 2005-08-25 | Adidas International Marketing B.V. | Bekleidungsstück |
US7818507B2 (en) * | 2005-04-04 | 2010-10-19 | Sony Computer Entertainment Inc. | Methods and apparatus for facilitating coherency management in distributed multi-processor system |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4959777A (en) * | 1987-07-27 | 1990-09-25 | Motorola Computer X | Write-shared cache circuit for multiprocessor system |
US5185878A (en) * | 1988-01-20 | 1993-02-09 | Advanced Micro Device, Inc. | Programmable cache memory as well as system incorporating same and method of operating programmable cache memory |
US5265235A (en) * | 1990-11-30 | 1993-11-23 | Xerox Corporation | Consistency protocols for shared memory multiprocessors |
US5293384A (en) * | 1991-10-04 | 1994-03-08 | Bull Hn Information Systems Inc. | Microprocessor bus interface protocol analyzer |
US5261106A (en) * | 1991-12-13 | 1993-11-09 | S-Mos Systems, Inc. | Semaphore bypass |
US5388224A (en) * | 1992-04-24 | 1995-02-07 | Digital Equipment Corporation | Processor identification mechanism for a multiprocessor system |
-
1993
- 1993-06-22 US US08/081,080 patent/US5546560A/en not_active Expired - Lifetime
-
1994
- 1994-05-05 EP EP94303243A patent/EP0631236B1/de not_active Expired - Lifetime
- 1994-05-05 DE DE69423266T patent/DE69423266T2/de not_active Expired - Lifetime
- 1994-06-20 JP JP6137451A patent/JPH0756844A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH0756844A (ja) | 1995-03-03 |
EP0631236A1 (de) | 1994-12-28 |
DE69423266T2 (de) | 2000-10-12 |
US5546560A (en) | 1996-08-13 |
EP0631236B1 (de) | 2000-03-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |