DE69310848D1 - Steuerschaltung zum Testen eines Abfragepfades - Google Patents
Steuerschaltung zum Testen eines AbfragepfadesInfo
- Publication number
- DE69310848D1 DE69310848D1 DE69310848T DE69310848T DE69310848D1 DE 69310848 D1 DE69310848 D1 DE 69310848D1 DE 69310848 T DE69310848 T DE 69310848T DE 69310848 T DE69310848 T DE 69310848T DE 69310848 D1 DE69310848 D1 DE 69310848D1
- Authority
- DE
- Germany
- Prior art keywords
- control circuit
- test
- scan path
- scan
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
- G01R31/318525—Test of flip-flops or latches
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4256670A JP2550837B2 (ja) | 1992-09-25 | 1992-09-25 | スキャンパスのテスト制御回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69310848D1 true DE69310848D1 (de) | 1997-06-26 |
DE69310848T2 DE69310848T2 (de) | 1998-01-08 |
Family
ID=17295841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69310848T Expired - Lifetime DE69310848T2 (de) | 1992-09-25 | 1993-09-27 | Steuerschaltung zum Testen eines Abfragepfades |
Country Status (4)
Country | Link |
---|---|
US (1) | US5467354A (de) |
EP (1) | EP0590575B1 (de) |
JP (1) | JP2550837B2 (de) |
DE (1) | DE69310848T2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5260950A (en) * | 1991-09-17 | 1993-11-09 | Ncr Corporation | Boundary-scan input circuit for a reset pin |
JP3319541B2 (ja) * | 1994-03-29 | 2002-09-03 | 株式会社東芝 | 半導体集積回路装置 |
TW418329B (en) * | 1994-08-24 | 2001-01-11 | Ibm | Integrated circuit clocking technique and circuit therefor |
US5729553A (en) * | 1994-08-29 | 1998-03-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with a testable block |
US6173428B1 (en) * | 1994-11-16 | 2001-01-09 | Cray Research, Inc. | Apparatus and method for testing using clocked test access port controller for level sensitive scan designs |
KR0147619B1 (ko) * | 1995-01-27 | 1998-12-01 | 김광호 | 플립플롭 제어기 |
US5710779A (en) * | 1996-04-09 | 1998-01-20 | Texas Instruments Incorporated | Real time data observation method and apparatus |
US5812561A (en) * | 1996-09-03 | 1998-09-22 | Motorola, Inc. | Scan based testing of an integrated circuit for compliance with timing specifications |
US5944845A (en) * | 1997-06-26 | 1999-08-31 | Micron Technology, Inc. | Circuit and method to prevent inadvertent test mode entry |
FR2821436B1 (fr) * | 2001-02-26 | 2004-07-23 | St Microelectronics Sa | Procede et systeme de test d'un circuit integre |
US7412624B1 (en) * | 2004-09-14 | 2008-08-12 | Altera Corporation | Methods and apparatus for debugging a system with a hung data bus |
JP4922055B2 (ja) * | 2007-04-27 | 2012-04-25 | ルネサスエレクトロニクス株式会社 | スキャンテスト回路、及びスキャンテスト制御方法 |
US20090177424A1 (en) * | 2008-01-08 | 2009-07-09 | Ronald Pasqualini | 3-Dimensional method for determining the clock-to-Q delay of a flipflop |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4588944A (en) * | 1983-06-13 | 1986-05-13 | Sperry Corporation | Fully scan-set testable embedded edge-triggered dual D and J-K flip-flops through testing as inverter strings |
US4580137A (en) * | 1983-08-29 | 1986-04-01 | International Business Machines Corporation | LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control |
US4718065A (en) * | 1986-03-31 | 1988-01-05 | Tandem Computers Incorporated | In-line scan control apparatus for data processor testing |
US5155432A (en) * | 1987-10-07 | 1992-10-13 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US5260950A (en) * | 1991-09-17 | 1993-11-09 | Ncr Corporation | Boundary-scan input circuit for a reset pin |
-
1992
- 1992-09-25 JP JP4256670A patent/JP2550837B2/ja not_active Expired - Fee Related
-
1993
- 1993-09-27 US US08/126,653 patent/US5467354A/en not_active Expired - Lifetime
- 1993-09-27 DE DE69310848T patent/DE69310848T2/de not_active Expired - Lifetime
- 1993-09-27 EP EP93115584A patent/EP0590575B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0590575A1 (de) | 1994-04-06 |
US5467354A (en) | 1995-11-14 |
JPH06160476A (ja) | 1994-06-07 |
EP0590575B1 (de) | 1997-05-21 |
DE69310848T2 (de) | 1998-01-08 |
JP2550837B2 (ja) | 1996-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69310848D1 (de) | Steuerschaltung zum Testen eines Abfragepfades | |
EP0548585A3 (de) | ||
DE69416471D1 (de) | Abtastpfadsystem und Prüf- und Diagnoseverfahren | |
WO1995030230A3 (en) | Scannable d-flip-flop with system independent clocking | |
IL120927A (en) | Method and apparatus for testing a megacell in an ASIC using JTAG | |
JPS6483169A (en) | Integrated circuit device | |
JPS643744A (en) | Lsi test method | |
DE69226401D1 (de) | Ausführung der IEEE 1149.1-Schnittstellenarchitektur | |
JPS5542391A (en) | Method and device for testing shift rfgister | |
DE69030209D1 (de) | Durch Ereigniss befähigte Prüfarchitektur für integrierte Schaltungen | |
TW255021B (en) | Testing data processing apparatus | |
TW200407721A (en) | Boundary-scan methods and apparatus | |
DE69229160D1 (de) | Prüfmustererzeugungsverfahren für Abtastschaltung | |
US7519111B2 (en) | Apparatus and method for providing system and test clock signals to an integrated circuit on a single pin | |
JPS5727041A (en) | Large-scale integrated circuit having testing function | |
JPS578858A (en) | Integrated circuit package | |
DE60105168D1 (de) | Automatische Abtastprüfung von komplexen integrierten Schaltungen | |
JPS55110341A (en) | Logic circuit | |
JPS5549757A (en) | Test method of testing shift path | |
JPS6479673A (en) | Test system for ram contained lsi chip | |
JPS5674759A (en) | Diagnostic system | |
JPS5549761A (en) | Logical operation circuit testing unit | |
ELLIS | ATLAS- Hit or myth(ATE compiler language) | |
JPS5690271A (en) | Testing method for logic device | |
JPS5422137A (en) | Bus line chekcing device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
R082 | Change of representative |
Ref document number: 590575 Country of ref document: EP Representative=s name: BETTEN & RESCH, DE |
|
R081 | Change of applicant/patentee |
Ref document number: 590575 Country of ref document: EP Owner name: RENESAS ELECTRONICS CORPORATION, JP Free format text: FORMER OWNER: NEC ELECTRONICS CORP., KAWASAKI, JP Effective date: 20120828 |
|
R082 | Change of representative |
Ref document number: 590575 Country of ref document: EP Representative=s name: PATENTANWAELTE BETTEN & RESCH, DE Effective date: 20120828 |