DE69230703D1 - Rechnerbussteuerungssystem - Google Patents

Rechnerbussteuerungssystem

Info

Publication number
DE69230703D1
DE69230703D1 DE69230703T DE69230703T DE69230703D1 DE 69230703 D1 DE69230703 D1 DE 69230703D1 DE 69230703 T DE69230703 T DE 69230703T DE 69230703 T DE69230703 T DE 69230703T DE 69230703 D1 DE69230703 D1 DE 69230703D1
Authority
DE
Germany
Prior art keywords
control system
bus control
computer bus
computer
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69230703T
Other languages
English (en)
Other versions
DE69230703T2 (de
Inventor
Thomas Heil
Edward A Mcdonald
Gene F Young
Craig A Walrath
James M Ottinger
Marti D Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/760,786 external-priority patent/US5359715A/en
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69230703D1 publication Critical patent/DE69230703D1/de
Publication of DE69230703T2 publication Critical patent/DE69230703T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE1992630703 1991-09-16 1992-09-15 Rechnerbussteuerungssystem Expired - Lifetime DE69230703T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/760,786 US5359715A (en) 1991-09-16 1991-09-16 Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces
US76108391A 1991-09-17 1991-09-17

Publications (2)

Publication Number Publication Date
DE69230703D1 true DE69230703D1 (de) 2000-03-30
DE69230703T2 DE69230703T2 (de) 2000-10-05

Family

ID=27116871

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992630703 Expired - Lifetime DE69230703T2 (de) 1991-09-16 1992-09-15 Rechnerbussteuerungssystem

Country Status (2)

Country Link
EP (1) EP0533429B1 (de)
DE (1) DE69230703T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5553248A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal
US7676621B2 (en) 2003-09-12 2010-03-09 Hewlett-Packard Development Company, L.P. Communications bus transceiver
CN114036096B (zh) * 2021-11-04 2024-05-03 珠海一微半导体股份有限公司 一种基于总线接口的读控制器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868741A (en) * 1983-07-22 1989-09-19 Texas Instruments Incorporated Computer bus deadlock prevention
US4870704A (en) * 1984-10-31 1989-09-26 Flexible Computer Corporation Multicomputer digital processing system

Also Published As

Publication number Publication date
DE69230703T2 (de) 2000-10-05
EP0533429B1 (de) 2000-02-23
EP0533429A2 (de) 1993-03-24
EP0533429A3 (en) 1993-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition