DE69220830T2 - Verfahren zur Herstellung von Halbleietervorrichtungen - Google Patents
Verfahren zur Herstellung von HalbleietervorrichtungenInfo
- Publication number
- DE69220830T2 DE69220830T2 DE69220830T DE69220830T DE69220830T2 DE 69220830 T2 DE69220830 T2 DE 69220830T2 DE 69220830 T DE69220830 T DE 69220830T DE 69220830 T DE69220830 T DE 69220830T DE 69220830 T2 DE69220830 T2 DE 69220830T2
- Authority
- DE
- Germany
- Prior art keywords
- conductor devices
- manufacturing semi
- semi
- manufacturing
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/680,953 US5168071A (en) | 1991-04-05 | 1991-04-05 | Method of making semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69220830D1 DE69220830D1 (de) | 1997-08-21 |
DE69220830T2 true DE69220830T2 (de) | 1998-01-02 |
Family
ID=24733186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69220830T Expired - Fee Related DE69220830T2 (de) | 1991-04-05 | 1992-02-03 | Verfahren zur Herstellung von Halbleietervorrichtungen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5168071A (de) |
EP (1) | EP0507434B1 (de) |
JP (1) | JPH0773109B2 (de) |
DE (1) | DE69220830T2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0478923B1 (de) * | 1990-08-31 | 1997-11-05 | Texas Instruments Incorporated | Verfahren zum Herstellen selbst-ausrichtender bipolarer Transistoren mit Heteroübergang |
EP0503473A3 (en) * | 1991-03-12 | 1992-10-28 | Texas Instruments Incorporated | Method of dry etching ina1as and ingaas lattice matched to inp |
JPH05152318A (ja) * | 1991-11-29 | 1993-06-18 | Nec Corp | ヘテロ接合バイポーラトランジスタとその製造方法 |
US5278083A (en) * | 1992-10-16 | 1994-01-11 | Texas Instruments Incorporated | Method for making reliable connections to small features of integrated circuits |
US5700701A (en) * | 1992-10-30 | 1997-12-23 | Texas Instruments Incorporated | Method for reducing junction capacitance and increasing current gain in collector-up bipolar transistors |
US5434091A (en) * | 1992-10-30 | 1995-07-18 | Texas Instruments Incorporated | Method for making collector up bipolar transistors having reducing junction capacitance and increasing current gain |
US5627105A (en) * | 1993-04-08 | 1997-05-06 | Varian Associates, Inc. | Plasma etch process and TiSix layers made using the process |
JP2720813B2 (ja) * | 1994-10-04 | 1998-03-04 | 日本電気株式会社 | 半導体装置の製造方法および半導体装置 |
US6010937A (en) * | 1995-09-05 | 2000-01-04 | Spire Corporation | Reduction of dislocations in a heteroepitaxial semiconductor structure |
US6083841A (en) * | 1997-05-15 | 2000-07-04 | Rohm Co., Ltd. | Method of etching gallium-nitride based compound semiconductor layer and method of manufacturing semiconductor light emitting device utilizing the same |
US6714573B2 (en) * | 2000-08-22 | 2004-03-30 | The Regents Of The University Of California | Contact scheme for intracavity-contacted vertical-cavity surface-emitting laser |
US7259444B1 (en) | 2004-07-20 | 2007-08-21 | Hrl Laboratories, Llc | Optoelectronic device with patterned ion implant subcollector |
JP2006073692A (ja) | 2004-09-01 | 2006-03-16 | Matsushita Electric Ind Co Ltd | ヘテロ接合バイポーラトランジスタおよびその製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60183726A (ja) * | 1984-03-02 | 1985-09-19 | Toshiba Corp | 半導体装置の電極パタ−ンの形成方法 |
US4541893A (en) * | 1984-05-15 | 1985-09-17 | Advanced Micro Devices, Inc. | Process for fabricating pedestal interconnections between conductive layers in an integrated circuit |
JPS63132452A (ja) * | 1986-11-24 | 1988-06-04 | Mitsubishi Electric Corp | パタ−ン形成方法 |
JPH0824123B2 (ja) * | 1987-04-17 | 1996-03-06 | 富士通株式会社 | 半導体装置の製造方法 |
JPS63276267A (ja) * | 1987-05-08 | 1988-11-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US5007984A (en) * | 1987-09-28 | 1991-04-16 | Mitsubishi Denki Kabushiki Kaisha | Method for etching chromium film formed on substrate |
JPH0276223A (ja) * | 1988-08-05 | 1990-03-15 | Siemens Ag | 金属接触の製造方法と装置 |
JP3057679B2 (ja) * | 1988-10-05 | 2000-07-04 | ソニー株式会社 | ヘテロ接合バイポーラトランジスタ及びその製造方法 |
JP2630445B2 (ja) * | 1988-10-08 | 1997-07-16 | 富士通株式会社 | 半導体装置 |
US4917759A (en) * | 1989-04-17 | 1990-04-17 | Motorola, Inc. | Method for forming self-aligned vias in multi-level metal integrated circuits |
JPH02297942A (ja) * | 1989-05-11 | 1990-12-10 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
FR2652200A1 (fr) * | 1989-09-21 | 1991-03-22 | Philips Lab Electronique | Procede de realisation d'un circuit semiconducteur integre incluant un transistor bipolaire a heterojonction et/ou des resistances enterrees. |
JPH03153043A (ja) * | 1989-11-10 | 1991-07-01 | Fujitsu Ltd | 高速半導体装置 |
-
1991
- 1991-04-05 US US07/680,953 patent/US5168071A/en not_active Expired - Lifetime
-
1992
- 1992-02-03 DE DE69220830T patent/DE69220830T2/de not_active Expired - Fee Related
- 1992-02-03 EP EP92300893A patent/EP0507434B1/de not_active Expired - Lifetime
- 1992-03-23 JP JP4094970A patent/JPH0773109B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH05109756A (ja) | 1993-04-30 |
US5168071A (en) | 1992-12-01 |
JPH0773109B2 (ja) | 1995-08-02 |
EP0507434B1 (de) | 1997-07-16 |
EP0507434A3 (en) | 1994-09-21 |
EP0507434A2 (de) | 1992-10-07 |
DE69220830D1 (de) | 1997-08-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |