DE69127050D1 - Abtast- und Halteschaltung - Google Patents

Abtast- und Halteschaltung

Info

Publication number
DE69127050D1
DE69127050D1 DE69127050T DE69127050T DE69127050D1 DE 69127050 D1 DE69127050 D1 DE 69127050D1 DE 69127050 T DE69127050 T DE 69127050T DE 69127050 T DE69127050 T DE 69127050T DE 69127050 D1 DE69127050 D1 DE 69127050D1
Authority
DE
Germany
Prior art keywords
sample
hold circuit
hold
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127050T
Other languages
English (en)
Other versions
DE69127050T2 (de
Inventor
Myles H Wakayama
Hiroshi Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69127050D1 publication Critical patent/DE69127050D1/de
Application granted granted Critical
Publication of DE69127050T2 publication Critical patent/DE69127050T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02Sample-and-hold arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02Sample-and-hold arrangements
    • G11C27/024Sample-and-hold arrangements using a capacitive memory element
DE69127050T 1990-10-30 1991-10-30 Abtast- und Halteschaltung Expired - Fee Related DE69127050T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29241890 1990-10-30
JP03241524A JP3103154B2 (ja) 1990-10-30 1991-09-20 サンプル・ホールド回路

Publications (2)

Publication Number Publication Date
DE69127050D1 true DE69127050D1 (de) 1997-09-04
DE69127050T2 DE69127050T2 (de) 1998-01-22

Family

ID=26535312

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127050T Expired - Fee Related DE69127050T2 (de) 1990-10-30 1991-10-30 Abtast- und Halteschaltung

Country Status (5)

Country Link
US (1) US5243235A (de)
EP (1) EP0484129B1 (de)
JP (1) JP3103154B2 (de)
KR (1) KR950012937B1 (de)
DE (1) DE69127050T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444363A (en) * 1993-12-16 1995-08-22 Advanced Micro Devices Inc. Low noise apparatus for receiving an input current and producing an output current which mirrors the input current
US5552784A (en) * 1994-06-30 1996-09-03 Northrop Grumman Corporation Distortion reduction circuit for analog to digital converter system
US5477190A (en) * 1994-12-16 1995-12-19 Advanced Micro Devices, Inc. Low voltage linear output buffer operational amplifier
US5572154A (en) * 1995-07-03 1996-11-05 Motorola, Inc. Circuit and method of sampling an analog signal
JPH09306193A (ja) * 1996-05-17 1997-11-28 Nec Corp サンプルホールド回路
US5838175A (en) * 1997-02-05 1998-11-17 Hewlett-Packard Company Low distortion track and hold circuit
US6069502A (en) * 1998-04-06 2000-05-30 Intersil Corporation Sample-and-hold circuit having reduced subthreshold conduction effects and related methods
US6002277A (en) * 1998-04-06 1999-12-14 Intersil Corporation Sample-and-hold circuit having reduced parasitic diode effects and related methods
US6016067A (en) * 1998-04-06 2000-01-18 Intersil Corporation Sample-and-hold circuit having reduced amplifier offset effects and related methods
US6323696B1 (en) 1999-12-07 2001-11-27 Hughes Electronics Corporation Sample and hold circuit
US6720799B2 (en) * 2001-01-11 2004-04-13 Broadcom Corporation Replica network for linearizing switched capacitor circuits
KR100433362B1 (ko) * 2002-07-11 2004-06-07 에이디반도체(주) 임피던스 비교 집적회로
US8482442B2 (en) * 2011-06-08 2013-07-09 Linear Technology Corporation System and methods to improve the performance of semiconductor based sampling system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115693A (ja) * 1981-12-28 1983-07-09 Sony Corp サンプルホ−ルド回路
US4879478A (en) * 1985-08-30 1989-11-07 Advanced Micro Devices, Inc. Fast sample and hold circuit
US4659946A (en) * 1986-04-14 1987-04-21 Tektronix, Inc. Memory gate for error sampler
JPS63108599A (ja) * 1986-10-24 1988-05-13 Mitsubishi Electric Corp ホ−ルド回路
JPS63263699A (ja) * 1987-04-21 1988-10-31 Nec Corp サンプルホ−ルド回路
FR2648943B1 (fr) * 1989-06-23 1991-10-11 Radiotechnique Compelec Circuit echantillonneur-bloqueur

Also Published As

Publication number Publication date
EP0484129B1 (de) 1997-07-30
US5243235A (en) 1993-09-07
JP3103154B2 (ja) 2000-10-23
EP0484129A2 (de) 1992-05-06
KR950012937B1 (ko) 1995-10-23
KR920009034A (ko) 1992-05-28
EP0484129A3 (en) 1992-08-26
DE69127050T2 (de) 1998-01-22
JPH0512897A (ja) 1993-01-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee