DE68916533D1 - Verfahren und vorrichtung zur hantierung von daten mit hoher geschwindigkeit. - Google Patents

Verfahren und vorrichtung zur hantierung von daten mit hoher geschwindigkeit.

Info

Publication number
DE68916533D1
DE68916533D1 DE68916533T DE68916533T DE68916533D1 DE 68916533 D1 DE68916533 D1 DE 68916533D1 DE 68916533 T DE68916533 T DE 68916533T DE 68916533 T DE68916533 T DE 68916533T DE 68916533 D1 DE68916533 D1 DE 68916533D1
Authority
DE
Germany
Prior art keywords
high speed
handling data
handling
data
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68916533T
Other languages
English (en)
Other versions
DE68916533T2 (de
Inventor
Nostrand Scott Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Application granted granted Critical
Publication of DE68916533D1 publication Critical patent/DE68916533D1/de
Publication of DE68916533T2 publication Critical patent/DE68916533T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Image Input (AREA)
DE68916533T 1988-12-12 1989-12-07 Verfahren und vorrichtung zur hantierung von daten mit hoher geschwindigkeit. Expired - Fee Related DE68916533T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/282,714 US5161221A (en) 1988-12-12 1988-12-12 Multi-memory bank system for receiving continuous serial data stream and monitoring same to control bank switching without interrupting continuous data flow rate
PCT/US1989/005440 WO1990007184A1 (en) 1988-12-12 1989-12-07 Method and apparatus for handling high speed data

Publications (2)

Publication Number Publication Date
DE68916533D1 true DE68916533D1 (de) 1994-08-04
DE68916533T2 DE68916533T2 (de) 1995-02-09

Family

ID=23082805

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916533T Expired - Fee Related DE68916533T2 (de) 1988-12-12 1989-12-07 Verfahren und vorrichtung zur hantierung von daten mit hoher geschwindigkeit.

Country Status (5)

Country Link
US (1) US5161221A (de)
EP (1) EP0401340B1 (de)
JP (1) JPH03502506A (de)
DE (1) DE68916533T2 (de)
WO (1) WO1990007184A1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9405914D0 (en) * 1994-03-24 1994-05-11 Discovision Ass Video decompression
FR2667688B1 (fr) * 1990-10-05 1994-04-29 Commissariat Energie Atomique Circuit d'acquisition ultrarapide.
DE69114825T2 (de) * 1990-12-21 1996-08-08 Sun Microsystems Inc Verfahren und Einrichtung zur Erhöhung der Verarbeitungsgeschwindigkeit eines Anzeigesystems mit Doppel-Pufferspeicher.
US5448710A (en) * 1991-02-26 1995-09-05 Hewlett-Packard Company Dynamically configurable interface cards with variable memory size
US6034674A (en) * 1992-06-30 2000-03-07 Discovision Associates Buffer manager
US5835740A (en) * 1992-06-30 1998-11-10 Discovision Associates Data pipeline system and data encoding method
ES2118217T3 (es) * 1993-05-19 1998-09-16 Alsthom Cge Alcatel Metodo de gestion de memoria de servidores de video.
EP0625856B1 (de) * 1993-05-19 1998-03-04 Alcatel Netzwerk für Video auf Anfrage
ES2118216T3 (es) * 1993-05-19 1998-09-16 Alsthom Cge Alcatel Dispositivo de servicio de video.
US6049331A (en) * 1993-05-20 2000-04-11 Hyundai Electronics America Step addressing in video RAM
US5861894A (en) * 1993-06-24 1999-01-19 Discovision Associates Buffer manager
US5768629A (en) * 1993-06-24 1998-06-16 Discovision Associates Token-based adaptive video processing arrangement
US5835952A (en) * 1993-07-14 1998-11-10 Matsushita Electric Industrial Co., Ltd. Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time
CA2145361C (en) * 1994-03-24 1999-09-07 Martin William Sotheran Buffer manager
US5701270A (en) * 1994-05-09 1997-12-23 Cirrus Logic, Inc. Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same
US5473573A (en) * 1994-05-09 1995-12-05 Cirrus Logic, Inc. Single chip controller-memory device and a memory architecture and methods suitable for implementing the same
JP3816972B2 (ja) * 1994-08-08 2006-08-30 株式会社ハイニックスセミコンダクター ディジタルビデオ記憶装置システム、およびそのビデオデータの格納方法と視聴方法
GB9417138D0 (en) * 1994-08-23 1994-10-12 Discovision Ass Data rate conversion
US5473566A (en) * 1994-09-12 1995-12-05 Cirrus Logic, Inc. Memory architecture and devices, systems and methods utilizing the same
EP0747825B1 (de) * 1995-06-06 2001-09-19 Hewlett-Packard Company, A Delaware Corporation SDRAM-Datenzuweisungsanordnung und -verfahren
US5654932A (en) * 1995-10-04 1997-08-05 Cirrus Logic, Inc. Memory devices with selectable access type and methods using the same
DE19750927B4 (de) * 1996-12-11 2007-10-18 Rohde & Schwarz Gmbh & Co. Kg Verfahren zum kontinuierlichen Auslesen einer Datenfolge aus einem Speicher
GB9704027D0 (en) * 1997-02-26 1997-04-16 Discovision Ass Memory manager for mpeg decoder
US7317957B1 (en) * 1997-09-24 2008-01-08 Sony Corporation Memory allocation for real-time audio processing
JP4378015B2 (ja) * 2000-02-28 2009-12-02 インターナショナル・ビジネス・マシーンズ・コーポレーション メモリ・チップ
US6459256B1 (en) * 2000-05-17 2002-10-01 Tektronix, Inc. Digital storage oscilloscope
EP1560190A3 (de) * 2004-01-27 2008-04-16 Data Display GmbH System zum Betreiben von Anzeigegeräten für Bilddaten über vorbestimmte Datenbuskonfigurationen
US7353491B2 (en) * 2004-05-28 2008-04-01 Peter Pius Gutberlet Optimization of memory accesses in a circuit design
US8564603B2 (en) * 2010-10-24 2013-10-22 Himax Technologies Limited Apparatus for controlling memory device and related method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA265765A (en) * 1926-11-16 Kanner Samuel Hat pad
US4206447A (en) * 1979-04-09 1980-06-03 Bell Telephone Laboratories, Incorporated Adaptive quantizer apparatus for differential coding of nonuniform digital signals
FR2463549A1 (fr) * 1979-08-10 1981-02-20 Telecommunications Sa Dispositif de reduction du debit numerique d'informations codees
JPS58149548A (ja) * 1982-03-02 1983-09-05 Hitachi Ltd メモリ制御方式
US4723226A (en) * 1982-09-29 1988-02-02 Texas Instruments Incorporated Video display system using serial/parallel access memories
US4663735A (en) * 1983-12-30 1987-05-05 Texas Instruments Incorporated Random/serial access mode selection circuit for a video memory system
US4747081A (en) * 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US4639890A (en) * 1983-12-30 1987-01-27 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers
CA1243138A (en) * 1984-03-09 1988-10-11 Masahiro Kodama High speed memory access circuit of crt display unit
JPS60245034A (ja) * 1984-05-18 1985-12-04 Ascii Corp デイスプレイコントロ−ラ
JPS6194295A (ja) * 1984-10-16 1986-05-13 Fujitsu Ltd 半導体記憶装置
US4667313A (en) * 1985-01-22 1987-05-19 Texas Instruments Incorporated Serially accessed semiconductor memory with tapped shift register
US4648077A (en) * 1985-01-22 1987-03-03 Texas Instruments Incorporated Video serial accessed memory with midline load
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4858107A (en) * 1985-03-11 1989-08-15 General Electric Company Computer device display system using conditionally asynchronous memory accessing by video display controller
US4663619A (en) * 1985-04-08 1987-05-05 Honeywell Inc. Memory access modes for a video display generator
US4884069A (en) * 1987-03-19 1989-11-28 Apple Computer, Inc. Video apparatus employing VRAMs
US4876663A (en) * 1987-04-23 1989-10-24 Mccord Donald G Display interface system using buffered VDRAMs and plural shift registers for data rate control between data source and display
GB2207840B (en) * 1987-08-07 1991-09-25 Philips Electronic Associated Method of and apparatus for modifying data stored in a random access memory

Also Published As

Publication number Publication date
DE68916533T2 (de) 1995-02-09
EP0401340A1 (de) 1990-12-12
US5161221A (en) 1992-11-03
EP0401340B1 (de) 1994-06-29
WO1990007184A1 (en) 1990-06-28
JPH03502506A (ja) 1991-06-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee