DE3751540D1 - Verfahren und Vorrichtung zur Datenverarbeitung. - Google Patents

Verfahren und Vorrichtung zur Datenverarbeitung.

Info

Publication number
DE3751540D1
DE3751540D1 DE3751540T DE3751540T DE3751540D1 DE 3751540 D1 DE3751540 D1 DE 3751540D1 DE 3751540 T DE3751540 T DE 3751540T DE 3751540 T DE3751540 T DE 3751540T DE 3751540 D1 DE3751540 D1 DE 3751540D1
Authority
DE
Germany
Prior art keywords
data processing
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3751540T
Other languages
English (en)
Other versions
DE3751540T2 (de
Inventor
Toyohiko Kagimasa
Yoshiki Matsuda
Kikuo Takahashi
Seiichi Yoshizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3751540D1 publication Critical patent/DE3751540D1/de
Application granted granted Critical
Publication of DE3751540T2 publication Critical patent/DE3751540T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
DE3751540T 1986-06-04 1987-06-04 Verfahren und Vorrichtung zur Datenverarbeitung. Expired - Fee Related DE3751540T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12791886 1986-06-04

Publications (2)

Publication Number Publication Date
DE3751540D1 true DE3751540D1 (de) 1995-11-02
DE3751540T2 DE3751540T2 (de) 1996-05-15

Family

ID=14971857

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751540T Expired - Fee Related DE3751540T2 (de) 1986-06-04 1987-06-04 Verfahren und Vorrichtung zur Datenverarbeitung.

Country Status (3)

Country Link
US (1) US4868740A (de)
EP (1) EP0248436B1 (de)
DE (1) DE3751540T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2617974B2 (ja) * 1988-03-08 1997-06-11 富士通株式会社 データ処理装置
JPH01269131A (ja) * 1988-04-20 1989-10-26 Hitachi Ltd 命令先行制御方式
US6038584A (en) * 1989-11-17 2000-03-14 Texas Instruments Incorporated Synchronized MIMD multi-processing system and method of operation
US5442769A (en) * 1990-03-13 1995-08-15 At&T Corp. Processor having general registers with subdivisions addressable in instructions by register number and subdivision type
DE69130495T2 (de) * 1990-06-29 1999-06-24 Digital Equipment Corp Umwandlung der Befehle von internen Prozessorregistern in I/O-Adressraum
EP0492971A3 (en) * 1990-12-21 1993-08-18 Sun Microsystems, Inc. Mask register for computer processor
DE69111778T2 (de) * 1990-12-21 1996-05-02 Sun Microsystems Inc Verfahren und Gerät zur Erweiterung einer Rechnerarchitektur von zweiunddreissig auf vierundsechzig Bits.
DE69227604T2 (de) * 1991-03-11 1999-06-24 Silicon Graphics Inc Mountain Rückwärts kompatible Rechnerarchitektur mit erweiterten Wortbreiten und Adressraum
US5341500A (en) * 1991-04-02 1994-08-23 Motorola, Inc. Data processor with combined static and dynamic masking of operand for breakpoint operation
JP3181307B2 (ja) * 1991-04-25 2001-07-03 株式会社東芝 命令処理装置
US5423013A (en) * 1991-09-04 1995-06-06 International Business Machines Corporation System for addressing a very large memory with real or virtual addresses using address mode registers
US5381537A (en) * 1991-12-06 1995-01-10 International Business Machines Corporation Large logical addressing method and means
CA2124333A1 (en) * 1992-02-27 1993-09-02 John A. Saba Cpu having pipelined instruction unit and effective address calculation unit with retained virtual address capability
GB9226463D0 (en) * 1992-12-18 1993-02-10 Univ London Integrated circuits
JP3451595B2 (ja) * 1995-06-07 2003-09-29 インターナショナル・ビジネス・マシーンズ・コーポレーション 二つの別個の命令セット・アーキテクチャへの拡張をサポートすることができるアーキテクチャ・モード制御を備えたマイクロプロセッサ
US5860076A (en) * 1996-01-11 1999-01-12 Alliance Semiconductor Corporation 48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses
US6182202B1 (en) * 1997-10-31 2001-01-30 Oracle Corporation Generating computer instructions having operand offset length fields for defining the length of variable length operand offsets
JP2000010863A (ja) * 1998-06-24 2000-01-14 Sony Computer Entertainment Inc 情報処理装置および方法、並びに提供媒体
US7124286B2 (en) * 2000-01-14 2006-10-17 Advanced Micro Devices, Inc. Establishing an operating mode in a processor
US6973562B1 (en) 2000-01-14 2005-12-06 Advanced Micro Devices, Inc. Establishing an operating mode in a processor
US7100028B2 (en) * 2000-08-09 2006-08-29 Advanced Micro Devices, Inc. Multiple entry points for system call instructions
US7058791B1 (en) 2000-08-09 2006-06-06 Advanced Micro Devices, Inc. Establishing a mode indication responsive to two or more indications
US7149878B1 (en) 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US6889312B1 (en) 2001-04-02 2005-05-03 Advanced Micro Devices, Inc. Selective zero extension based on operand size
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US7707389B2 (en) * 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof
CN115858432B (zh) * 2023-03-01 2023-05-16 上海励驰半导体有限公司 一种访问方法、装置、电子设备及可读存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100634A (en) * 1978-01-26 1979-08-08 Toshiba Corp Computer
JPS58189738A (ja) * 1982-04-30 1983-11-05 Hitachi Ltd デ−タ処理システム
JPS58189739A (ja) * 1982-04-30 1983-11-05 Hitachi Ltd デ−タ処理システム
JPS6097435A (ja) * 1983-11-02 1985-05-31 Hitachi Ltd 演算処理装置
DE3479356D1 (en) * 1983-12-23 1989-09-14 Hitachi Ltd A data processor with control of the significant bit lenghts of general purpose registers
US4785393A (en) * 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip
ATE45824T1 (de) * 1984-09-13 1989-09-15 Siemens Ag Schaltungsanordnung zur befehlstypabhaengigen berechnung von operandenadressen und zur pruefung der seitengrenzenueberschreitung bei operanden fuer logische oder dezimale speicher-speicherbefehle.

Also Published As

Publication number Publication date
EP0248436A2 (de) 1987-12-09
EP0248436B1 (de) 1995-09-27
DE3751540T2 (de) 1996-05-15
EP0248436A3 (de) 1991-09-04
US4868740A (en) 1989-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee