DE68906171D1 - Speichersytem mit serienzugriff mit einer kaskaden-pufferschaltung. - Google Patents

Speichersytem mit serienzugriff mit einer kaskaden-pufferschaltung.

Info

Publication number
DE68906171D1
DE68906171D1 DE8989101943T DE68906171T DE68906171D1 DE 68906171 D1 DE68906171 D1 DE 68906171D1 DE 8989101943 T DE8989101943 T DE 8989101943T DE 68906171 T DE68906171 T DE 68906171T DE 68906171 D1 DE68906171 D1 DE 68906171D1
Authority
DE
Germany
Prior art keywords
storage
storage system
cascade buffer
cascade
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8989101943T
Other languages
English (en)
Other versions
DE68906171T2 (de
Inventor
Takeshi C O Nec Corpo Mizukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE68906171D1 publication Critical patent/DE68906171D1/de
Publication of DE68906171T2 publication Critical patent/DE68906171T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)
DE8989101943T 1988-02-04 1989-02-03 Speichersytem mit serienzugriff mit einer kaskaden-pufferschaltung. Expired - Lifetime DE68906171T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63024893A JP2764908B2 (ja) 1988-02-04 1988-02-04 カスケード・バッファ回路

Publications (2)

Publication Number Publication Date
DE68906171D1 true DE68906171D1 (de) 1993-06-03
DE68906171T2 DE68906171T2 (de) 1993-08-05

Family

ID=12150864

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8989101943T Expired - Lifetime DE68906171T2 (de) 1988-02-04 1989-02-03 Speichersytem mit serienzugriff mit einer kaskaden-pufferschaltung.

Country Status (4)

Country Link
US (1) US4922457A (de)
EP (1) EP0327115B1 (de)
JP (1) JP2764908B2 (de)
DE (1) DE68906171T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5257237A (en) * 1989-05-16 1993-10-26 International Business Machines Corporation SAM data selection on dual-ported DRAM devices
US5068881A (en) * 1990-08-10 1991-11-26 Hewlett-Packard Company Scannable register with delay test capability
KR100275182B1 (ko) * 1990-12-17 2000-12-15 윌리엄 비. 켐플러 순차 메모리
US5255242A (en) * 1990-12-17 1993-10-19 Texas Instruments Incorporated Sequential memory
US5250858A (en) * 1992-02-19 1993-10-05 Vlsi Technology, Inc. Double-edge triggered memory device and system
CA2106271C (en) * 1993-01-11 2004-11-30 Joseph H. Steinmetz Single and multistage stage fifo designs for data transfer synchronizers
TW561491B (en) * 2001-06-29 2003-11-11 Toshiba Corp Semiconductor memory device
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
WO2007036050A1 (en) 2005-09-30 2007-04-05 Mosaid Technologies Incorporated Memory with output control
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
DE102008048066B4 (de) * 2008-09-19 2018-02-01 Texas Instruments Deutschland Gmbh Zugriffssteuerschaltung zur Verwendung mit einer Überwachungs-Logikschaltungsanordnung in einem Verfahren zum Schutz von Software für eingebettete Anwendungen vor unerlaubtem Zugriff

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7713706A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met een variabele ingang en een variabele uitgang.
NL7713707A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met variabele ingang en vaste uitgang.
JPS5694589A (en) * 1979-12-27 1981-07-31 Nec Corp Memory device
JPS57164331A (en) * 1981-04-02 1982-10-08 Nec Corp Buffer controller
JPH07118187B2 (ja) * 1985-05-27 1995-12-18 松下電器産業株式会社 先入れ先出し記憶装置
EP0206743A3 (de) * 1985-06-20 1990-04-25 Texas Instruments Incorporated Asynchroner FIFO-Puffer mit Null-Durchfallzeit und eindeutiger Leer/Voll-Angabe
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
JPH0817028B2 (ja) * 1985-12-06 1996-02-21 日本電気株式会社 リフレッシュ信号入力回路
US4829471A (en) * 1986-02-07 1989-05-09 Advanced Micro Devices, Inc. Data load sequencer for multiple data line serializer
US4750149A (en) * 1986-07-03 1988-06-07 Integrated Device Technology, Inc. Programmable FIFO buffer

Also Published As

Publication number Publication date
DE68906171T2 (de) 1993-08-05
JPH01200447A (ja) 1989-08-11
EP0327115A1 (de) 1989-08-09
JP2764908B2 (ja) 1998-06-11
US4922457A (en) 1990-05-01
EP0327115B1 (de) 1993-04-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKIO/TOKYO, JP