DE60313860D1 - Integrierte Schaltung mit verbesserter BIST-Schaltung zur Ausführung einer strukturierten Prüfung - Google Patents
Integrierte Schaltung mit verbesserter BIST-Schaltung zur Ausführung einer strukturierten PrüfungInfo
- Publication number
- DE60313860D1 DE60313860D1 DE60313860T DE60313860T DE60313860D1 DE 60313860 D1 DE60313860 D1 DE 60313860D1 DE 60313860 T DE60313860 T DE 60313860T DE 60313860 T DE60313860 T DE 60313860T DE 60313860 D1 DE60313860 D1 DE 60313860D1
- Authority
- DE
- Germany
- Prior art keywords
- test values
- built
- testing circuit
- test
- self testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/005—Testing of electric installations on transport means
- G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318577—AC testing, e.g. current testing, burn-in
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03425405A EP1491906B1 (de) | 2003-06-24 | 2003-06-24 | Integrierte Schaltung mit verbesserter BIST-Schaltung zur Ausführung einer strukturierten Prüfung |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60313860D1 true DE60313860D1 (de) | 2007-06-28 |
Family
ID=33396130
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60313860T Expired - Fee Related DE60313860D1 (de) | 2003-06-24 | 2003-06-24 | Integrierte Schaltung mit verbesserter BIST-Schaltung zur Ausführung einer strukturierten Prüfung |
Country Status (3)
Country | Link |
---|---|
US (1) | US7246288B2 (de) |
EP (1) | EP1491906B1 (de) |
DE (1) | DE60313860D1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050108228A1 (en) * | 2003-11-05 | 2005-05-19 | Larson Lee A. | Apparatus and method for performing a polling operation of a single bit in a JTAG data stream |
JP4157066B2 (ja) * | 2004-03-29 | 2008-09-24 | 株式会社東芝 | 半導体集積回路 |
US7272767B2 (en) * | 2005-04-29 | 2007-09-18 | Freescale Semiconductor, Inc. | Methods and apparatus for incorporating IDDQ testing into logic BIST |
TWI266065B (en) * | 2005-05-18 | 2006-11-11 | Via Tech Inc | Chip capable of testing itself and testing method thereof |
DE102005042790B4 (de) * | 2005-09-08 | 2010-11-18 | Infineon Technologies Ag | Integrierte Schaltungsanordnung und Verfahren zum Betrieb einer solchen |
US7652975B2 (en) * | 2006-02-03 | 2010-01-26 | Agilent Technologies, Inc. | Interoperability verification for implementation according to communication standard |
JP5661313B2 (ja) * | 2010-03-30 | 2015-01-28 | キヤノン株式会社 | 記憶装置 |
US20110307748A1 (en) * | 2010-06-15 | 2011-12-15 | Qualcomm Incorporated | Techniques for error diagnosis in vlsi systems |
JP6072437B2 (ja) * | 2012-06-06 | 2017-02-01 | ルネサスエレクトロニクス株式会社 | 半導体集積回路及びその設計方法 |
JP6191124B2 (ja) * | 2012-11-08 | 2017-09-06 | 株式会社ソシオネクスト | 半導体集積回路 |
US9268660B2 (en) | 2014-03-12 | 2016-02-23 | International Business Machines Corporation | Matrix and compression-based error detection |
CN105092930B (zh) * | 2014-05-06 | 2020-10-30 | 恩智浦美国有限公司 | 片上电流测试电路 |
US10691249B2 (en) * | 2017-09-29 | 2020-06-23 | Intel Corporation | Touch host controller |
US11003153B2 (en) * | 2017-11-17 | 2021-05-11 | Intel Corporation | Safety operation configuration for computer assisted vehicle |
CN108375702B (zh) * | 2017-12-01 | 2021-05-07 | 国网北京市电力公司 | 电采暖设备的监测方法及装置 |
US10345380B1 (en) | 2018-02-02 | 2019-07-09 | International Business Machines Corporation | Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading |
US11082241B2 (en) * | 2018-03-30 | 2021-08-03 | Intel Corporation | Physically unclonable function with feed-forward addressing and variable latency output |
KR102099355B1 (ko) * | 2018-11-26 | 2020-04-10 | 현대오트론 주식회사 | 집적회로 진단 장치 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4701920A (en) * | 1985-11-08 | 1987-10-20 | Eta Systems, Inc. | Built-in self-test system for VLSI circuit chips |
US5138619A (en) * | 1990-02-15 | 1992-08-11 | National Semiconductor Corporation | Built-in self test for integrated circuit memory |
US5383143A (en) * | 1994-03-30 | 1995-01-17 | Motorola, Inc. | Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit stream and method of operation |
US5471482A (en) * | 1994-04-05 | 1995-11-28 | Unisys Corporation | VLSI embedded RAM test |
US5570035A (en) * | 1995-01-31 | 1996-10-29 | The United States Of America As Represented By The Secretary Of The Army | Built-in self test indicator for an integrated circuit package |
US5574733A (en) * | 1995-07-25 | 1996-11-12 | Intel Corporation | Scan-based built-in self test (BIST) with automatic reseeding of pattern generator |
KR100412589B1 (ko) * | 1996-07-05 | 2004-04-06 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체 회로 시스템, 반도체 집적회로의 검사방법 및 그 검사계열의 생성방법 |
US5757203A (en) * | 1996-10-16 | 1998-05-26 | Hewlett-Packard Company | Multiple on-chip IDDQ monitors |
US5701308A (en) * | 1996-10-29 | 1997-12-23 | Lockheed Martin Corporation | Fast bist architecture with flexible standard interface |
US6208477B1 (en) * | 1997-06-06 | 2001-03-27 | Western Digital Corporation | Hard disk drive having a built-in self-test for measuring non-linear signal distortion |
US6272653B1 (en) * | 1997-11-14 | 2001-08-07 | Intrinsity, Inc. | Method and apparatus for built-in self-test of logic circuitry |
JP2000011691A (ja) * | 1998-06-16 | 2000-01-14 | Mitsubishi Electric Corp | 半導体試験装置 |
US6456101B2 (en) * | 1999-04-07 | 2002-09-24 | Agere Systems Guardian Corp. | Chip-on-chip testing using BIST |
US6684358B1 (en) * | 1999-11-23 | 2004-01-27 | Janusz Rajski | Decompressor/PRPG for applying pseudo-random and deterministic test patterns |
JP3434762B2 (ja) * | 1999-12-27 | 2003-08-11 | エヌイーシーマイクロシステム株式会社 | 半導体集積回路 |
US6760873B1 (en) * | 2000-09-28 | 2004-07-06 | Lsi Logic Corporation | Built-in self test for speed and timing margin for a source synchronous IO interface |
US6829728B2 (en) * | 2000-11-13 | 2004-12-07 | Wu-Tung Cheng | Full-speed BIST controller for testing embedded synchronous memories |
JP2002181893A (ja) * | 2000-12-11 | 2002-06-26 | Mitsubishi Electric Corp | 半導体装置の検査方法および検査装置 |
US6757857B2 (en) * | 2001-04-10 | 2004-06-29 | International Business Machines Corporation | Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test |
US6701476B2 (en) * | 2001-05-29 | 2004-03-02 | Motorola, Inc. | Test access mechanism for supporting a configurable built-in self-test circuit and method thereof |
US6934900B1 (en) * | 2001-06-25 | 2005-08-23 | Global Unichip Corporation | Test pattern generator for SRAM and DRAM |
US6928638B2 (en) * | 2001-08-07 | 2005-08-09 | Intel Corporation | Tool for generating a re-generative functional test |
-
2003
- 2003-06-24 EP EP03425405A patent/EP1491906B1/de not_active Expired - Fee Related
- 2003-06-24 DE DE60313860T patent/DE60313860D1/de not_active Expired - Fee Related
-
2004
- 2004-06-24 US US10/876,372 patent/US7246288B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7246288B2 (en) | 2007-07-17 |
EP1491906A1 (de) | 2004-12-29 |
EP1491906B1 (de) | 2007-05-16 |
US20050034041A1 (en) | 2005-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60313860D1 (de) | Integrierte Schaltung mit verbesserter BIST-Schaltung zur Ausführung einer strukturierten Prüfung | |
TW200626917A (en) | Low cost test for IC's or electrical modules using standard reconfigurable logic devices | |
DE602006013339D1 (de) | Ic-testverfahren und vorrichtung | |
ATE424566T1 (de) | Integrierte schaltung und verfahren zur gesicherten prüfung | |
DE602006009277D1 (de) | Testfähige integrierte schaltung und system in einer verpackung | |
EP1717653A3 (de) | Sicherheitsvorrichtung | |
WO2008114701A1 (ja) | 試験装置および電子デバイス | |
ATE408152T1 (de) | Prüfung von schaltungen mit mehreren taktdomänen | |
ATE521902T1 (de) | Integrierte halbleiterschaltung und verfahren zur speicherung und wiederherstellung des inneren zustandes derselben | |
TW200700740A (en) | Method for using internal semiconductor junctions to aid in non-contact testing | |
TW200629284A (en) | Semiconductor memory device and method of testing the same | |
DE602006012082D1 (de) | Ic-testverfahren und vorrichtung | |
DE60329709D1 (de) | Rprogramm-hörgerät | |
DE602006013600D1 (de) | Testen einer integrierten schaltung mit mehreren taktdomänen | |
TW200608409A (en) | Testing device and testing method | |
TW200717276A (en) | Development of assertions for integrated circuit design simulation | |
DE602004018918D1 (de) | Automatisches testsystem mit leicht modifizierter software | |
DE602006010915D1 (de) | Onchip-prüfschaltung für einen eingebetteten komparator | |
WO2006071668A3 (en) | Pin electronics with high voltage functionality | |
ATE329326T1 (de) | Vorrichtung zur ermittlung des energiezustandes eines energiespeichers eines mobilen datenträgers | |
EP1612573A3 (de) | Prüfschaltung und integrierte Halbleiterschaltung zur Durchführung der Überprüfung von Knotenverbindungen | |
WO2001073457A3 (en) | Controllable and testable oscillator apparatus for an integrated circuit | |
ATE420373T1 (de) | Schaltungsanordnung und verfahren zum prüfen einer in der schaltungsanordnung bereitgestellten anwendungsschaltung | |
TW200631025A (en) | Method and system for timing measurement of embedded macro module | |
DE602005014264D1 (de) | Adaptive speicherkalibration unter verwendung von bins |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8339 | Ceased/non-payment of the annual fee |