ATE424566T1 - Integrierte schaltung und verfahren zur gesicherten prüfung - Google Patents
Integrierte schaltung und verfahren zur gesicherten prüfungInfo
- Publication number
- ATE424566T1 ATE424566T1 AT04804390T AT04804390T ATE424566T1 AT E424566 T1 ATE424566 T1 AT E424566T1 AT 04804390 T AT04804390 T AT 04804390T AT 04804390 T AT04804390 T AT 04804390T AT E424566 T1 ATE424566 T1 AT E424566T1
- Authority
- AT
- Austria
- Prior art keywords
- integrated circuit
- security
- security mode
- defining
- request
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2004/014804 WO2006053586A1 (en) | 2004-11-22 | 2004-11-22 | Integrated circuit and a method for secure testing |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE424566T1 true ATE424566T1 (de) | 2009-03-15 |
Family
ID=34960219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT04804390T ATE424566T1 (de) | 2004-11-22 | 2004-11-22 | Integrierte schaltung und verfahren zur gesicherten prüfung |
Country Status (6)
Country | Link |
---|---|
US (1) | US8379861B2 (de) |
EP (1) | EP1817595B1 (de) |
AT (1) | ATE424566T1 (de) |
DE (1) | DE602004019827D1 (de) |
TW (1) | TW200623780A (de) |
WO (1) | WO2006053586A1 (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB0615392D0 (en) * | 2006-08-03 | 2006-09-13 | Wivenhoe Technology Ltd | Pseudo random number circuitry |
WO2009004506A1 (en) * | 2007-07-05 | 2009-01-08 | Nxp B.V. | Method for the improvement of microprocessor security |
KR101497456B1 (ko) * | 2008-04-29 | 2015-03-02 | 삼성전자주식회사 | 전기퓨즈 회로를 갖는 보안 회로 및 보안 키 프로그램 방법 |
US8332641B2 (en) * | 2009-01-30 | 2012-12-11 | Freescale Semiconductor, Inc. | Authenticated debug access for field returns |
US8341472B2 (en) | 2010-06-25 | 2012-12-25 | Via Technologies, Inc. | Apparatus and method for tamper protection of a microprocessor fuse array |
US8429471B2 (en) | 2010-06-25 | 2013-04-23 | Via Technologies, Inc. | Microprocessor apparatus and method for securing a programmable fuse array |
US8242800B2 (en) * | 2010-06-25 | 2012-08-14 | Via Technologies, Inc. | Apparatus and method for override access to a secured programmable fuse array |
US10923204B2 (en) * | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
US9390278B2 (en) | 2012-09-14 | 2016-07-12 | Freescale Semiconductor, Inc. | Systems and methods for code protection in non-volatile memory systems |
US9323633B2 (en) * | 2013-03-28 | 2016-04-26 | Stmicroelectronics, Inc. | Dual master JTAG method, circuit, and system |
US20140344960A1 (en) * | 2013-05-17 | 2014-11-20 | Lsi Corporation | Selective control of on-chip debug circuitry of embedded processors |
US9224012B2 (en) * | 2013-05-20 | 2015-12-29 | Advanced Micro Devices, Inc. | Debug functionality in a secure computing environment |
US9436844B2 (en) * | 2013-08-29 | 2016-09-06 | Microsoft Technology Licensing, Llc | Access enablement security circuit |
KR102066661B1 (ko) * | 2013-09-02 | 2020-01-15 | 삼성전자 주식회사 | 스캔-체인으로 연결된 플립-플롭들의 값들을 jtag 인터페이스를 이용하여 재구성할 수 있는 집적 회로, 이의 동작 방법, 및 상기 집적 회로를 포함하는 장치들 |
US9716708B2 (en) | 2013-09-13 | 2017-07-25 | Microsoft Technology Licensing, Llc | Security certificates for system-on-chip security |
US9721100B2 (en) * | 2014-06-27 | 2017-08-01 | Intel Corporation | Technologies for protected hardware function monitoring and forensics |
KR102251812B1 (ko) | 2015-01-26 | 2021-05-13 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 동작 방법 |
GB201522244D0 (en) * | 2015-12-16 | 2016-01-27 | Nagravision Sa | Hardware integrity check |
US10095889B2 (en) * | 2016-03-04 | 2018-10-09 | Altera Corporation | Techniques for protecting security features of integrated circuits |
US11615859B2 (en) | 2017-04-14 | 2023-03-28 | Attopsemi Technology Co., Ltd | One-time programmable memories with ultra-low power read operation and novel sensing scheme |
US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
US10770160B2 (en) | 2017-11-30 | 2020-09-08 | Attopsemi Technology Co., Ltd | Programmable resistive memory formed by bit slices from a standard cell library |
US10613955B2 (en) * | 2017-12-28 | 2020-04-07 | Intel Corporation | Platform debug and testing with secured hardware |
US10984108B2 (en) | 2018-10-05 | 2021-04-20 | International Business Machines Corporation | Trusted computing attestation of system validation state |
CN110716125A (zh) * | 2019-10-08 | 2020-01-21 | 东信和平科技股份有限公司 | 一种支持crc校验的智能卡的寿命测试方法和*** |
US11636907B2 (en) | 2020-06-30 | 2023-04-25 | Nuvoton Technology Corporation | Integrity verification of lifecycle-state memory using multi-threshold supply voltage detection |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357572A (en) * | 1992-09-22 | 1994-10-18 | Hughes Aircraft Company | Apparatus and method for sensitive circuit protection with set-scan testing |
JPH0855023A (ja) * | 1994-07-25 | 1996-02-27 | Motorola Inc | データ処理システムおよびその方法 |
US5530753A (en) * | 1994-08-15 | 1996-06-25 | International Business Machines Corporation | Methods and apparatus for secure hardware configuration |
US5892900A (en) * | 1996-08-30 | 1999-04-06 | Intertrust Technologies Corp. | Systems and methods for secure transaction management and electronic rights protection |
EP0743603B1 (de) | 1995-05-18 | 2002-10-02 | Hewlett-Packard Company, A Delaware Corporation | Integrierte Halbleiterschaltungsanordnung zum Schutz mehrerer Hilfsmittel in einer elektronischen Einheit |
FR2751461B1 (fr) * | 1996-07-22 | 1998-11-06 | Sgs Thomson Microelectronics | Dispositif de controle de finalite de test |
US5898776A (en) * | 1996-11-21 | 1999-04-27 | Quicklogic Corporation | Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array |
FR2818847A1 (fr) * | 2000-12-26 | 2002-06-28 | St Microelectronics Sa | Circuit logique a polarite variable |
US7165180B1 (en) * | 2001-11-27 | 2007-01-16 | Vixs Systems, Inc. | Monolithic semiconductor device for preventing external access to an encryption key |
US7266848B2 (en) * | 2002-03-18 | 2007-09-04 | Freescale Semiconductor, Inc. | Integrated circuit security and method therefor |
US7185249B2 (en) * | 2002-04-30 | 2007-02-27 | Freescale Semiconductor, Inc. | Method and apparatus for secure scan testing |
US6807660B1 (en) * | 2002-10-01 | 2004-10-19 | Sequence Design, Inc. | Vectorless instantaneous current estimation |
EP1560033A1 (de) * | 2004-01-29 | 2005-08-03 | STMicroelectronics S.A. | Integrierte Schaltung mit sicherem Testmodus mittels Initialisierung des Testmodus |
US8332641B2 (en) * | 2009-01-30 | 2012-12-11 | Freescale Semiconductor, Inc. | Authenticated debug access for field returns |
-
2004
- 2004-11-22 AT AT04804390T patent/ATE424566T1/de not_active IP Right Cessation
- 2004-11-22 DE DE602004019827T patent/DE602004019827D1/de active Active
- 2004-11-22 US US11/719,883 patent/US8379861B2/en active Active
- 2004-11-22 EP EP04804390A patent/EP1817595B1/de not_active Not-in-force
- 2004-11-22 WO PCT/EP2004/014804 patent/WO2006053586A1/en active Application Filing
-
2005
- 2005-11-15 TW TW094140131A patent/TW200623780A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
WO2006053586A1 (en) | 2006-05-26 |
EP1817595A1 (de) | 2007-08-15 |
US20090296933A1 (en) | 2009-12-03 |
EP1817595B1 (de) | 2009-03-04 |
US8379861B2 (en) | 2013-02-19 |
DE602004019827D1 (de) | 2009-04-16 |
TW200623780A (en) | 2006-07-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |