DE60211190D1 - Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende struktur - Google Patents
Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende strukturInfo
- Publication number
- DE60211190D1 DE60211190D1 DE60211190T DE60211190T DE60211190D1 DE 60211190 D1 DE60211190 D1 DE 60211190D1 DE 60211190 T DE60211190 T DE 60211190T DE 60211190 T DE60211190 T DE 60211190T DE 60211190 D1 DE60211190 D1 DE 60211190D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor coating
- coating structure
- corresponding structure
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011248 coating agent Substances 0.000 title 1
- 238000000576 coating method Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7602—Making of isolation regions between components between components manufactured in an active substrate comprising SiC compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US32875901P | 2001-10-12 | 2001-10-12 | |
US328759P | 2001-10-12 | ||
PCT/EP2002/011423 WO2003034484A2 (en) | 2001-10-12 | 2002-10-11 | A method for forming a layered semiconductor structure and corresponding structure |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60211190D1 true DE60211190D1 (de) | 2006-06-08 |
DE60211190T2 DE60211190T2 (de) | 2006-10-26 |
Family
ID=23282315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60211190T Expired - Lifetime DE60211190T2 (de) | 2001-10-12 | 2002-10-11 | Verfahren zur herstellung einer halbleiter-schichtstruktur und entsprechende struktur |
Country Status (8)
Country | Link |
---|---|
US (1) | US7294564B2 (de) |
EP (1) | EP1435110B1 (de) |
JP (1) | JP4225905B2 (de) |
KR (1) | KR100618103B1 (de) |
CN (1) | CN1316586C (de) |
AU (1) | AU2002340555A1 (de) |
DE (1) | DE60211190T2 (de) |
WO (1) | WO2003034484A2 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2843061B1 (fr) * | 2002-08-02 | 2004-09-24 | Soitec Silicon On Insulator | Procede de polissage de tranche de materiau |
US7749881B2 (en) | 2005-05-18 | 2010-07-06 | Intermolecular, Inc. | Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region |
US8882914B2 (en) | 2004-09-17 | 2014-11-11 | Intermolecular, Inc. | Processing substrates using site-isolated processing |
US7390739B2 (en) | 2005-05-18 | 2008-06-24 | Lazovsky David E | Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region |
US8084400B2 (en) | 2005-10-11 | 2011-12-27 | Intermolecular, Inc. | Methods for discretized processing and process sequence integration of regions of a substrate |
US7879710B2 (en) | 2005-05-18 | 2011-02-01 | Intermolecular, Inc. | Substrate processing including a masking layer |
WO2006058034A2 (en) | 2004-11-22 | 2006-06-01 | Intermolecular, Inc. | Molecular self-assembly in substrate processing |
DE102005024073A1 (de) * | 2005-05-25 | 2006-11-30 | Siltronic Ag | Halbleiter-Schichtstruktur und Verfahren zur Herstellung einer Halbleiter-Schichtstruktur |
US7955436B2 (en) | 2006-02-24 | 2011-06-07 | Intermolecular, Inc. | Systems and methods for sealing in site-isolated reactors |
US7902063B2 (en) | 2005-10-11 | 2011-03-08 | Intermolecular, Inc. | Methods for discretized formation of masking and capping layers on a substrate |
CN101385138B (zh) * | 2006-01-12 | 2011-05-11 | Nxp股份有限公司 | 具有正面衬底接触的绝缘体上半导体器件的制造方法 |
US8772772B2 (en) | 2006-05-18 | 2014-07-08 | Intermolecular, Inc. | System and method for increasing productivity of combinatorial screening |
EP1901345A1 (de) * | 2006-08-30 | 2008-03-19 | Siltronic AG | Mehrlagiger Halbleiterwafer und entsprechendes Verfahren |
US8011317B2 (en) | 2006-12-29 | 2011-09-06 | Intermolecular, Inc. | Advanced mixing system for integrated tool having site-isolated reactors |
JP2009149481A (ja) * | 2007-12-21 | 2009-07-09 | Siltronic Ag | 半導体基板の製造方法 |
DE102008006745B3 (de) * | 2008-01-30 | 2009-10-08 | Siltronic Ag | Verfahren zur Herstellung einer Halbleiterstruktur |
EP2172967A1 (de) | 2008-08-04 | 2010-04-07 | Siltronic AG | Verfahren zur Herstellung von Siliciumcarbid |
US7868306B2 (en) * | 2008-10-02 | 2011-01-11 | Varian Semiconductor Equipment Associates, Inc. | Thermal modulation of implant process |
US10049914B2 (en) | 2015-11-20 | 2018-08-14 | Infineon Technologies Ag | Method for thinning substrates |
EP4135006A1 (de) | 2021-08-13 | 2023-02-15 | Siltronic AG | Verfahren zur herstellung eines substratwafers zum darauf erstellen von gruppe-iii-v-vorrichtungen und substratwafer zum darauf erstellen von gruppe-iii-v-vorrichtungen |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622382A (en) * | 1969-05-05 | 1971-11-23 | Ibm | Semiconductor isolation structure and method of producing |
KR100312568B1 (ko) * | 1996-04-18 | 2003-06-19 | 마쯔시다덴기산교 가부시키가이샤 | Sic 소자 및 그 제조방법 |
JP3958404B2 (ja) * | 1997-06-06 | 2007-08-15 | 三菱電機株式会社 | 横型高耐圧素子を有する半導体装置 |
ES2165315B1 (es) * | 2000-03-31 | 2003-08-01 | Consejo Superior Investigacion | Procedimiento de fabricacion de capas de carburo de silicio (sic) mediante implantacion ionica de carbono y recocidos. |
-
2002
- 2002-10-11 AU AU2002340555A patent/AU2002340555A1/en not_active Abandoned
- 2002-10-11 JP JP2003537114A patent/JP4225905B2/ja not_active Expired - Fee Related
- 2002-10-11 US US10/492,329 patent/US7294564B2/en not_active Expired - Fee Related
- 2002-10-11 CN CNB028201957A patent/CN1316586C/zh not_active Expired - Fee Related
- 2002-10-11 KR KR1020047005378A patent/KR100618103B1/ko not_active IP Right Cessation
- 2002-10-11 EP EP02774705A patent/EP1435110B1/de not_active Expired - Fee Related
- 2002-10-11 WO PCT/EP2002/011423 patent/WO2003034484A2/en active IP Right Grant
- 2002-10-11 DE DE60211190T patent/DE60211190T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7294564B2 (en) | 2007-11-13 |
EP1435110A2 (de) | 2004-07-07 |
CN1316586C (zh) | 2007-05-16 |
CN1698193A (zh) | 2005-11-16 |
JP4225905B2 (ja) | 2009-02-18 |
DE60211190T2 (de) | 2006-10-26 |
AU2002340555A1 (en) | 2003-04-28 |
WO2003034484A3 (en) | 2003-09-18 |
KR20050035156A (ko) | 2005-04-15 |
US20040248390A1 (en) | 2004-12-09 |
KR100618103B1 (ko) | 2006-08-29 |
JP2005506699A (ja) | 2005-03-03 |
WO2003034484A2 (en) | 2003-04-24 |
EP1435110B1 (de) | 2006-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: UNIVERSITAET AUGSBURG, 86159 AUGSBURG, DE |