CN101385138B - 具有正面衬底接触的绝缘体上半导体器件的制造方法 - Google Patents

具有正面衬底接触的绝缘体上半导体器件的制造方法 Download PDF

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CN101385138B
CN101385138B CN2007800022850A CN200780002285A CN101385138B CN 101385138 B CN101385138 B CN 101385138B CN 2007800022850 A CN2007800022850 A CN 2007800022850A CN 200780002285 A CN200780002285 A CN 200780002285A CN 101385138 B CN101385138 B CN 101385138B
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派比·A·泽斯特拉
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Abstract

一种在半导体器件中形成衬底接触的方法，包括如下步骤：提供半导体基础衬底(2)，其具有掩埋氧化(BOX)层(4)以及在所述BOX层(4)上的一薄有源半导体层(103)，在所述有源半导体层(103)和BOX层(4)中形成沟槽(104)直至下面的半导体基础衬底(2)，以及之后在剩余的有源半导体层(103)上和沟槽(104)中沉积另一有源半导体(外延)层(6)以形成所述衬底接触。在晶片上对应划线(106)的位置处蚀刻所述沟槽(104)。

Description

具有正面衬底接触的绝缘体上半导体器件的制造方法 
技术领域
本发明涉及一种具有正面衬底接触的绝缘体上半导体(SOI)器件的制造方法。 
背景技术
通常希望有源半导体器件与下层半导体衬底和相邻有源器件完全电绝缘。 
通常利用绝缘体上半导体(SOI)衬底实现有源器件的垂直绝缘，所述绝缘体上半导体(SOI)衬底，参照图1的图示，包括基础半导体(典型地是硅)衬底2，其具有形成于其上表面的一掩埋绝缘体(典型地是氧化硅)或BOX层4，以及一形成于所述BOX层4上的有源结合半导体(典型地是硅)层6。有源器件(晶体管)制造于所述绝缘层4顶部上的有源半导体层6中。 
在许多应用中，需要将所述基础半导体衬底2接地或使其接地，且为实现上述目的，就需要到所述衬底2的接触。在这方面，提出两个常规解决方案：正面和背面接触，上述两者的构造是本领域公知的。 
通过背面接触，在所述有源器件经过加工后，所述接触从晶片6的后侧(相对于所述有源层6)提供给所述衬底2，背面接触速度特性有可能不足(特别是在HV应用中)，这是由于经由所述衬底的BOX下面的电荷充电和放电。另一方面，通过正面接触，经由所述有源层6和所述BOX层4从晶片的正表面或顶表面至所述基础衬底2提供接触，例如日本专利申请第6-151576中所阐述的。然而，这种选择的一个主要缺点在于深接触蚀刻，因为其大多在工艺流程最后进行。 
发明内容
因此，本发明的一个目的是提供一种制造绝缘体上半导体(SOI) 器件的方法，其具有正面衬底接触，其中对于形成正面衬底接触所需的接触蚀刻相对于现有技术方法显著地简化了。 
根据本发明，提供一种制造绝缘体上半导体器件的方法，所述方法包括提供半导体晶片，该半导体晶片包括半导体基础衬底、在其上的绝缘材料层以及在所述绝缘材料层上的第一有源半导体层，其中在所述晶片上设置至少一个划线(scribe lane)，所述方法进一步包括在所述晶片的对应所述至少一个划线的位置处，通过在所述第一和有源半导体层和所述绝缘材料层中形成直至所述基础衬底的开口，以及接着在所述第一有源半导体层上和所述开口中沉积第二有源半导体层，形成衬底接触。 
因此，在所述第二有源半导体(外延)层沉积之前，通过在所述第一(相对薄)有源半导体层中对应所述至少一个划线的位置处形成一个开口，以便接着在沉积所述第二有源半导体层时，用半导体材料填充所述开口以形成衬底接触，实现以上提及的目的。一个吸杂位置有利地形成于所述有源半导体层的所述衬底接触区域中。 
所述开口可以包括沟槽。可替换地，所述开口可以包括接触孔且更优选地，所述开口可以包括接触孔阵列。 
本发明还涉及形成于半导体晶片上的集成电路，所述半导体晶片包括半导体基础衬底、在其上形成的绝缘材料层以及在所述绝缘材料层上的第一有源半导体层，所述半导体晶片具有至少两个形成于其上的管芯垫，通过至少一个划线隔离所述至少两个管芯垫，其中在所述晶片上的对应所述至少一个划线的位置处，通过在所述第一有源半导体层和所述绝缘材料层中形成一个直至所述基础衬底的开口，以及接着在所述第一有源半导体层上和所述开口中沉积第二有源半导体层，在所述绝缘材料层中形成衬底接触，其中在形成所述衬底接触之后，在所述有源层中形成一个或多个半导体器件。 
在这种(典型的)情况下，其中在所述半导体晶片周围提供一个或多个划线，因此，可以提供与其相关的一个相应的环形衬底接触。 
本发明的这些和其他的方面将参照于此描述的实施例的说明而变得明显。
附图说明
现在，将仅通过例子和参考附图来描述本发明的实施例，其中： 
图1是绝缘体上半导体(SOI)衬底的截面示意图； 
图2a到2d是根据本发明的一个示例性实施例所制造的半导体器件的不同制造阶段的截面示意图；以及 
图3是说明其中具有划线的半导体晶片的示意图。 
具体实施方式
参照图2a，根据本发明的一个示例性实施例的器件制造方法开始于半导体(典型地是硅)基础衬底2，其上具有一掩埋氧化(BOX)层4，其上提供一薄Si层103。所述BOX层典型地包括氧化硅。一抗蚀剂层提供在所述Si层103上且接着被图案化。接着，在划线106的位置处，穿过所述薄Si层103和BOX层4蚀刻一沟槽(或接触孔阵列)104，如图2b所示(为了简化，省略所述基础衬底2的描述)。 
参照图3，划线106是等宽线，其水平和垂直延伸穿过半导体晶片100。它们典型地在所述晶片100的***区域内部形成规则网格且不延伸到边缘。 
接着，参照图2c，移除标记层102，并且通过例如外延工艺沉积有源半导体层6。所述有源层6(例如1.3μm)可以是Si、Si-Ge、Si-Ge-C或任何合适的半导体材料，在一个示例性实施例中，可以对所述有源层进行P掺杂以提供器件的N阱背底。因此，根据本发明，在工艺开始时，形成其中具有划线的衬底接触以及，以这种方式，如果需要(取决于沟槽和划线的宽度)，可以获得围绕集成电路或晶片的环形(保护环)衬底接触。 
吸杂(gettering)的定义是从晶片的有源电路区域移除导致器件退化的杂质的工艺。吸杂是增加VLSI制造良率的一个重要因素，可以在晶体生长期间或随后的晶片制造步骤中实施。从器件区域移除杂质的吸杂的常规机制可以描述为如下步骤：1)要被吸杂的杂质从其中含有它们的任何沉淀物释放进固溶体；2)它们经历穿过硅的扩散；3)它们在远离器件区的区域中被例如位错或沉淀物的缺陷俘获。吸杂大体有两个分类，即，非本征和本征。非本征吸杂指的是使用外部方式在硅晶格中形成损坏或应力的吸杂，其方式使得形成了俘获杂质所需的延伸缺陷。这些化学活性俘获位置通常位于晶片背面。 
本征吸杂解释为包括由从硅晶片溢出的过饱和氧气沉淀形成的杂质俘获位置的吸杂。所述过饱和氧气沉淀形成持续生长的聚簇，在该情况下将引入应力到晶片。 
最后，这些应力到达需要释放的点。因此形成位错环或堆垛层错以提供必要的应力消除。这些位错或层错接着用作用于杂质的俘获位置。 
因此，作为本发明的另一优点，在所述SOI层中的杂质的扩散和沉淀不会被BOX阻挡，而是延伸到基础衬底，且此外，在工艺流程中发生非常早。 
一旦形成所述衬底接触，则剩余的器件工艺步骤可以正常实施，以制造完整的半导体器件，如图2d中所说明的那样。 
总而言之，本发明的方法提供的优点包括： 
包括晶片有关的机械应力释放(以补偿弯曲、扭曲)； 
-显著提升吸杂性能； 
-提供生长不同材料外延层的可能性，而不仅仅是Si，例如Si-Ge或Si-Ge-C等；以及 
-可以自动形成围绕管芯的保护环形状的衬底接触。 
应当注意到，上述实施例用于阐述而并非限制本发明，且本领域技术人员将能够在不被背离由附加的权利要求所定义的本发明的范围下，设计出许多不同的实例。在这些权利要求中，任何位于括号中的参考标记将不能解释为对权利要求的限制。词语“包含”和“包括”等不排除不同于那些在任何权利要求中或说明书全文中列出的元件或步骤的存在。所提及的单数元件不排除所提及的这种元件的复数且反之亦然。本发明可以借助于硬件实现，所述硬件包括几个分离的元件，以及可以借助于合适的程序控制计算机实现。在一个器件中要求列举几个方式，这几个方式可以包含一个和硬件的相同的零件。重要的事实是在彼此不同的从属权利要求中所述的某些措施不表示不能有利地使用这些措施的组合。

Claims (7)

1.一种制造绝缘体上半导体器件的方法，所述方法包括提供半导体晶片(100)，该半导体晶片包括半导体基础衬底(2)、在半导体基础衬底上的绝缘材料层(4)以及在所述绝缘材料层(4)上的第一有源半导体层(103)，其中至少一个划线(106)设置在所述晶片(100)上，所述方法进一步包括在所述晶片的对应所述至少一个划线(106)的位置处，通过在所述第一有源半导体层(103)和所述绝缘材料层(4)中形成直至所述基础衬底(2)的开口(104)，以及接着在所述第一有源半导体层(103)以及所述绝缘层(4)上以及所述开口(104)中沉积第二有源半导体层(6)，形成衬底接触。
2.根据权利要求1的方法，其中在所述衬底接触区中从所述有源半导体层(6)到所述基础衬底(2)形成吸杂通道。
3.根据权利要求1的方法，其中所述开口(104)包括沟槽。
4.根据权利要求1的方法，其中所述开口(104)包括接触孔。
5.根据权利要求4的方法，其中在对应所述至少一个划线(106)的位置处，在所述第一有源半导体层(103)和所述绝缘材料层(4)中形成直至所述基础衬底(2)的接触孔阵列，以及接着在所述第一有源半导体层(103)和所述绝缘材料层(4)上以及在所述接触孔阵列中沉积所述第二有源半导体层(6)。
6.一种形成在半导体晶片上的集成电路，所述半导体晶片包括半导体基础衬底(2)、形成在半导体基础衬底上的绝缘材料层(4)以及在所述绝缘材料层(4)上的第一有源半导体层(103)，所述半导体晶片(100)具有至少两个形成于其上的管芯垫，所述至少两个管芯垫通过至少一个划线(106)隔离，其中在所述晶片上的对应所述至少一个划线(106)的位置处，通过在所述第一有源半导体层(103)和所述绝缘材料层(4)中形成直至所述基础衬底(2)的开口(104)，以及接着在所述第一有源半导体层(103)上和所述开口(104)中沉积第二有源半导体层(6)，在所述绝缘材料层(4)中形成衬底接触，其中在形成所述衬底接触之后，在所述有源层中一个或多个半导体器件形成。
7.根据权利要求6的集成电路，其中在所述半导体晶片(100)周围设置一个或多个划线以及相关地设置相应的环形衬底接触。
CN2007800022850A 2006-01-12 2007-01-10 具有正面衬底接触的绝缘体上半导体器件的制造方法 Expired - Fee Related CN101385138B (zh)

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CN107204366A (zh) * 2016-03-17 2017-09-26 英飞凌科技股份有限公司 制造具有晶体管单元的半导体器件的方法以及半导体器件

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CN101385138A (zh) 2009-03-11
US20100163993A1 (en) 2010-07-01
WO2007080545A1 (en) 2007-07-19

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