DE602007012131D1 - System und verfahren zur verwendung eines funktionierenden globalen vorgeschichteregisters - Google Patents
System und verfahren zur verwendung eines funktionierenden globalen vorgeschichteregistersInfo
- Publication number
- DE602007012131D1 DE602007012131D1 DE602007012131T DE602007012131T DE602007012131D1 DE 602007012131 D1 DE602007012131 D1 DE 602007012131D1 DE 602007012131 T DE602007012131 T DE 602007012131T DE 602007012131 T DE602007012131 T DE 602007012131T DE 602007012131 D1 DE602007012131 D1 DE 602007012131D1
- Authority
- DE
- Germany
- Prior art keywords
- branch
- history information
- register
- branch history
- global historical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/556,244 US7984279B2 (en) | 2006-11-03 | 2006-11-03 | System and method for using a working global history register |
PCT/US2007/082538 WO2008055045A1 (en) | 2006-11-03 | 2007-10-25 | A system and method for using a working global history register |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602007012131D1 true DE602007012131D1 (de) | 2011-03-03 |
Family
ID=38926137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602007012131T Active DE602007012131D1 (de) | 2006-11-03 | 2007-10-25 | System und verfahren zur verwendung eines funktionierenden globalen vorgeschichteregisters |
Country Status (8)
Country | Link |
---|---|
US (1) | US7984279B2 (de) |
EP (1) | EP2084602B1 (de) |
JP (1) | JP5209633B2 (de) |
KR (1) | KR101081674B1 (de) |
CN (1) | CN101529378B (de) |
AT (1) | ATE496329T1 (de) |
DE (1) | DE602007012131D1 (de) |
WO (1) | WO2008055045A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5145809B2 (ja) * | 2007-07-31 | 2013-02-20 | 日本電気株式会社 | 分岐予測装置、ハイブリッド分岐予測装置、プロセッサ、分岐予測方法、及び分岐予測制御プログラム |
US20100031011A1 (en) * | 2008-08-04 | 2010-02-04 | International Business Machines Corporation | Method and apparatus for optimized method of bht banking and multiple updates |
US8078851B2 (en) * | 2008-12-18 | 2011-12-13 | Faraday Technology Corp. | Processor and method for recovering global history shift register and return address stack thereof by determining a removal range of a branch recovery table |
JP5367416B2 (ja) * | 2009-03-04 | 2013-12-11 | 光洋サーモシステム株式会社 | 搬送ロボット装置 |
US20140195790A1 (en) * | 2011-12-28 | 2014-07-10 | Matthew C. Merten | Processor with second jump execution unit for branch misprediction |
US9229723B2 (en) | 2012-06-11 | 2016-01-05 | International Business Machines Corporation | Global weak pattern history table filtering |
US9858081B2 (en) * | 2013-08-12 | 2018-01-02 | International Business Machines Corporation | Global branch prediction using branch and fetch group history |
US10372590B2 (en) | 2013-11-22 | 2019-08-06 | International Business Corporation | Determining instruction execution history in a debugger |
JP5863855B2 (ja) | 2014-02-26 | 2016-02-17 | ファナック株式会社 | 分岐命令を高速に処理するためのインストラクションキャッシュを有するプログラマブルコントローラ |
CN113721985B (zh) * | 2021-11-02 | 2022-02-08 | 超验信息科技(长沙)有限公司 | Risc-v向量寄存器分组设置方法、装置及电子设备 |
US20230315468A1 (en) * | 2022-03-30 | 2023-10-05 | Advanced Micro Devices, Inc. | Enforcing consistency across redundant tagged geometric (tage) branch histories |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5155818A (en) * | 1988-09-28 | 1992-10-13 | Data General Corporation | Unconditional wide branch instruction acceleration |
US5604877A (en) * | 1994-01-04 | 1997-02-18 | Intel Corporation | Method and apparatus for resolving return from subroutine instructions in a computer processor |
JPH08106387A (ja) | 1994-10-06 | 1996-04-23 | Oki Electric Ind Co Ltd | 命令プリフェッチ回路及びキャッシュ装置 |
US5918245A (en) * | 1996-03-13 | 1999-06-29 | Sun Microsystems, Inc. | Microprocessor having a cache memory system using multi-level cache set prediction |
US5860017A (en) * | 1996-06-28 | 1999-01-12 | Intel Corporation | Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction |
US5838962A (en) * | 1997-04-09 | 1998-11-17 | Hewlett-Packard Company | Interrupt driven dynamic adjustment of branch predictions |
US6157988A (en) * | 1997-08-01 | 2000-12-05 | Micron Technology, Inc. | Method and apparatus for high performance branching in pipelined microsystems |
US6418530B2 (en) | 1999-02-18 | 2002-07-09 | Hewlett-Packard Company | Hardware/software system for instruction profiling and trace selection using branch history information for branch predictions |
US6622240B1 (en) * | 1999-06-18 | 2003-09-16 | Intrinsity, Inc. | Method and apparatus for pre-branch instruction |
SE0003446L (sv) * | 2000-09-27 | 2002-03-28 | Ericsson Telefon Ab L M | En pipelinemikroprocessor och ett förfarnade relaterande därtill |
US6886093B2 (en) | 2001-05-04 | 2005-04-26 | Ip-First, Llc | Speculative hybrid branch direction predictor |
US7107438B2 (en) * | 2003-02-04 | 2006-09-12 | Via Technologies, Inc. | Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions |
US20040225866A1 (en) * | 2003-05-06 | 2004-11-11 | Williamson David James | Branch prediction in a data processing system |
US20050228977A1 (en) * | 2004-04-09 | 2005-10-13 | Sun Microsystems,Inc. | Branch prediction mechanism using multiple hash functions |
US7181190B2 (en) | 2004-04-30 | 2007-02-20 | Microsoft Corporation | Method for maintaining wireless network response time while saving wireless adapter power |
WO2005119428A1 (en) * | 2004-06-02 | 2005-12-15 | Intel Corporation | Tlb correlated branch predictor and method for use therof |
US7752426B2 (en) * | 2004-08-30 | 2010-07-06 | Texas Instruments Incorporated | Processes, circuits, devices, and systems for branch prediction and other processor improvements |
US7278012B2 (en) * | 2005-06-02 | 2007-10-02 | Qualcomm Incorporated | Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions |
TW200739419A (en) * | 2006-04-07 | 2007-10-16 | Univ Feng Chia | Prediction mechanism of a program backward jump instruction |
-
2006
- 2006-11-03 US US11/556,244 patent/US7984279B2/en active Active
-
2007
- 2007-10-25 WO PCT/US2007/082538 patent/WO2008055045A1/en active Application Filing
- 2007-10-25 DE DE602007012131T patent/DE602007012131D1/de active Active
- 2007-10-25 CN CN2007800398002A patent/CN101529378B/zh not_active Expired - Fee Related
- 2007-10-25 AT AT07844606T patent/ATE496329T1/de not_active IP Right Cessation
- 2007-10-25 EP EP07844606A patent/EP2084602B1/de not_active Not-in-force
- 2007-10-25 JP JP2009536380A patent/JP5209633B2/ja not_active Expired - Fee Related
- 2007-10-25 KR KR1020097011477A patent/KR101081674B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN101529378A (zh) | 2009-09-09 |
EP2084602B1 (de) | 2011-01-19 |
JP2010509680A (ja) | 2010-03-25 |
ATE496329T1 (de) | 2011-02-15 |
KR20090089358A (ko) | 2009-08-21 |
KR101081674B1 (ko) | 2011-11-09 |
EP2084602A1 (de) | 2009-08-05 |
WO2008055045A1 (en) | 2008-05-08 |
CN101529378B (zh) | 2013-04-03 |
JP5209633B2 (ja) | 2013-06-12 |
US7984279B2 (en) | 2011-07-19 |
US20080109644A1 (en) | 2008-05-08 |
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