DE602007002637D1 - Verfahren und vorrichtung zur messung des tastverhältnisses oder relativen tastverhältnisses eines digitalen signals - Google Patents

Verfahren und vorrichtung zur messung des tastverhältnisses oder relativen tastverhältnisses eines digitalen signals

Info

Publication number
DE602007002637D1
DE602007002637D1 DE602007002637T DE602007002637T DE602007002637D1 DE 602007002637 D1 DE602007002637 D1 DE 602007002637D1 DE 602007002637 T DE602007002637 T DE 602007002637T DE 602007002637 T DE602007002637 T DE 602007002637T DE 602007002637 D1 DE602007002637 D1 DE 602007002637D1
Authority
DE
Germany
Prior art keywords
key ratio
clock signal
relative
duty cycle
measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007002637T
Other languages
English (en)
Inventor
David William Boerstler
Eskinder Hailu
Jieming Qi
Bin Wan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/383,570 external-priority patent/US7333905B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE602007002637D1 publication Critical patent/DE602007002637D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
    • G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Lock And Its Accessories (AREA)
  • Measurement Of Current Or Voltage (AREA)
DE602007002637T 2006-05-16 2007-05-16 Verfahren und vorrichtung zur messung des tastverhältnisses oder relativen tastverhältnisses eines digitalen signals Active DE602007002637D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/383,570 US7333905B2 (en) 2006-05-01 2006-05-16 Method and apparatus for measuring the duty cycle of a digital signal
US11/555,018 US7363178B2 (en) 2006-05-01 2006-10-31 Method and apparatus for measuring the relative duty cycle of a clock signal
PCT/EP2007/054767 WO2007132015A1 (en) 2006-05-16 2007-05-16 Method and apparatus for measuring the duty cycle or relative duty cycle of a digital signal

Publications (1)

Publication Number Publication Date
DE602007002637D1 true DE602007002637D1 (de) 2009-11-12

Family

ID=38375762

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007002637T Active DE602007002637D1 (de) 2006-05-16 2007-05-16 Verfahren und vorrichtung zur messung des tastverhältnisses oder relativen tastverhältnisses eines digitalen signals

Country Status (7)

Country Link
US (1) US7363178B2 (de)
EP (1) EP2027480B1 (de)
JP (1) JP4588110B2 (de)
CN (1) CN101410719B (de)
AT (1) ATE444496T1 (de)
DE (1) DE602007002637D1 (de)
WO (1) WO2007132015A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7333905B2 (en) * 2006-05-01 2008-02-19 International Business Machines Corporation Method and apparatus for measuring the duty cycle of a digital signal
US7479777B2 (en) * 2006-12-28 2009-01-20 Intel Corporation Circuitry and method to measure a duty cycle of a clock signal
GB0702597D0 (en) 2007-02-09 2007-03-21 Texas Instruments Ltd A debug circuit and a method of debugging
US8032850B2 (en) * 2007-11-12 2011-10-04 International Business Machines Corporation Structure for an absolute duty cycle measurement circuit
US7917318B2 (en) * 2007-11-20 2011-03-29 International Business Machines Corporation Structure for a duty cycle measurement circuit
CN102055444B (zh) * 2009-10-30 2013-10-16 无锡海威半导体科技有限公司 一种占空比判定电路
TWI426283B (zh) * 2010-12-22 2014-02-11 Inventec Corp 工作週期測量系統與其方法
DE102014225867A1 (de) * 2014-12-15 2016-06-16 Dr. Johannes Heidenhain Gmbh Vorrichtung und Verfahren zur Überprüfung eines Arbeitstaktsignals einer Positionsmesseinrichtung
EP3648348B1 (de) * 2018-10-29 2022-09-28 NXP USA, Inc. Arbeitszyklusüberwachungsschaltung und verfahren zur arbeitszyklusüberwachung
KR102679157B1 (ko) * 2018-10-30 2024-06-27 삼성전자주식회사 모드 레지스터 쓰기 명령을 이용하여 쓰기 클럭의 듀티 사이클의 트레이닝을 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치
US11703905B1 (en) 2022-04-26 2023-07-18 Changxin Memory Technologies, Inc. Clock generation circuit, equidistant four-phase signal generation method, and memory

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CU21488A1 (es) * 1982-07-26 1987-06-09 Inst Central De Investigacion Medidor lógico
JPS59171219A (ja) * 1983-03-17 1984-09-27 Nec Corp レベル検出回路
US4814872A (en) * 1987-06-04 1989-03-21 Tektronix, Inc. Digital video probe system
US4859944A (en) * 1987-08-25 1989-08-22 Analog Devices, Inc. Single-winding magnetometer with oscillator duty cycle measurement
JPH01123518A (ja) * 1987-11-06 1989-05-16 Nec Corp ジッタ検出回路
US5367200A (en) * 1993-11-29 1994-11-22 Northern Telecom Limited Method and apparatus for measuring the duty cycle of a digital signal
JP3576638B2 (ja) * 1994-06-09 2004-10-13 株式会社東芝 フリップフロップ装置
JP3199027B2 (ja) 1998-05-11 2001-08-13 日本電気株式会社 デューティ測定回路、データ識別システム、データ信号再生システム、デューティ測定方法、データ識別方法、及びデータ信号再生方法
US6084452A (en) * 1998-06-30 2000-07-04 Sun Microsystems, Inc Clock duty cycle control technique
US6150847A (en) * 1999-03-18 2000-11-21 Vanguard International Semiconductor Corporation Device and method for generating a variable duty cycle clock
JP2000286696A (ja) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp 分周回路
US6664834B2 (en) * 2000-12-22 2003-12-16 Intel Corporation Method for automatic duty cycle control using adaptive body bias control
US6441600B1 (en) * 2001-01-19 2002-08-27 International Business Machines Corporation Apparatus for measuring the duty cycle of a high speed clocking signal
JP3762281B2 (ja) * 2001-10-17 2006-04-05 シャープ株式会社 テスト回路及びテスト方法
US6847244B2 (en) * 2002-07-22 2005-01-25 Cirrus Logic, Inc. Variable duty cycle clock generation circuits and methods and systems using the same
KR100486268B1 (ko) * 2002-10-05 2005-05-03 삼성전자주식회사 내부에서 자체적으로 듀티싸이클 보정을 수행하는지연동기루프 회로 및 이의 듀티싸이클 보정방법
US6700530B1 (en) * 2002-10-28 2004-03-02 Saab Marine Electronics Ab Circuit and method for generation of trigger signals
US6798266B1 (en) * 2003-05-27 2004-09-28 Micrel, Incorporated Universal clock generator using delay lock loop
US7002358B2 (en) * 2003-12-10 2006-02-21 Hewlett-Packard Development Company, L.P. Method and apparatus for measuring jitter
US7151367B2 (en) * 2004-03-31 2006-12-19 Teradyne, Inc. Method of measuring duty cycle
JP2005316722A (ja) * 2004-04-28 2005-11-10 Renesas Technology Corp クロック発生回路及び半導体集積回路
JP2005322075A (ja) * 2004-05-10 2005-11-17 Matsushita Electric Ind Co Ltd クロック信号出力装置
US20060181320A1 (en) * 2005-02-11 2006-08-17 International Business Machines Corporation Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line
US7590194B2 (en) * 2005-09-27 2009-09-15 International Business Machines Corporation Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer
US7330061B2 (en) * 2006-05-01 2008-02-12 International Business Machines Corporation Method and apparatus for correcting the duty cycle of a digital signal
US7595675B2 (en) * 2006-05-01 2009-09-29 International Business Machines Corporation Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode
US7420400B2 (en) * 2006-05-01 2008-09-02 International Business Machines Corporation Method and apparatus for on-chip duty cycle measurement

Also Published As

Publication number Publication date
US7363178B2 (en) 2008-04-22
CN101410719A (zh) 2009-04-15
EP2027480A1 (de) 2009-02-25
CN101410719B (zh) 2012-01-18
ATE444496T1 (de) 2009-10-15
WO2007132015A1 (en) 2007-11-22
JP4588110B2 (ja) 2010-11-24
EP2027480B1 (de) 2009-09-30
US20070271068A1 (en) 2007-11-22
JP2009537805A (ja) 2009-10-29

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8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition