DE602004012113D1 - Befehls- und adressenbustopologie mit aufgeteiltem t-ketten-speicher - Google Patents
Befehls- und adressenbustopologie mit aufgeteiltem t-ketten-speicherInfo
- Publication number
- DE602004012113D1 DE602004012113D1 DE602004012113T DE602004012113T DE602004012113D1 DE 602004012113 D1 DE602004012113 D1 DE 602004012113D1 DE 602004012113 T DE602004012113 T DE 602004012113T DE 602004012113 T DE602004012113 T DE 602004012113T DE 602004012113 D1 DE602004012113 D1 DE 602004012113D1
- Authority
- DE
- Germany
- Prior art keywords
- dimm
- signal
- address
- dram
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Exchange Systems With Centralized Control (AREA)
- Communication Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Memory System (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US638069 | 1996-04-25 | ||
US10/638,069 US7194572B2 (en) | 2003-08-08 | 2003-08-08 | Memory system and method to reduce reflection and signal degradation |
PCT/US2004/025220 WO2005017760A2 (en) | 2003-08-08 | 2004-08-04 | Split t-chain memory command and address bus topology |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004012113D1 true DE602004012113D1 (de) | 2008-04-10 |
DE602004012113T2 DE602004012113T2 (de) | 2009-02-19 |
Family
ID=34116714
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004012113T Active DE602004012113T2 (de) | 2003-08-08 | 2004-08-04 | Befehls- und adressenbustopologie mit aufgeteiltem t-ketten-speicher |
Country Status (6)
Country | Link |
---|---|
US (1) | US7194572B2 (de) |
EP (1) | EP1652097B1 (de) |
CN (1) | CN100456275C (de) |
AT (1) | ATE387668T1 (de) |
DE (1) | DE602004012113T2 (de) |
WO (1) | WO2005017760A2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7133962B2 (en) * | 2003-09-09 | 2006-11-07 | Intel Corporation | Circulator chain memory command and address bus topology |
US20070189049A1 (en) * | 2006-02-16 | 2007-08-16 | Srdjan Djordjevic | Semiconductor memory module |
DE102008010544A1 (de) | 2008-02-22 | 2009-09-17 | Qimonda Ag | Speichermodul und Verfahren zur Speicherung digitaler Daten |
US7944726B2 (en) * | 2008-09-30 | 2011-05-17 | Intel Corporation | Low power termination for memory modules |
US8225069B2 (en) * | 2009-03-31 | 2012-07-17 | Intel Corporation | Control of on-die system fabric blocks |
JP5471631B2 (ja) * | 2010-03-10 | 2014-04-16 | セイコーエプソン株式会社 | 電子機器 |
CN104704572A (zh) * | 2012-10-31 | 2015-06-10 | 惠普发展公司,有限责任合伙企业 | 修复内存装置 |
KR101781277B1 (ko) | 2012-11-30 | 2017-09-22 | 인텔 코포레이션 | 집적 회로 패키지의 다수의 칩들에 대한 종단을 제공하는 장치, 방법 및 시스템 |
JP6434870B2 (ja) * | 2015-07-28 | 2018-12-05 | ルネサスエレクトロニクス株式会社 | 電子装置 |
US10146711B2 (en) | 2016-01-11 | 2018-12-04 | Intel Corporation | Techniques to access or operate a dual in-line memory module via multiple data channels |
CN111159082B (zh) * | 2018-11-07 | 2021-12-07 | 财团法人工业技术研究院 | 可重组式数据总线***及其方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5668834A (en) | 1993-12-28 | 1997-09-16 | Hitachi, Ltd. | Signal transmitting device suitable for fast signal transmission including an arrangement to reduce signal amplitude in a second stage transmission line |
US6125419A (en) | 1996-06-13 | 2000-09-26 | Hitachi, Ltd. | Bus system, printed circuit board, signal transmission line, series circuit and memory module |
US6587912B2 (en) * | 1998-09-30 | 2003-07-01 | Intel Corporation | Method and apparatus for implementing multiple memory buses on a memory module |
US6934785B2 (en) * | 2000-12-22 | 2005-08-23 | Micron Technology, Inc. | High speed interface with looped bus |
US6882082B2 (en) * | 2001-03-13 | 2005-04-19 | Micron Technology, Inc. | Memory repeater |
US6757755B2 (en) * | 2001-10-15 | 2004-06-29 | Advanced Micro Devices, Inc. | Peripheral interface circuit for handling graphics responses in an I/O node of a computer system |
KR100502408B1 (ko) * | 2002-06-21 | 2005-07-19 | 삼성전자주식회사 | 액티브 터미네이션을 내장한 메모리 장치의 파워-업시퀀스를 제어하는 메모리 시스템과 그 파워-업 및 초기화방법 |
-
2003
- 2003-08-08 US US10/638,069 patent/US7194572B2/en not_active Expired - Lifetime
-
2004
- 2004-08-04 CN CNB2004800285161A patent/CN100456275C/zh active Active
- 2004-08-04 WO PCT/US2004/025220 patent/WO2005017760A2/en active IP Right Grant
- 2004-08-04 AT AT04780114T patent/ATE387668T1/de not_active IP Right Cessation
- 2004-08-04 EP EP04780114A patent/EP1652097B1/de active Active
- 2004-08-04 DE DE602004012113T patent/DE602004012113T2/de active Active
Also Published As
Publication number | Publication date |
---|---|
US7194572B2 (en) | 2007-03-20 |
EP1652097B1 (de) | 2008-02-27 |
CN100456275C (zh) | 2009-01-28 |
WO2005017760A3 (en) | 2005-06-30 |
EP1652097A2 (de) | 2006-05-03 |
ATE387668T1 (de) | 2008-03-15 |
DE602004012113T2 (de) | 2009-02-19 |
WO2005017760A2 (en) | 2005-02-24 |
US20050033905A1 (en) | 2005-02-10 |
CN1860461A (zh) | 2006-11-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |