DE602004007503D1 - REKONFIGURIERBARE ARCHITEKTUR FÜR SOCs - Google Patents
REKONFIGURIERBARE ARCHITEKTUR FÜR SOCsInfo
- Publication number
- DE602004007503D1 DE602004007503D1 DE602004007503T DE602004007503T DE602004007503D1 DE 602004007503 D1 DE602004007503 D1 DE 602004007503D1 DE 602004007503 T DE602004007503 T DE 602004007503T DE 602004007503 T DE602004007503 T DE 602004007503T DE 602004007503 D1 DE602004007503 D1 DE 602004007503D1
- Authority
- DE
- Germany
- Prior art keywords
- socs
- reconfigurable architecture
- reconfigurable
- architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US425101 | 1995-04-20 | ||
US10/425,101 US7058918B2 (en) | 2003-04-28 | 2003-04-28 | Reconfigurable fabric for SoCs using functional I/O leads |
PCT/US2004/013155 WO2004102210A1 (en) | 2003-04-28 | 2004-04-28 | RECONFIGURABLE FABRIC FOR SoCs |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004007503D1 true DE602004007503D1 (de) | 2007-08-23 |
DE602004007503T2 DE602004007503T2 (de) | 2008-04-17 |
Family
ID=33299473
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004007503T Expired - Lifetime DE602004007503T2 (de) | 2003-04-28 | 2004-04-28 | REKONFIGURIERBARE ARCHITEKTUR FÜR SOCs |
Country Status (6)
Country | Link |
---|---|
US (2) | US7058918B2 (de) |
EP (1) | EP1620739B1 (de) |
JP (1) | JP4406648B2 (de) |
KR (1) | KR20060003063A (de) |
DE (1) | DE602004007503T2 (de) |
WO (1) | WO2004102210A1 (de) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7127697B1 (en) * | 2001-08-07 | 2006-10-24 | Xilinx, Inc. | Methods of utilizing programmable logic devices having localized defects in application-specific products |
US6842039B1 (en) * | 2002-10-21 | 2005-01-11 | Altera Corporation | Configuration shift register |
KR101034494B1 (ko) * | 2004-02-11 | 2011-05-17 | 삼성전자주식회사 | 개방형 코어 프로토콜을 기반으로 하는 버스 시스템 |
DE602005015422D1 (de) * | 2004-02-17 | 2009-08-27 | Inst Nat Polytech Grenoble | Integrierter schaltungschip mit kommunikationsmitteln, wodurch eine fernbedienung von testmitteln von ip-kernen der integrierten schaltung möglich wird |
US7607057B2 (en) * | 2004-12-28 | 2009-10-20 | Lsi Corporation | Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip |
US7358765B2 (en) * | 2005-02-23 | 2008-04-15 | Cswitch Corporation | Dedicated logic cells employing configurable logic and dedicated logic functions |
US7605605B2 (en) * | 2005-01-27 | 2009-10-20 | Cswitch Corporation | Programmable logic cells with local connections |
US7394708B1 (en) | 2005-03-18 | 2008-07-01 | Xilinx, Inc. | Adjustable global tap voltage to improve memory cell yield |
KR100662471B1 (ko) | 2005-10-11 | 2007-01-02 | 엘지전자 주식회사 | 시스템 온 칩 구조 및 데이터 전송 방법 |
US7348796B2 (en) * | 2005-10-26 | 2008-03-25 | Dafca, Inc. | Method and system for network-on-chip and other integrated circuit architectures |
US7296201B2 (en) * | 2005-10-29 | 2007-11-13 | Dafca, Inc. | Method to locate logic errors and defects in digital circuits |
US7484153B2 (en) * | 2005-12-06 | 2009-01-27 | Kabushiki Kaisha Toshiba | Systems and methods for LBIST testing using isolatable scan chains |
US8656191B2 (en) | 2005-12-23 | 2014-02-18 | Nagravision S.A. | Secure system-on-chip |
EP1802030A1 (de) * | 2005-12-23 | 2007-06-27 | Nagracard S.A. | Sicheres System-on-Chip |
EP1811415A1 (de) * | 2005-12-23 | 2007-07-25 | Nagracard S.A. | Sicheres System-on-Chip |
US7519884B2 (en) | 2006-06-16 | 2009-04-14 | Texas Instruments Incorporated | TAM controller for plural test access mechanisms |
US7827515B2 (en) * | 2007-03-15 | 2010-11-02 | Oracle America, Inc. | Package designs for fully functional and partially functional chips |
US20090271877A1 (en) * | 2008-04-28 | 2009-10-29 | Dafca, Inc. | Method to secure embedded system with programmable logic, hardware and software binding, execution monitoring and counteraction |
US8234540B2 (en) | 2008-07-01 | 2012-07-31 | International Business Machines Corporation | Error correcting code protected quasi-static bit communication on a high-speed bus |
US8082474B2 (en) * | 2008-07-01 | 2011-12-20 | International Business Machines Corporation | Bit shadowing in a memory system |
US8201069B2 (en) * | 2008-07-01 | 2012-06-12 | International Business Machines Corporation | Cyclical redundancy code for use in a high-speed serial link |
US8245105B2 (en) * | 2008-07-01 | 2012-08-14 | International Business Machines Corporation | Cascade interconnect memory system with enhanced reliability |
US7895374B2 (en) * | 2008-07-01 | 2011-02-22 | International Business Machines Corporation | Dynamic segment sparing and repair in a memory system |
US8139430B2 (en) * | 2008-07-01 | 2012-03-20 | International Business Machines Corporation | Power-on initialization and test for a cascade interconnect memory system |
US8082475B2 (en) * | 2008-07-01 | 2011-12-20 | International Business Machines Corporation | Enhanced microprocessor interconnect with bit shadowing |
US20100005335A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Microprocessor interface with dynamic segment sparing and repair |
FR2933826B1 (fr) * | 2008-07-09 | 2011-11-18 | Univ Paris Curie | Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau |
US7956639B2 (en) * | 2008-07-23 | 2011-06-07 | Ndsu Research Foundation | Intelligent cellular electronic structures |
WO2010055462A1 (en) * | 2008-11-13 | 2010-05-20 | Nxp B.V. | Testable integrated circuit and test method therefor |
US7979759B2 (en) * | 2009-01-08 | 2011-07-12 | International Business Machines Corporation | Test and bring-up of an enhanced cascade interconnect memory system |
US20100180154A1 (en) * | 2009-01-13 | 2010-07-15 | International Business Machines Corporation | Built In Self-Test of Memory Stressor |
JP5451542B2 (ja) * | 2010-06-30 | 2014-03-26 | 日本電信電話株式会社 | 集積回路 |
US8793095B2 (en) * | 2011-03-09 | 2014-07-29 | Intel Corporation | Functional fabric-based test controller for functional and structural test and debug |
US9043665B2 (en) * | 2011-03-09 | 2015-05-26 | Intel Corporation | Functional fabric based test wrapper for circuit testing of IP blocks |
US8522189B2 (en) | 2011-03-09 | 2013-08-27 | Intel Corporation | Functional fabric based test access mechanism for SoCs |
US20150067428A1 (en) * | 2012-05-02 | 2015-03-05 | Freescale Semiconductor, Inc. | System-on-chip, method of manufacture thereof and method of communicating diagnostic data |
US9436623B2 (en) * | 2012-09-20 | 2016-09-06 | Intel Corporation | Run-time fabric reconfiguration |
US20210026934A1 (en) | 2018-02-02 | 2021-01-28 | Dover Microsystems, Inc. | Systems and methods for policy linking and/or loading for secure initialization |
US11797398B2 (en) | 2018-04-30 | 2023-10-24 | Dover Microsystems, Inc. | Systems and methods for checking safety properties |
EP3877874A1 (de) | 2018-11-06 | 2021-09-15 | Dover Microsystems, Inc. | Systeme und verfahren zum stillstand eines host-prozessors |
WO2020132012A1 (en) | 2018-12-18 | 2020-06-25 | Dover Microsystems, Inc. | Systems and methods for data lifecycle protection |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212652A (en) * | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
JP3552175B2 (ja) * | 1995-05-17 | 2004-08-11 | 株式会社アドバンテスト | フェイルメモリ装置 |
US6968514B2 (en) * | 1998-09-30 | 2005-11-22 | Cadence Design Systems, Inc. | Block based design methodology with programmable components |
US6484280B1 (en) | 1999-09-30 | 2002-11-19 | Agilent Technologies Inc. | Scan path test support |
US6594802B1 (en) | 2000-03-23 | 2003-07-15 | Intellitech Corporation | Method and apparatus for providing optimized access to circuits for debug, programming, and test |
US6877122B2 (en) * | 2001-12-21 | 2005-04-05 | Texas Instruments Incorporated | Link instruction register providing test control signals to core wrappers |
EP1296152A1 (de) | 2001-09-21 | 2003-03-26 | Siemens Aktiengesellschaft | Elektronischer Baustein und Verfahren zu dessen Qualifizierungsmessung |
-
2003
- 2003-04-28 US US10/425,101 patent/US7058918B2/en not_active Expired - Lifetime
-
2004
- 2004-04-28 WO PCT/US2004/013155 patent/WO2004102210A1/en active IP Right Grant
- 2004-04-28 EP EP04750858A patent/EP1620739B1/de not_active Expired - Fee Related
- 2004-04-28 DE DE602004007503T patent/DE602004007503T2/de not_active Expired - Lifetime
- 2004-04-28 JP JP2006532496A patent/JP4406648B2/ja not_active Expired - Fee Related
- 2004-04-28 KR KR1020057020501A patent/KR20060003063A/ko not_active Application Discontinuation
- 2004-08-30 US US10/929,709 patent/US7146548B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1620739B1 (de) | 2007-07-11 |
US7058918B2 (en) | 2006-06-06 |
EP1620739A1 (de) | 2006-02-01 |
WO2004102210A1 (en) | 2004-11-25 |
US7146548B1 (en) | 2006-12-05 |
US20040212393A1 (en) | 2004-10-28 |
DE602004007503T2 (de) | 2008-04-17 |
JP4406648B2 (ja) | 2010-02-03 |
KR20060003063A (ko) | 2006-01-09 |
JP2007501586A (ja) | 2007-01-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |