DE602004005912D1 - Vorrichtung und Verfahren zur Reduzierung der Verriegelungszeit einer Phasenregelschleife - Google Patents
Vorrichtung und Verfahren zur Reduzierung der Verriegelungszeit einer PhasenregelschleifeInfo
- Publication number
- DE602004005912D1 DE602004005912D1 DE602004005912T DE602004005912T DE602004005912D1 DE 602004005912 D1 DE602004005912 D1 DE 602004005912D1 DE 602004005912 T DE602004005912 T DE 602004005912T DE 602004005912 T DE602004005912 T DE 602004005912T DE 602004005912 D1 DE602004005912 D1 DE 602004005912D1
- Authority
- DE
- Germany
- Prior art keywords
- lock
- reducing
- time
- locked loop
- phase locked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/407,632 US7180334B2 (en) | 2003-04-03 | 2003-04-03 | Apparatus and method for decreasing the lock time of a lock loop circuit |
US407632 | 2003-04-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004005912D1 true DE602004005912D1 (de) | 2007-05-31 |
DE602004005912T2 DE602004005912T2 (de) | 2008-01-17 |
Family
ID=32908261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004005912T Expired - Lifetime DE602004005912T2 (de) | 2003-04-03 | 2004-03-31 | Vorrichtung und Verfahren zur Reduzierung der Verriegelungszeit einer Phasenregelschleife |
Country Status (4)
Country | Link |
---|---|
US (1) | US7180334B2 (de) |
EP (1) | EP1469605B1 (de) |
CN (1) | CN1551504B (de) |
DE (1) | DE602004005912T2 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6920552B2 (en) * | 2001-03-16 | 2005-07-19 | Broadcom Corporation | Network interface with double data rate and delay locked loop |
US20060002501A1 (en) * | 2004-06-30 | 2006-01-05 | Nokia Corporation | Ultra-fast hopping frequency synthesizer for multi-band transmission standards |
US7443761B2 (en) * | 2006-02-21 | 2008-10-28 | Micron Technology, Inc. | Loop filtering for fast PLL locking |
US7463057B1 (en) * | 2006-03-29 | 2008-12-09 | Altera Corporation | Integrated circuits with adjustable memory element power supplies |
US8788850B1 (en) * | 2009-01-22 | 2014-07-22 | Marvell International Ltd. | Systems and methods for using a security circuit to monitor a voltage of an integrated circuit to counter security threats to the integrated circuit |
US8072237B1 (en) | 2009-06-04 | 2011-12-06 | Altera Corporation | Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks |
US8633731B1 (en) | 2011-08-09 | 2014-01-21 | Altera Corporation | Programmable integrated circuit with thin-oxide passgates |
US9444460B1 (en) | 2013-11-22 | 2016-09-13 | Altera Corporation | Integrated circuits with programmable overdrive capabilities |
US10121534B1 (en) | 2015-12-18 | 2018-11-06 | Altera Corporation | Integrated circuit with overdriven and underdriven pass gates |
TWI697210B (zh) * | 2019-05-10 | 2020-06-21 | 國立中山大學 | 具自動頻帶選擇器之鎖相迴路及其多頻帶壓控振盪器 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4584539A (en) * | 1984-11-28 | 1986-04-22 | General Dynamics Pomona Division | Frequency-agile, multi-channel, microwave frequency synthesizer |
JPH0537936A (ja) * | 1990-11-08 | 1993-02-12 | Pioneer Electron Corp | 信号発振装置 |
US5124671A (en) * | 1991-06-04 | 1992-06-23 | Zenith Electronics Corporation | Lock detector and confidence system for multiple frequency range oscillator control |
FI95522C (fi) | 1992-11-27 | 1996-02-12 | Nokia Mobile Phones Ltd | Jänniteohjattu oskillaattori, jolla on laaja taajuusalue |
US5686864A (en) * | 1995-09-05 | 1997-11-11 | Motorola, Inc. | Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer |
US5648744A (en) * | 1995-12-22 | 1997-07-15 | Microtune, Inc. | System and method for voltage controlled oscillator automatic band selection |
US5739730A (en) * | 1995-12-22 | 1998-04-14 | Microtune, Inc. | Voltage controlled oscillator band switching technique |
US6091304A (en) * | 1998-09-22 | 2000-07-18 | Lg Information & Communications, Ltd. | Frequency band select phase lock loop device |
US6218876B1 (en) * | 1999-01-08 | 2001-04-17 | Altera Corporation | Phase-locked loop circuitry for programmable logic devices |
JP2002016493A (ja) * | 2000-06-30 | 2002-01-18 | Hitachi Ltd | 半導体集積回路および光伝送用送信回路 |
EP1193879A1 (de) * | 2000-09-29 | 2002-04-03 | Koninklijke Philips Electronics N.V. | Rauscharmer und schnellansprechender Frequenzsynthesierer, und übereinstimmendes Verfahren zur Frequenzsynthese |
US20050221773A1 (en) | 2002-06-24 | 2005-10-06 | Koninklijke Philips Electronics N.V. | Tuning system |
-
2003
- 2003-04-03 US US10/407,632 patent/US7180334B2/en not_active Expired - Lifetime
-
2004
- 2004-03-31 DE DE602004005912T patent/DE602004005912T2/de not_active Expired - Lifetime
- 2004-03-31 EP EP04251931A patent/EP1469605B1/de not_active Expired - Fee Related
- 2004-04-03 CN CN2004100352755A patent/CN1551504B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1551504B (zh) | 2011-05-25 |
US20040239385A1 (en) | 2004-12-02 |
CN1551504A (zh) | 2004-12-01 |
US7180334B2 (en) | 2007-02-20 |
DE602004005912T2 (de) | 2008-01-17 |
EP1469605A1 (de) | 2004-10-20 |
EP1469605B1 (de) | 2007-04-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |