DE60045073D1 - Verfahren zum Speichern und Lesen von Daten eines nichtflüchtigen Multibitspeichers mit einer nichtbinären Anzahl von Bits pro Zelle - Google Patents
Verfahren zum Speichern und Lesen von Daten eines nichtflüchtigen Multibitspeichers mit einer nichtbinären Anzahl von Bits pro ZelleInfo
- Publication number
- DE60045073D1 DE60045073D1 DE60045073T DE60045073T DE60045073D1 DE 60045073 D1 DE60045073 D1 DE 60045073D1 DE 60045073 T DE60045073 T DE 60045073T DE 60045073 T DE60045073 T DE 60045073T DE 60045073 D1 DE60045073 D1 DE 60045073D1
- Authority
- DE
- Germany
- Prior art keywords
- volatile
- storing
- reading data
- bits per
- per cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP00830671A EP1199725B1 (de) | 2000-10-13 | 2000-10-13 | Verfahren zum Speichern und Lesen von Daten eines nichtflüchtigen Multibitspeichers mit einer nichtbinären Anzahl von Bits pro Zelle |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE60045073D1 true DE60045073D1 (de) | 2010-11-18 |
Family
ID=8175511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60045073T Expired - Lifetime DE60045073D1 (de) | 2000-10-13 | 2000-10-13 | Verfahren zum Speichern und Lesen von Daten eines nichtflüchtigen Multibitspeichers mit einer nichtbinären Anzahl von Bits pro Zelle |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6646913B2 (de) |
| EP (1) | EP1199725B1 (de) |
| JP (1) | JP4237958B2 (de) |
| DE (1) | DE60045073D1 (de) |
Families Citing this family (74)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60328354D1 (de) * | 2003-02-20 | 2009-08-27 | St Microelectronics Srl | Programmierverfahren eines elektrisch programmierbaren, nichtflüchtigen Multibithalbleiterspeichers |
| US7372731B2 (en) * | 2003-06-17 | 2008-05-13 | Sandisk Il Ltd. | Flash memories with adaptive reference voltages |
| WO2005096507A1 (fr) * | 2004-04-04 | 2005-10-13 | Guobiao Zhang | Système binaire de nombres non entiers |
| US7071849B2 (en) * | 2004-04-04 | 2006-07-04 | Guobiao Zhang | Fractional-Bit Systems |
| US7272052B2 (en) * | 2005-03-31 | 2007-09-18 | Sandisk 3D Llc | Decoding circuit for non-binary groups of memory line drivers |
| US7167109B2 (en) * | 2005-03-31 | 2007-01-23 | Chenming Hu | Hybrid fractional-bit systems |
| US7633128B2 (en) * | 2005-07-15 | 2009-12-15 | Guobiao Zhang | N-ary mask-programmable memory |
| US7821080B2 (en) * | 2005-07-15 | 2010-10-26 | Guobiao Zhang | N-ary three-dimensional mask-programmable read-only memory |
| KR101375955B1 (ko) | 2006-05-12 | 2014-03-18 | 애플 인크. | 메모리 디바이스 내의 왜곡 추정 및 상쇄 |
| KR101202537B1 (ko) | 2006-05-12 | 2012-11-19 | 애플 인크. | 메모리 디바이스를 위한 결합된 왜곡 추정 및 에러 보정 코딩 |
| US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
| WO2008026203A2 (en) * | 2006-08-27 | 2008-03-06 | Anobit Technologies | Estimation of non-linear distortion in memory devices |
| US7420841B2 (en) * | 2006-08-30 | 2008-09-02 | Qimonda Ag | Memory device and method for transforming between non-power-of-2 levels of multilevel memory cells and 2-level data bits |
| DE102006040570A1 (de) * | 2006-08-30 | 2008-03-13 | Qimonda Ag | Speichervorrichtung, insbesondere Phasenwechsel-RAM-Vorrichtung und Verfahren zum Betreiben einer Speichervorrichtung |
| US7975192B2 (en) * | 2006-10-30 | 2011-07-05 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
| WO2008068747A2 (en) | 2006-12-03 | 2008-06-12 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
| US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
| WO2008111058A2 (en) | 2007-03-12 | 2008-09-18 | Anobit Technologies Ltd. | Adaptive estimation of memory cell read thresholds |
| US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
| US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
| US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
| US7966547B2 (en) * | 2007-07-02 | 2011-06-21 | International Business Machines Corporation | Multi-bit error correction scheme in multi-level memory storage system |
| US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
| US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
| US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
| US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
| US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
| US7742335B2 (en) * | 2007-10-31 | 2010-06-22 | Micron Technology, Inc. | Non-volatile multilevel memory cells |
| KR101509836B1 (ko) | 2007-11-13 | 2015-04-06 | 애플 인크. | 멀티 유닛 메모리 디바이스에서의 메모리 유닛의 최적화된 선택 |
| US7633798B2 (en) * | 2007-11-21 | 2009-12-15 | Micron Technology, Inc. | M+N bit programming and M+L bit read for M bit memory cells |
| US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
| US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
| US8456905B2 (en) * | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
| US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
| US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
| US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
| US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
| US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
| US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
| US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
| US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
| US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| JP4746658B2 (ja) | 2008-09-29 | 2011-08-10 | 株式会社東芝 | 半導体記憶システム |
| US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
| US8713330B1 (en) | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
| US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
| US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
| US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
| US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
| US8228701B2 (en) * | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
| US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
| US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
| US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
| US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
| US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
| US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
| US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
| US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
| US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
| US8564070B2 (en) | 2010-05-24 | 2013-10-22 | Chengdu Haicun Ip Technology Llc | Large bit-per-cell three-dimensional mask-programmable read-only memory |
| US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
| US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
| US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
| US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
| US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
| US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
| US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
| US8711617B2 (en) * | 2011-06-03 | 2014-04-29 | Micron Technology, Inc. | Data modulation for groups of memory cells |
| JP2012043530A (ja) * | 2011-10-24 | 2012-03-01 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US9171624B2 (en) | 2013-12-20 | 2015-10-27 | Apple Inc. | Management of data storage in analog memory cells using a non-integer number of bits per cell |
| FR3122024B1 (fr) * | 2021-04-20 | 2024-03-29 | St Microelectronics Grenoble 2 | Procédé de gestion de données pour mémoire non volatile programmable bit à bit, et dispositif correspondant |
| US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
| US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5093805A (en) * | 1990-06-20 | 1992-03-03 | Cypress Semiconductor Corporation | Non-binary memory array |
| US6002614A (en) * | 1991-02-08 | 1999-12-14 | Btg International Inc. | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
| US5315558A (en) * | 1991-10-25 | 1994-05-24 | Vlsi Technology, Inc. | Integrated circuit memory with non-binary array configuration |
| US5835414A (en) * | 1996-06-14 | 1998-11-10 | Macronix International Co., Ltd. | Page mode program, program verify, read and erase verify for floating gate memory device with low current page buffer |
| KR100192476B1 (ko) * | 1996-06-26 | 1999-06-15 | 구본준 | 다중 비트 메모리 셀의 데이타 센싱장치 및 방법 |
| US5854763A (en) * | 1997-01-31 | 1998-12-29 | Mosaid Technologies Inc. | Integrated circuit with non-binary decoding and data access |
| US5953255A (en) * | 1997-12-24 | 1999-09-14 | Aplus Flash Technology, Inc. | Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance |
| JP2001067884A (ja) * | 1999-08-31 | 2001-03-16 | Hitachi Ltd | 不揮発性半導体記憶装置 |
| US6373767B1 (en) * | 1999-10-12 | 2002-04-16 | Robert Patti | Memory that stores multiple bits per storage cell |
-
2000
- 2000-10-13 EP EP00830671A patent/EP1199725B1/de not_active Expired - Lifetime
- 2000-10-13 DE DE60045073T patent/DE60045073D1/de not_active Expired - Lifetime
-
2001
- 2001-10-11 US US09/976,473 patent/US6646913B2/en not_active Expired - Lifetime
- 2001-10-15 JP JP2001316940A patent/JP4237958B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6646913B2 (en) | 2003-11-11 |
| US20020054505A1 (en) | 2002-05-09 |
| JP2002124093A (ja) | 2002-04-26 |
| EP1199725A1 (de) | 2002-04-24 |
| JP4237958B2 (ja) | 2009-03-11 |
| EP1199725B1 (de) | 2010-10-06 |
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