DE60033776D1 - Verfahren und Anordnung zur Reduzierung des Spitzen -Programmierstroms - Google Patents

Verfahren und Anordnung zur Reduzierung des Spitzen -Programmierstroms

Info

Publication number
DE60033776D1
DE60033776D1 DE60033776T DE60033776T DE60033776D1 DE 60033776 D1 DE60033776 D1 DE 60033776D1 DE 60033776 T DE60033776 T DE 60033776T DE 60033776 T DE60033776 T DE 60033776T DE 60033776 D1 DE60033776 D1 DE 60033776D1
Authority
DE
Germany
Prior art keywords
arrangement
reducing
programming current
peak programming
peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60033776T
Other languages
English (en)
Other versions
DE60033776T2 (de
Inventor
Peter K Naji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE60033776D1 publication Critical patent/DE60033776D1/de
Application granted granted Critical
Publication of DE60033776T2 publication Critical patent/DE60033776T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Analogue/Digital Conversion (AREA)
DE60033776T 1999-12-20 2000-12-19 Verfahren und Anordnung zur Reduzierung des Spitzen -Programmierstroms Expired - Fee Related DE60033776T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US467788 1999-12-20
US09/467,788 US6236611B1 (en) 1999-12-20 1999-12-20 Peak program current reduction apparatus and method

Publications (2)

Publication Number Publication Date
DE60033776D1 true DE60033776D1 (de) 2007-04-19
DE60033776T2 DE60033776T2 (de) 2007-06-28

Family

ID=23857180

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60033776T Expired - Fee Related DE60033776T2 (de) 1999-12-20 2000-12-19 Verfahren und Anordnung zur Reduzierung des Spitzen -Programmierstroms

Country Status (8)

Country Link
US (1) US6236611B1 (de)
EP (1) EP1111619B1 (de)
JP (1) JP2001222882A (de)
KR (1) KR100748070B1 (de)
CN (1) CN1181494C (de)
DE (1) DE60033776T2 (de)
SG (1) SG88805A1 (de)
TW (1) TW505921B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6256224B1 (en) * 2000-05-03 2001-07-03 Hewlett-Packard Co Write circuit for large MRAM arrays
WO2003001532A2 (en) * 2001-01-24 2003-01-03 Infineon Technologies North America Corp. Current source and drain arrangement for magnetoresistive memories (mrams)
JP4637388B2 (ja) * 2001-03-23 2011-02-23 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
EP1433181B1 (de) * 2001-06-20 2007-10-24 Qimonda AG Stromquelle und drainanordnung für magnetoresitive speicher
JP4771631B2 (ja) * 2001-09-21 2011-09-14 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
US6621729B1 (en) 2002-06-28 2003-09-16 Motorola, Inc. Sense amplifier incorporating a symmetric midpoint reference
US6714440B2 (en) 2002-06-28 2004-03-30 Motorola, Inc. Memory architecture with write circuitry and method therefor
US6711052B2 (en) * 2002-06-28 2004-03-23 Motorola, Inc. Memory having a precharge circuit and method therefor
ES2406304T3 (es) 2002-11-28 2013-06-06 Crocus Technology, Inc. Procedimiento y dispositivo para la generación mejorada de campos magnéticos durante una operación de escritura de un dispositivo de memoria magnetorresistente
US6778431B2 (en) * 2002-12-13 2004-08-17 International Business Machines Corporation Architecture for high-speed magnetic memories
US7221582B2 (en) * 2003-08-27 2007-05-22 Hewlett-Packard Development Company, L.P. Method and system for controlling write current in magnetic memory
JP2008500718A (ja) * 2004-05-27 2008-01-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｍｒａｍを電力効率良くバイト書込みするための逆にされた磁気トンネル接合
KR100587702B1 (ko) 2004-07-09 2006-06-08 삼성전자주식회사 피크 전류의 감소 특성을 갖는 상변화 메모리 장치 및그에 따른 데이터 라이팅 방법
KR100694967B1 (ko) * 2005-06-29 2007-03-14 주식회사 하이닉스반도체 프로그램 동작시 에러 발생 비율을 감소시키는 플래시메모리 장치 및 그 프로그램 동작 제어 방법
TWI398065B (zh) * 2009-09-02 2013-06-01 Giga Byte Tech Co Ltd 分配器、控制方法及電子系統
KR102081757B1 (ko) 2013-06-26 2020-02-26 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
KR20150022242A (ko) * 2013-08-22 2015-03-04 에스케이하이닉스 주식회사 반도체 메모리 장치
US9330746B2 (en) * 2014-03-19 2016-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Resistive memory array

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101095A (ja) * 1982-11-29 1984-06-11 Toshiba Corp 不揮発性半導体メモリ
JPH0793040B2 (ja) * 1987-11-11 1995-10-09 日本電気株式会社 書込み・消去可能な読出し専用メモリ
US5025419A (en) * 1988-03-31 1991-06-18 Sony Corporation Input/output circuit
JPH0512891A (ja) * 1990-09-17 1993-01-22 Toshiba Corp 半導体記憶装置
JPH0562484A (ja) * 1991-09-06 1993-03-12 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US5534793A (en) * 1995-01-24 1996-07-09 Texas Instruments Incorporated Parallel antifuse routing scheme (PARS) circuit and method for field programmable gate arrays
JPH09306159A (ja) * 1996-05-14 1997-11-28 Nippon Telegr & Teleph Corp <Ntt> 逐次読出しメモリ
JP4136028B2 (ja) * 1997-04-28 2008-08-20 キヤノン株式会社 磁性薄膜メモリ素子、それを用いた磁性薄膜メモリ及びその記録再生方法
JPH11176179A (ja) * 1997-12-15 1999-07-02 Nec Corp 不揮発性半導体記憶装置
US6097626A (en) * 1999-07-28 2000-08-01 Hewlett-Packard Company MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells

Also Published As

Publication number Publication date
US6236611B1 (en) 2001-05-22
JP2001222882A (ja) 2001-08-17
TW505921B (en) 2002-10-11
CN1181494C (zh) 2004-12-22
SG88805A1 (en) 2002-05-21
CN1302069A (zh) 2001-07-04
KR100748070B1 (ko) 2007-08-09
EP1111619A3 (de) 2001-09-26
DE60033776T2 (de) 2007-06-28
EP1111619A2 (de) 2001-06-27
EP1111619B1 (de) 2007-03-07
KR20010062468A (ko) 2001-07-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee