DE3885204D1 - Serial interface. - Google Patents

Serial interface.

Info

Publication number
DE3885204D1
DE3885204D1 DE88113485T DE3885204T DE3885204D1 DE 3885204 D1 DE3885204 D1 DE 3885204D1 DE 88113485 T DE88113485 T DE 88113485T DE 3885204 T DE3885204 T DE 3885204T DE 3885204 D1 DE3885204 D1 DE 3885204D1
Authority
DE
Germany
Prior art keywords
control signals
circuit arrangement
static
evaluating
serial interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88113485T
Other languages
German (de)
Inventor
Dieter Dipl Ing Rottmann
Juergen Dipl Ing Laabs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Priority to DE88113485T priority Critical patent/DE3885204D1/en
Application granted granted Critical
Publication of DE3885204D1 publication Critical patent/DE3885204D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/90Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving

Landscapes

  • Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Circuits Of Receivers In General (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Microcomputers (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Communication Control (AREA)

Abstract

1.1 Circuit arrangement for evaluating control signals 2.1 In highly integrated data processors, the number of control ports is restricted. There is a problem to supply different control signals via the existing control ports. 2.2 In a circuit arrangement for evaluating control signals output from a data processor, which consists of static and dynamic control signals, a memory is provided to which the static control signals are supplied and another memory is provided which is synchronised by the dynamic signal. 2.3 The circuit arrangement can be applied in the processing of control signals in a receiver for digital audio broadcasting.
DE88113485T 1987-08-28 1988-08-19 Serial interface. Expired - Fee Related DE3885204D1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE88113485T DE3885204D1 (en) 1987-08-28 1988-08-19 Serial interface.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19873728793 DE3728793A1 (en) 1987-08-28 1987-08-28 CIRCUIT ARRANGEMENT FOR EVALUATING CONTROL SIGNALS OUTPUT FROM A DATA PROCESSOR
DE88113485T DE3885204D1 (en) 1987-08-28 1988-08-19 Serial interface.

Publications (1)

Publication Number Publication Date
DE3885204D1 true DE3885204D1 (en) 1993-12-02

Family

ID=6334723

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19873728793 Withdrawn DE3728793A1 (en) 1987-08-28 1987-08-28 CIRCUIT ARRANGEMENT FOR EVALUATING CONTROL SIGNALS OUTPUT FROM A DATA PROCESSOR
DE88113485T Expired - Fee Related DE3885204D1 (en) 1987-08-28 1988-08-19 Serial interface.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE19873728793 Withdrawn DE3728793A1 (en) 1987-08-28 1987-08-28 CIRCUIT ARRANGEMENT FOR EVALUATING CONTROL SIGNALS OUTPUT FROM A DATA PROCESSOR

Country Status (5)

Country Link
EP (1) EP0304813B1 (en)
JP (1) JP2950834B2 (en)
AT (1) ATE96589T1 (en)
DE (2) DE3728793A1 (en)
HK (1) HK124494A (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3076587B2 (en) * 1990-05-31 2000-08-14 ナカミチ株式会社 Changer type disc player
EP0614178A3 (en) * 1993-03-05 1994-10-12 Nakamichi Corp Disc player with compact disk transporter.
JPH06259864A (en) * 1993-03-05 1994-09-16 Nakamichi Corp Disk reproducing device
JPH06259865A (en) * 1993-03-05 1994-09-16 Nakamichi Corp Disk reproducing device
US5508994A (en) * 1993-03-05 1996-04-16 Nakamichi Corporation Disk player with compact arrangement of a reader and disk storage magazine
JPH06259869A (en) * 1993-03-05 1994-09-16 Nakamichi Corp Disk reproducing device
JP3183744B2 (en) * 1993-03-05 2001-07-09 ナカミチ株式会社 Disc player with changer function
JP2596255Y2 (en) * 1993-03-23 1999-06-07 ナカミチ株式会社 Disc playback device
US5544148A (en) * 1993-05-20 1996-08-06 Nakamichi Corporation Compact configuration disk player
JPH06349186A (en) * 1993-06-03 1994-12-22 Nakamichi Corp Disk reproducing device
JP4741024B1 (en) * 2010-01-27 2011-08-03 シャープ株式会社 Image forming apparatus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117939A (en) * 1983-11-30 1985-06-25 Matsushita Electric Works Ltd Information transmission system
JPS6170827A (en) * 1984-09-14 1986-04-11 Yamatake Honeywell Co Ltd Communication method
SE458972B (en) * 1984-06-04 1989-05-22 Yamatake Honeywell Co Ltd DIALOGUE PROCEDURE AND DEVICE FOR IMPLEMENTATION OF THE PROCEDURE

Also Published As

Publication number Publication date
EP0304813B1 (en) 1993-10-27
EP0304813A2 (en) 1989-03-01
DE3728793A1 (en) 1989-03-09
EP0304813A3 (en) 1991-04-10
ATE96589T1 (en) 1993-11-15
JPS6471338A (en) 1989-03-16
JP2950834B2 (en) 1999-09-20
HK124494A (en) 1994-11-18

Similar Documents

Publication Publication Date Title
DK25186D0 (en) CIRCUIT ARRANGEMENT FOR USE IN AN INTEGRATED CIRCUIT
DE68914716D1 (en) Processing methods for data signals.
DE68929113D1 (en) Digital signal processing unit
JPS6489678A (en) Signal processing system
DE68916818D1 (en) Semiconductor memory arrangement capable of generating a write signal internally.
DE3885204D1 (en) Serial interface.
DE3481351D1 (en) DATA PROCESSING SYSTEM CONTAINING A MAIN PROCESSOR AND A COMPRESSOR PROCESSOR AND AN ERROR TREATMENT LOGIC REQUIRED WITH THE SUPPORTER PROCESSOR.
DE69610824D1 (en) READING AMPLIFIER WITH PULL-UP CIRCUIT FOR ACCELERATING THE LOGICAL RULE OF OUTPUT DATA
DE3784769D1 (en) VIDEO SIGNAL PROCESSING CIRCUITS.
FR2608808B1 (en) INTEGRATED CIRCUIT FOR DIGITAL SIGNAL PROCESSING
DE3879758D1 (en) CIRCUIT FOR REDUCING NOISE OF A VIDEO SIGNAL.
DE69032358D1 (en) Data processing system for audio signals
DE3480895D1 (en) SIGNAL PROCESSING CIRCUITS.
ATE64511T1 (en) CIRCUIT FOR CONTROLLING THE PHASE OF A SIGNAL PROCESSED IN A DATA MEMORY.
NO820513L (en) SIGNAL PROCESSING CIRCUIT FOR AUDIO SIGNALS OVER A SUBSCRIPTION LINE.
DE68906908D1 (en) SIGNAL PROCESSING CIRCUIT AND METHOD.
JPS57182837A (en) Digital data connecting device
JPS57182838A (en) Digital data connecting circuit
DE68909841D1 (en) Video signal processing circuit.
KR890009829U (en) Audio signal output control circuit
ZA866883B (en) Method and circuit arrangement for the transmission of data signals between control devices connected to one another via a loop system
DE3882320D1 (en) DIGITAL SIGNAL PROCESSING DEVICE.
ATE96591T1 (en) CIRCUIT ARRANGEMENT FOR SYNCHRONIZATION.
JPS6473876A (en) Moving image processor
KR890009802U (en) Video signal processing output circuit

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee