DE3876195D1 - Verdrahtungssystem fuer die verbindung von mehreren elektrischen oder elektronischen anordnungen. - Google Patents

Verdrahtungssystem fuer die verbindung von mehreren elektrischen oder elektronischen anordnungen.

Info

Publication number
DE3876195D1
DE3876195D1 DE8888114456T DE3876195T DE3876195D1 DE 3876195 D1 DE3876195 D1 DE 3876195D1 DE 8888114456 T DE8888114456 T DE 8888114456T DE 3876195 T DE3876195 T DE 3876195T DE 3876195 D1 DE3876195 D1 DE 3876195D1
Authority
DE
Germany
Prior art keywords
wiring system
several electrical
connecting several
electronic arrangements
arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888114456T
Other languages
English (en)
Other versions
DE3876195T2 (de
Inventor
Ralph Linsker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3876195D1 publication Critical patent/DE3876195D1/de
Application granted granted Critical
Publication of DE3876195T2 publication Critical patent/DE3876195T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE8888114456T 1987-09-25 1988-09-05 Verdrahtungssystem fuer die verbindung von mehreren elektrischen oder elektronischen anordnungen. Expired - Fee Related DE3876195T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/101,228 US4782193A (en) 1987-09-25 1987-09-25 Polygonal wiring for improved package performance

Publications (2)

Publication Number Publication Date
DE3876195D1 true DE3876195D1 (de) 1993-01-07
DE3876195T2 DE3876195T2 (de) 1993-06-03

Family

ID=22283602

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888114456T Expired - Fee Related DE3876195T2 (de) 1987-09-25 1988-09-05 Verdrahtungssystem fuer die verbindung von mehreren elektrischen oder elektronischen anordnungen.

Country Status (4)

Country Link
US (1) US4782193A (de)
EP (1) EP0308714B1 (de)
JP (1) JPH0196953A (de)
DE (1) DE3876195T2 (de)

Families Citing this family (78)

* Cited by examiner, † Cited by third party
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FR2634340B1 (fr) * 1988-07-13 1994-06-17 Thomson Csf Dispositif d'interconnexion entre un circuit integre et un circuit electrique, application du dispositif a la connexion d'un circuit integre notamment a un circuit imprime, et procede de fabrication du dispositif
EP0405755B1 (de) * 1989-05-31 1995-11-29 Fujitsu Limited Packungsstruktur mit einem Steckerstift-Gitter
JPH0714024B2 (ja) * 1990-11-29 1995-02-15 川崎製鉄株式会社 マルチチップモジュール
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
JP2759573B2 (ja) * 1992-01-23 1998-05-28 株式会社日立製作所 回路基板の配線パターン決定方法
US5360948A (en) * 1992-08-14 1994-11-01 Ncr Corporation Via programming for multichip modules
US5410107A (en) 1993-03-01 1995-04-25 The Board Of Trustees Of The University Of Arkansas Multichip module
US5723908A (en) * 1993-03-11 1998-03-03 Kabushiki Kaisha Toshiba Multilayer wiring structure
DE19652258A1 (de) * 1996-12-16 1998-06-18 Ibm Verbesserte Verdrahtungsstruktur für Hochleistungschips
JP3386977B2 (ja) * 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
JP3466443B2 (ja) * 1997-11-19 2003-11-10 新光電気工業株式会社 多層回路基板
JP3380151B2 (ja) 1997-12-22 2003-02-24 新光電気工業株式会社 多層回路基板
JP3184796B2 (ja) * 1998-03-19 2001-07-09 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 配線設計装置およびその方法
US6483714B1 (en) 1999-02-24 2002-11-19 Kyocera Corporation Multilayered wiring board
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US6957410B2 (en) 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US7003754B2 (en) 2000-12-07 2006-02-21 Cadence Design Systems, Inc. Routing method and apparatus that use of diagonal routes
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US6900540B1 (en) * 2000-12-07 2005-05-31 Cadence Design Systems, Inc. Simulating diagonal wiring directions using Manhattan directional wires
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US6883154B2 (en) 2001-01-19 2005-04-19 Cadence Design Systems, Inc. LP method and apparatus for identifying route propagations
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
US6526555B1 (en) * 2001-06-03 2003-02-25 Cadence Design Systems, Inc. Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction
US6877146B1 (en) 2001-06-03 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US6931616B2 (en) * 2001-08-23 2005-08-16 Cadence Design Systems, Inc. Routing method and apparatus
US6795958B2 (en) * 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
US7398498B2 (en) 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US6745379B2 (en) 2001-08-23 2004-06-01 Cadence Design Systems, Inc. Method and apparatus for identifying propagation for routes with diagonal edges
US7143382B2 (en) 2001-08-23 2006-11-28 Cadence Design Systems, Inc. Method and apparatus for storing routes
US6762489B2 (en) * 2001-11-20 2004-07-13 International Business Machines Corporation Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US7013451B1 (en) 2002-01-22 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for performing routability checking
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US6973634B1 (en) 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US6892369B2 (en) * 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US6996789B2 (en) * 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7003752B2 (en) * 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US6988257B2 (en) * 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7171635B2 (en) * 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7480885B2 (en) * 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7047513B2 (en) * 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7010771B2 (en) * 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7624367B2 (en) 2002-11-18 2009-11-24 Cadence Design Systems, Inc. Method and system for routing
US7216308B2 (en) * 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7093221B2 (en) * 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7080342B2 (en) * 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US8095903B2 (en) * 2004-06-01 2012-01-10 Pulsic Limited Automatically routing nets with variable spacing
US7784010B1 (en) 2004-06-01 2010-08-24 Pulsic Limited Automatic routing system with variable width interconnect
US7131096B1 (en) 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
US7373628B1 (en) 2004-06-01 2008-05-13 Pulsic Limited Method of automatically routing nets using a Steiner tree
US7257797B1 (en) 2004-06-07 2007-08-14 Pulsic Limited Method of automatic shape-based routing of interconnects in spines for integrated circuit design
US7107556B1 (en) * 2004-12-29 2006-09-12 Cadence Design Systems, Inc. Method and system for implementing an analytical wirelength formulation for unavailability of routing directions
US7168053B1 (en) 2004-12-29 2007-01-23 Cadence Design Systems, Inc. Method and system for implementing an analytical wirelength formulation
US9245082B2 (en) * 2005-06-21 2016-01-26 Pulsic Limited High-speed shape-based router
US7603644B2 (en) * 2005-06-24 2009-10-13 Pulsic Limited Integrated circuit routing and compaction
US7363607B2 (en) * 2005-11-08 2008-04-22 Pulsic Limited Method of automatically routing nets according to parasitic constraint rules
US8201128B2 (en) 2006-06-16 2012-06-12 Cadence Design Systems, Inc. Method and apparatus for approximating diagonal lines in placement
US8250514B1 (en) 2006-07-13 2012-08-21 Cadence Design Systems, Inc. Localized routing direction
JP2009122474A (ja) 2007-11-16 2009-06-04 Mitsubishi Electric Corp 液晶表示装置及びその製造方法
US8011950B2 (en) 2009-02-18 2011-09-06 Cinch Connectors, Inc. Electrical connector
US8458636B1 (en) 2009-03-18 2013-06-04 Pulsic Limited Filling vacant areas of an integrated circuit design
KR20220145988A (ko) 2021-04-22 2022-11-01 삼성전자주식회사 반도체 장치

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US3179913A (en) * 1962-01-25 1965-04-20 Ind Electronic Hardware Corp Rack with multilayer matrix boards
US3470612A (en) * 1966-11-14 1969-10-07 Texas Instruments Inc Method of making multilayer circuit boards
JPS5530822A (en) * 1978-08-25 1980-03-04 Fujitsu Ltd Printed board
US4254445A (en) * 1979-05-07 1981-03-03 International Business Machines Corporation Discretionary fly wire chip interconnection
US4302625A (en) * 1980-06-30 1981-11-24 International Business Machines Corp. Multi-layer ceramic substrate
JPS5818950A (ja) * 1981-07-28 1983-02-03 Nec Corp 多層配線基板
JPS60136294A (ja) * 1983-12-23 1985-07-19 株式会社日立製作所 セラミック多層配線回路板
US4535388A (en) * 1984-06-29 1985-08-13 International Business Machines Corporation High density wired module

Also Published As

Publication number Publication date
EP0308714B1 (de) 1992-11-25
US4782193A (en) 1988-11-01
EP0308714A3 (en) 1989-08-09
DE3876195T2 (de) 1993-06-03
JPH0196953A (ja) 1989-04-14
EP0308714A2 (de) 1989-03-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee