DE3854636D1 - Automatischer Prüfprozess für logische Geräte. - Google Patents

Automatischer Prüfprozess für logische Geräte.

Info

Publication number
DE3854636D1
DE3854636D1 DE3854636T DE3854636T DE3854636D1 DE 3854636 D1 DE3854636 D1 DE 3854636D1 DE 3854636 T DE3854636 T DE 3854636T DE 3854636 T DE3854636 T DE 3854636T DE 3854636 D1 DE3854636 D1 DE 3854636D1
Authority
DE
Germany
Prior art keywords
test process
automatic test
logical devices
logical
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3854636T
Other languages
English (en)
Other versions
DE3854636T2 (de
Inventor
Wayne Roger Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE3854636D1 publication Critical patent/DE3854636D1/de
Application granted granted Critical
Publication of DE3854636T2 publication Critical patent/DE3854636T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE3854636T 1987-08-28 1988-08-26 Automatischer Prüfprozess für logische Geräte. Expired - Fee Related DE3854636T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/090,869 US4853928A (en) 1987-08-28 1987-08-28 Automatic test generator for logic devices

Publications (2)

Publication Number Publication Date
DE3854636D1 true DE3854636D1 (de) 1995-12-07
DE3854636T2 DE3854636T2 (de) 1996-05-02

Family

ID=22224717

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3854636T Expired - Fee Related DE3854636T2 (de) 1987-08-28 1988-08-26 Automatischer Prüfprozess für logische Geräte.

Country Status (5)

Country Link
US (1) US4853928A (de)
EP (1) EP0305217B1 (de)
JP (1) JPH01152379A (de)
KR (1) KR920006969B1 (de)
DE (1) DE3854636T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1246467B (it) * 1990-10-22 1994-11-19 St Microelectronics Srl Macchina a stati finiti per sistemi affidabili di computazione e regolazione
US5321701A (en) * 1990-12-06 1994-06-14 Teradyne, Inc. Method and apparatus for a minimal memory in-circuit digital tester
US5377201A (en) * 1991-06-18 1994-12-27 Nec Research Institute, Inc. Transitive closure based process for generating test vectors for VLSI circuit
US5331570A (en) * 1992-03-27 1994-07-19 Mitsubishi Electric Research Laboratories, Inc. Method for generating test access procedures
EP0584385B1 (de) * 1992-08-25 1996-11-06 International Business Machines Corporation Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign
US5517506A (en) * 1994-03-28 1996-05-14 Motorola, Inc. Method and data processing system for testing circuits using boolean differences
US5546408A (en) * 1994-06-09 1996-08-13 International Business Machines Corporation Hierarchical pattern faults for describing logic circuit failure mechanisms
US6134689A (en) 1998-02-12 2000-10-17 Motorola Inc. Method of testing logic devices
FR2798472B1 (fr) * 1999-09-15 2001-12-14 Centre Nat Etd Spatiales Procede de localisation d'elements defectueux dans un circuit integre
EP1364286B1 (de) * 2001-02-20 2009-08-19 Siemens Aktiengesellschaft Verfahren und anordnung zur ermittlung einer gesamtfehlerbeschreibung zumindest eines teils eines technischen systems, computer programm-element und computerlesbares speichermedium
US6654701B2 (en) * 2001-08-30 2003-11-25 Spirent Communications Method and apparatus for measuring protocol performance in a data communication network
US7437638B2 (en) * 2002-11-12 2008-10-14 Agilent Technologies, Inc. Boundary-Scan methods and apparatus
US7376876B2 (en) * 2004-12-23 2008-05-20 Honeywell International Inc. Test program set generation tool

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1381413A (en) * 1920-01-06 1921-06-14 Henry A Gardner Fabric for airships and process of making same
GB1381413A (en) * 1972-06-21 1975-01-22 Ibm Methods of testing asynchronous sequential circuits
US4204633A (en) * 1978-11-20 1980-05-27 International Business Machines Corporation Logic chip test system with path oriented decision making test pattern generator
GB8327753D0 (en) * 1983-10-17 1983-11-16 Robinson G D Test generation system
FR2573887B1 (fr) * 1984-11-26 1992-09-04 Nec Corp Procede de generation de configurations de test pour dispositifs a reseaux logiques
US4692921A (en) * 1985-08-22 1987-09-08 American Telephone And Telegraph Company, At&T Bell Laboratories Method for generating verification tests

Also Published As

Publication number Publication date
EP0305217A3 (en) 1990-10-24
EP0305217B1 (de) 1995-11-02
US4853928A (en) 1989-08-01
KR890004172A (ko) 1989-04-20
KR920006969B1 (ko) 1992-08-22
JPH01152379A (ja) 1989-06-14
EP0305217A2 (de) 1989-03-01
DE3854636T2 (de) 1996-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee