DE3784751D1 - Verfahren zur herstellung von verbindungsloechern auf integrierten schaltungen. - Google Patents

Verfahren zur herstellung von verbindungsloechern auf integrierten schaltungen.

Info

Publication number
DE3784751D1
DE3784751D1 DE8787400652T DE3784751T DE3784751D1 DE 3784751 D1 DE3784751 D1 DE 3784751D1 DE 8787400652 T DE8787400652 T DE 8787400652T DE 3784751 T DE3784751 T DE 3784751T DE 3784751 D1 DE3784751 D1 DE 3784751D1
Authority
DE
Germany
Prior art keywords
integrated circuits
connection holes
producing connection
producing
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787400652T
Other languages
English (en)
Other versions
DE3784751T2 (de
Inventor
Michael E Thomas
Robert L Brown
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE3784751D1 publication Critical patent/DE3784751D1/de
Application granted granted Critical
Publication of DE3784751T2 publication Critical patent/DE3784751T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8787400652T 1986-03-24 1987-03-24 Verfahren zur herstellung von verbindungsloechern auf integrierten schaltungen. Expired - Fee Related DE3784751T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/843,328 US4670091A (en) 1984-08-23 1986-03-24 Process for forming vias on integrated circuits

Publications (2)

Publication Number Publication Date
DE3784751D1 true DE3784751D1 (de) 1993-04-22
DE3784751T2 DE3784751T2 (de) 1993-09-23

Family

ID=25289658

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787400652T Expired - Fee Related DE3784751T2 (de) 1986-03-24 1987-03-24 Verfahren zur herstellung von verbindungsloechern auf integrierten schaltungen.

Country Status (5)

Country Link
US (1) US4670091A (de)
EP (1) EP0239489B1 (de)
JP (1) JPS62279661A (de)
CA (1) CA1249072A (de)
DE (1) DE3784751T2 (de)

Families Citing this family (49)

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Publication number Priority date Publication date Assignee Title
JPS61258453A (ja) * 1985-05-13 1986-11-15 Toshiba Corp 半導体装置の製造方法
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
US5462767A (en) * 1985-09-21 1995-10-31 Semiconductor Energy Laboratory Co., Ltd. CVD of conformal coatings over a depression using alkylmetal precursors
JPS63132452A (ja) * 1986-11-24 1988-06-04 Mitsubishi Electric Corp パタ−ン形成方法
NL8701032A (nl) * 1987-05-01 1988-12-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met interconnecties die zowel boven een halfgeleidergebied als boven een daaraan grenzend isolatiegebied liggen.
US4981550A (en) * 1987-09-25 1991-01-01 At&T Bell Laboratories Semiconductor device having tungsten plugs
US4963510A (en) * 1987-11-02 1990-10-16 Texas Instruments Incorporated Method and apparatus for providing interconnection between metallization layers on semiconductors devices
GB2212979A (en) * 1987-12-02 1989-08-02 Philips Nv Fabricating electrical connections,particularly in integrated circuit manufacture
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
US4897676A (en) * 1988-01-05 1990-01-30 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5488394A (en) * 1988-01-05 1996-01-30 Max Levy Autograph, Inc. Print head and method of making same
US5162191A (en) * 1988-01-05 1992-11-10 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
GB2214709A (en) * 1988-01-20 1989-09-06 Philips Nv A method of enabling connection to a substructure forming part of an electronic device
EP0343269B1 (de) * 1988-05-26 1993-05-12 Fairchild Semiconductor Corporation Verbindungssystem von hoher Leistungsfähigkeit für eine integrierte Schaltung
US4997789A (en) * 1988-10-31 1991-03-05 Texas Instruments Incorporated Aluminum contact etch mask and etchstop for tungsten etchback
US4920072A (en) * 1988-10-31 1990-04-24 Texas Instruments Incorporated Method of forming metal interconnects
US4933743A (en) * 1989-03-11 1990-06-12 Fairchild Semiconductor Corporation High performance interconnect system for an integrated circuit
US4917759A (en) * 1989-04-17 1990-04-17 Motorola, Inc. Method for forming self-aligned vias in multi-level metal integrated circuits
FR2650472A1 (fr) * 1989-07-27 1991-02-01 Bull Sa Procede de depot d'une couche isolante sur une couche conductrice du reseau multicouche d'une carte de connexion de circuit integre de haute densite, et carte en resultant
US5000818A (en) * 1989-08-14 1991-03-19 Fairchild Semiconductor Corporation Method of fabricating a high performance interconnect system for an integrated circuit
US5117276A (en) * 1989-08-14 1992-05-26 Fairchild Camera And Instrument Corp. High performance interconnect system for an integrated circuit
US4991285A (en) * 1989-11-17 1991-02-12 Rockwell International Corporation Method of fabricating multi-layer board
US4992059A (en) * 1989-12-01 1991-02-12 Westinghouse Electric Corp. Ultra fine line cable and a method for fabricating the same
US5112761A (en) * 1990-01-10 1992-05-12 Microunity Systems Engineering Bicmos process utilizing planarization technique
US5225040A (en) * 1990-04-16 1993-07-06 Raytheon Company Process for patterning metal connections in small-geometry semiconductor structures
US5245751A (en) * 1990-04-27 1993-09-21 Circuit Components, Incorporated Array connector
US5071359A (en) * 1990-04-27 1991-12-10 Rogers Corporation Array connector
JPH0710030B2 (ja) * 1990-05-18 1995-02-01 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層配線基板の製造方法
US5217570A (en) * 1991-01-31 1993-06-08 Sony Corporation Dry etching method
US5118385A (en) * 1991-05-28 1992-06-02 Microelectronics And Computer Technology Corporation Multilayer electrical interconnect fabrication with few process steps
JPH06216061A (ja) * 1992-11-25 1994-08-05 Sgs Thomson Microelectron Inc 自己整合型ビア
JPH06314687A (ja) * 1993-04-30 1994-11-08 Sony Corp 多層配線構造の半導体装置およびその製造方法
KR0137978B1 (ko) * 1994-10-12 1998-06-15 김주용 반도체 소자 제조방법
US6191484B1 (en) * 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members
KR0185298B1 (ko) * 1995-12-30 1999-04-15 김주용 반도체 소자의 콘택홀 매립용 플러그 형성방법
US5639692A (en) * 1996-04-08 1997-06-17 Chartered Semiconductor Manufacturing Pte, Ltd. Non-etch back SOG process using a metal via stud
US5925577A (en) * 1997-02-19 1999-07-20 Vlsi Technology, Inc. Method for forming via contact hole in a semiconductor device
US5851302A (en) * 1997-02-19 1998-12-22 Vlsi Technology, Inc. Method for dry etching sidewall polymer
US6495442B1 (en) 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US6251773B1 (en) 1999-12-28 2001-06-26 International Business Machines Corporation Method of designing and structure for visual and electrical test of semiconductor devices
US7084066B1 (en) * 2000-07-03 2006-08-01 Cypress Semiconductor Corporation Method of uniformly etching refractory metals, refractory metal alloys and refractory metal silicides
TW477019B (en) * 2000-09-15 2002-02-21 Promos Technologies Inc Via chain structure and process with testing potential
US6569295B2 (en) * 2001-03-20 2003-05-27 International Business Machines Corporation Method for grading surface topography for improved step coverage and planarization
US7358116B2 (en) * 2002-04-29 2008-04-15 Intel Corporation Substrate conductive post formation
US7307013B2 (en) * 2004-06-30 2007-12-11 Sandisk 3D Llc Nonselective unpatterned etchback to expose buried patterned features
US20090165296A1 (en) * 2006-04-04 2009-07-02 Yoash Carmi Patterns of conductive objects on a substrate and method of producing thereof
CN116169118A (zh) * 2019-12-06 2023-05-26 中国科学院微电子研究所 金属化叠层及其制造方法及包括金属化叠层的电子设备
US11328954B2 (en) * 2020-03-13 2022-05-10 International Business Machines Corporation Bi metal subtractive etch for trench and via formation

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2731333A (en) * 1954-05-13 1956-01-17 Komak Inc Method of forming ornamented surfaces
US3489656A (en) * 1964-11-09 1970-01-13 Western Electric Co Method of producing an integrated circuit containing multilayer tantalum compounds
US3679941A (en) * 1969-09-22 1972-07-25 Gen Electric Composite integrated circuits including semiconductor chips mounted on a common substrate with connections made through a dielectric encapsulator
US3756887A (en) * 1971-07-29 1973-09-04 Us Navy Method of making microfuses on a thin film circuitry panel
US3904461A (en) * 1972-10-02 1975-09-09 Bendix Corp Method of manufacturing solderable thin film microcircuit with stabilized resistive films
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
US4203800A (en) * 1977-12-30 1980-05-20 International Business Machines Corporation Reactive ion etching process for metals
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
JPS57130461A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor memory storage
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
FR2564242B1 (fr) * 1984-05-11 1986-09-19 Efcis Procede de fabrication de circuits integres a plusieurs niveaux d'interconnexion en tungstene
JPS613431A (ja) * 1984-06-15 1986-01-09 Nec Corp 多層配線を有する半導体装置およびその製造方法
DE3571723D1 (en) * 1984-08-23 1989-08-24 Fairchild Semiconductor A process for forming vias on integrated circuits

Also Published As

Publication number Publication date
EP0239489B1 (de) 1993-03-17
JPS62279661A (ja) 1987-12-04
CA1249072A (en) 1989-01-17
DE3784751T2 (de) 1993-09-23
EP0239489A3 (en) 1989-05-31
EP0239489A2 (de) 1987-09-30
US4670091A (en) 1987-06-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee