DE3775625D1 - Gedruckte leiterplatte. - Google Patents

Gedruckte leiterplatte.

Info

Publication number
DE3775625D1
DE3775625D1 DE8787103898T DE3775625T DE3775625D1 DE 3775625 D1 DE3775625 D1 DE 3775625D1 DE 8787103898 T DE8787103898 T DE 8787103898T DE 3775625 T DE3775625 T DE 3775625T DE 3775625 D1 DE3775625 D1 DE 3775625D1
Authority
DE
Germany
Prior art keywords
printed circuit
printed
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787103898T
Other languages
English (en)
Inventor
Robert Brewster Hitchcock
Eduardo Kellerman
John Paul Koons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3775625D1 publication Critical patent/DE3775625D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
DE8787103898T 1986-05-16 1987-03-17 Gedruckte leiterplatte. Expired - Lifetime DE3775625D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/863,850 US4700016A (en) 1986-05-16 1986-05-16 Printed circuit board with vias at fixed and selectable locations

Publications (1)

Publication Number Publication Date
DE3775625D1 true DE3775625D1 (de) 1992-02-13

Family

ID=25341930

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787103898T Expired - Lifetime DE3775625D1 (de) 1986-05-16 1987-03-17 Gedruckte leiterplatte.

Country Status (4)

Country Link
US (1) US4700016A (de)
EP (1) EP0249688B1 (de)
JP (1) JPS62274692A (de)
DE (1) DE3775625D1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916260A (en) * 1988-10-11 1990-04-10 International Business Machines Corporation Circuit member for use in multilayered printed circuit board assembly and method of making same
US5224022A (en) * 1990-05-15 1993-06-29 Microelectronics And Computer Technology Corporation Reroute strategy for high density substrates
US5220490A (en) * 1990-10-25 1993-06-15 Microelectronics And Computer Technology Corporation Substrate interconnect allowing personalization using spot surface links
JP3037043B2 (ja) * 1993-10-29 2000-04-24 日本電気株式会社 プリント基板のテスト容易化回路実装方式
KR0157906B1 (ko) * 1995-10-19 1998-12-01 문정환 더미볼을 이용한 비지에이 패키지 및 그 보수방법
US6010058A (en) * 1995-10-19 2000-01-04 Lg Semicon Co., Ltd. BGA package using a dummy ball and a repairing method thereof
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6859916B1 (en) * 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US6829757B1 (en) 2001-06-03 2004-12-07 Cadence Design Systems, Inc. Method and apparatus for generating multi-layer routes
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
JP4935225B2 (ja) * 2006-07-28 2012-05-23 株式会社島津製作所 電子部品実装体
US7465882B2 (en) * 2006-12-13 2008-12-16 International Business Machines Corporation Ceramic substrate grid structure for the creation of virtual coax arrangement
CN101902874A (zh) * 2009-05-27 2010-12-01 鸿富锦精密工业（深圳）有限公司 多层印刷电路板
US10778584B2 (en) 2013-11-05 2020-09-15 Cisco Technology, Inc. System and method for multi-path load balancing in network fabrics
US9674086B2 (en) 2013-11-05 2017-06-06 Cisco Technology, Inc. Work conserving schedular based on ranking
US9769078B2 (en) 2013-11-05 2017-09-19 Cisco Technology, Inc. Dynamic flowlet prioritization
US10951522B2 (en) 2013-11-05 2021-03-16 Cisco Technology, Inc. IP-based forwarding of bridged and routed IP packets and unicast ARP
US9655232B2 (en) 2013-11-05 2017-05-16 Cisco Technology, Inc. Spanning tree protocol (STP) optimization techniques
US9397946B1 (en) 2013-11-05 2016-07-19 Cisco Technology, Inc. Forwarding to clusters of service nodes
US9825857B2 (en) 2013-11-05 2017-11-21 Cisco Technology, Inc. Method for increasing Layer-3 longest prefix match scale
US9502111B2 (en) 2013-11-05 2016-11-22 Cisco Technology, Inc. Weighted equal cost multipath routing
US9876711B2 (en) 2013-11-05 2018-01-23 Cisco Technology, Inc. Source address translation in overlay networks
US9374294B1 (en) 2013-11-05 2016-06-21 Cisco Technology, Inc. On-demand learning in overlay networks
US9509092B2 (en) * 2013-11-06 2016-11-29 Cisco Technology, Inc. System and apparatus for network device heat management
US10116493B2 (en) 2014-11-21 2018-10-30 Cisco Technology, Inc. Recovering from virtual port channel peer failure
US10142163B2 (en) 2016-03-07 2018-11-27 Cisco Technology, Inc BFD over VxLAN on vPC uplinks
US10333828B2 (en) 2016-05-31 2019-06-25 Cisco Technology, Inc. Bidirectional multicasting over virtual port channel
US11509501B2 (en) 2016-07-20 2022-11-22 Cisco Technology, Inc. Automatic port verification and policy application for rogue devices
US10193750B2 (en) 2016-09-07 2019-01-29 Cisco Technology, Inc. Managing virtual port channel switch peers from software-defined network controller
US10547509B2 (en) 2017-06-19 2020-01-28 Cisco Technology, Inc. Validation of a virtual port channel (VPC) endpoint in the network fabric

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3726989A (en) * 1970-07-27 1973-04-10 Hughes Aircraft Co Circuit module providing high density interconnections
FR2243578B1 (de) * 1973-09-12 1976-11-19 Honeywell Bull Soc Ind
DE2352973A1 (de) * 1973-10-23 1975-05-07 Computer Ges Konstanz Dicht gepackte elektrische baugruppe
DE2553534A1 (de) * 1975-11-28 1977-06-02 Licentia Gmbh Leitungstraegerplatte
JPS5530822A (en) * 1978-08-25 1980-03-04 Fujitsu Ltd Printed board
GB2060266B (en) * 1979-10-05 1984-05-31 Borrill P L Multilayer printed circuit board
US4598166A (en) * 1984-08-06 1986-07-01 Gte Communication Systems Corporation High density multi-layer circuit arrangement
CA1237820A (en) * 1985-03-20 1988-06-07 Hitachi, Ltd. Multilayer printed circuit board

Also Published As

Publication number Publication date
EP0249688A2 (de) 1987-12-23
JPS62274692A (ja) 1987-11-28
US4700016A (en) 1987-10-13
JPH0230200B2 (de) 1990-07-04
EP0249688B1 (de) 1992-01-02
EP0249688A3 (en) 1988-05-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8330 Complete disclaimer