DE3710223C2 - Conductor arrangement with an overlapping connection between a metallic conductor and an ITO layer conductor on an insulating plate made of glass - Google Patents
Conductor arrangement with an overlapping connection between a metallic conductor and an ITO layer conductor on an insulating plate made of glassInfo
- Publication number
- DE3710223C2 DE3710223C2 DE19873710223 DE3710223A DE3710223C2 DE 3710223 C2 DE3710223 C2 DE 3710223C2 DE 19873710223 DE19873710223 DE 19873710223 DE 3710223 A DE3710223 A DE 3710223A DE 3710223 C2 DE3710223 C2 DE 3710223C2
- Authority
- DE
- Germany
- Prior art keywords
- arrangement according
- layer
- conductor
- conductor track
- metallic conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0108—Transparent
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0317—Thin film conductor layer; Thin film passive component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/032—Materials
- H05K2201/0326—Inorganic, non-metallic conductor, e.g. indium-tin oxide [ITO]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0391—Using different types of conductors
Description
Die vorliegende Erfindung betrifft eine Leiterbahnenanordnung mit einer überlappenden Verbindung zwischen einer metallischen Lei terbahn und einer ITO-Schicht-Leiterbahn auf einer Isolierplatte aus Glas.The present invention relates to an interconnect arrangement an overlapping connection between a metallic lead terbahn and an ITO layer conductor track on an insulating plate of glass.
Es ist bekannt, bei Flüssigkristallanzeigezellen die aus einer transparenten, leitenden Schicht bestehenden Elektroden in Form von Leiterbahnen aus dem Inneren der Zelle herausführen. Dabei ist eine der beiden gläsernen Deckplatten größer als die andere, so daß die herausgeführte ITO-Schicht auf der Oberfläche des größeren Substrats von außen kontaktierbar sind.It is known that the liquid crystal display cells from a transparent, conductive layer existing electrodes in the form lead out of conductor tracks from inside the cell. there one of the two glass cover plates is larger than the other, so that the led out ITO layer on the surface of the larger substrate can be contacted from the outside.
Aus der DE 32 08 611 ist es bekannt diese herausgeführten ITO- Leiterbahnen mit überlappenden metallischen Leiterbahnen auf der Glasplatte zu kontaktieren. Diese meist mehrschichtigen metalli schen Leiterbahnen müssen einerseits guten und dauerhaften elek trischen Kontakt mit den ITO-Leiterbahnen gewährleisten und ande rerseits lötfähig sein, damit Lötverbindungen mit den Anschlüssen der Schaltkreise möglich sind.It is known from DE 32 08 611 that these ITO Traces with overlapping metallic traces on the Contact glass plate. These mostly multilayered metalli On the one hand, conductor tracks must have good and durable electrical Ensure electrical contact with the ITO conductor tracks and others be able to be soldered, so that solder connections to the connections of the circuits are possible.
Der DE 23 21 099 ist eine Anordnung zum Anschluß der großflächi gen Gegenelektroden mittels schmaler Leiterbahnen an einen ge meinsamen Kontakt zu entnehmen. Leiterbahnen und Gegenelektroden können aus unterschiedlichen Materialien bestehen und überlappend ausgeführt sein. Aus ITO bestehende Leiterbahnen können in be stimmten Bereichen durch Aufbringen zusätzlicher Metallschichten verstärkt werden. DE 23 21 099 is an arrangement for connecting the large area counter electrodes by means of narrow conductor tracks to a ge to find out common contact. Conductor tracks and counter electrodes can consist of different materials and overlap be executed. Traces made of ITO can be used in be agreed areas by applying additional metal layers be reinforced.
Probleme dieser Kontaktierungstechnik liegen darin, auch bei großen Temperaturunterschieden, z. B. zwischen 200°C und -20°C ein Loslösen der Schichten von dem Glassubstrat zu vermeiden.There are problems with this contacting technique, too large temperature differences, e.g. B. between 200 ° C and -20 ° C. Avoid detachment of the layers from the glass substrate.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, eine Lei terbahnenverbindung zwischen einer ITO-Schicht-Leiterbahn und ei ner metallischen Leiterbahn so auszubilden, daß die Leiterbahnan ordnung einen geringen elektrischen Widerstand aufweist und im Übergangsbereich zwischen den unterschiedlichen Leiterbahnen auch bei größeren Temperaturänderungen keine mechanischen oder elek trischen Mängel auftreten.The present invention has for its object a Lei Interconnection between an ITO layer interconnect and an egg ner metallic conductor track so that the conductor track order has a low electrical resistance and in Transition area between the different conductor tracks too no mechanical or elec tric defects occur.
Diese Aufgabe wird durch die im Patentanspruch 1 angegebenen Merkmale gelöst.This object is achieved by the specified in claim 1 Features resolved.
Durch die beschriebene Ausgestaltung des Überlappungsbereichs zwischen der ITO-Schicht und der mehrlagigen Metallschicht wird verhindert, daß bei größeren Temperaturänderungen, wie sie z. B. beim Löten auftreten. Loslösungen der Schichten und damit Kon taktschwierigkeiten auftreten können. Unter einer ITO-(indium- tin-oxid)Schicht wird eine äußerst dünne und transparente elek trisch leitende Schicht auf Zinnoxydbasis verstanden, die übli cherweise als Elektroden in Flüssigkristallanzeigezellen oder in Elektrolumineszenzzellen verwendet werden.Due to the described configuration of the overlap area between the ITO layer and the multilayer metal layer prevents that with major temperature changes, such as. B. occur during soldering. Detachment of the layers and thus con clock difficulties can occur. Under an ITO (indium tin oxide) layer becomes an extremely thin and transparent elec tric conductive layer based on tin oxide understood, the übli usually as electrodes in liquid crystal display cells or in Electroluminescent cells are used.
Anhand des in den Fig. 1 und 2 beschriebenen Ausführungsbei spiels wird die Erfindung nachfolgend näher erläutert. Based on the game Ausführungsbei described in FIGS . 1 and 2, the invention is explained in more detail below.
Die Figuren zeigen in der Aufsicht einen Ausschnitt einer Oberfläche einer Glasplatte 1, die einen Teil der Deckplatte einer Flüssigkristallanzeigezelle ist, die über die andere Deckplatte hinaussteht. Auf diesem überstehenden Teil der gläsernen Deckplatte werden Ansteuerschaltkreise und die dazu erforderlichen Lei terbahnen aufgebracht.The figures show a top view of a section of a surface of a glass plate 1 , which is part of the cover plate of a liquid crystal display cell, which projects beyond the other cover plate. Control circuits and the conductor tracks required for this purpose are applied to this protruding part of the glass cover plate.
Die in Fig. 1 und Fig. 2 gezeigten Ausschnitte der Deckplatte 1 weist ein Ende einer ITO-Leiterbahn 2 auf, die als Zuführung aus der Flüssigkristallzelle heraus geführt ist und die die Breite a besitzt.The sections of the cover plate 1 shown in FIG. 1 and FIG. 2 have one end of an ITO conductor track 2 , which is led out of the liquid crystal cell and has the width a.
Des weiteren ist auf der gleichen Oberfläche der Glas platte 1 eine Leiterbahn 3 vorgesehen, die wesentlich dicker ist als die ITO-Leiterbahn 1 und aus mehreren Schichten unterschiedlicher Metalle besteht. Bevorzugt besteht diese metallische Leiterbahn aus einer aufge dampften Chromschicht, einer darauf aufgebrachten dickeren Kupferschicht und einer Zinnschicht. Insgesamt ist die Leiterbahn 3 nicht dicker als 10 µm, insbeson dere etwa 3 bis 7,5 µm dick. Die ITO-Schicht 2 ist etwa 25 nm dick.Furthermore, a conductor track 3 is provided on the same surface of the glass plate 1 , which is much thicker than the ITO conductor track 1 and consists of several layers of different metals. This metallic conductor track preferably consists of a vapor-deposited chrome layer, a thicker copper layer applied thereon and a tin layer. Overall, the conductor track 3 is not thicker than 10 microns, in particular about 3 to 7.5 microns thick. The ITO layer 2 is approximately 25 nm thick.
Die elektrische Verbindung zwischen der ITO-Schicht 2 und der Mehrschicht-Metallschicht 3 ist in der Weise ausgebildet, daß die Metallschicht 3 einen fingerför migen Fortsatz 4 aufweist, der die ITO-Schicht über lappend bedeckt. Gemäß der Erfindung ist die Breite b des fingerförmigen Fortsatzes 4 so bemessen, daß sie höchstens 0,75 mal der Breite a der ITO-Leiterbahn entspricht. The electrical connection between the ITO layer 2 and the multilayer metal layer 3 is formed in such a way that the metal layer 3 has a finger-shaped extension 4 which covers the ITO layer overlapping. According to the invention, the width b of the finger-shaped extension 4 is dimensioned such that it corresponds to a maximum of 0.75 times the width a of the ITO conductor track.
Gemäß einem bevorzugten ausführungsbeispiel soll gelten
According to a preferred exemplary embodiment, the following applies
Die Länge l des fingerförmigen Fortsatzes soll höch stens 0,70 mm, insbesondere nicht mehr als 0,5 mm betragen. Dabei überdeckt etwa die halbe Länge l die ITO-Schicht 2.The length l of the finger-shaped extension should be at most 0.70 mm, in particular not more than 0.5 mm. About half the length l covers the ITO layer 2 .
Gemäß einer bevorzugten Weiterbildung soll die metal lische Leiterbahn 3 eine Abbiegung 5 aufweisen, wobei der Abbiegewinkel α vorzugsweise nicht kleiner als 30° sein soll. Dadurch werden nachteilige Auswirkungen bei Temperaturänderungen weiter reduziert.According to a preferred development, the metallic conductor track 3 should have a bend 5 , the bend angle α preferably not being less than 30 °. This further reduces the adverse effects of temperature changes.
Claims (10)
eine aufgedampfte Schicht eines 3- oder 4-wertigen Metalls wie Ti, Al, Zr, Ni, La oder insbesondere Chrom;
eine darauf aufgedampfte Cu-Schicht, die durch eine nachfolgend galvanisch abgeschiedene weitere Kupferschicht verstärkt ist;
eine auf der Kupferschicht galvanisch abgeschiedene Zinnschicht.7. trace arrangement according to one of claims 1 to 6, characterized in that the multilayer metallic conductor track ( 3 ) has the following layer structure:
an evaporated layer of a trivalent or tetravalent metal such as Ti, Al, Zr, Ni, La or in particular chromium;
a Cu layer deposited thereon, which is reinforced by a further galvanically deposited further copper layer;
a tin layer electrodeposited on the copper layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19873710223 DE3710223C2 (en) | 1987-03-27 | 1987-03-27 | Conductor arrangement with an overlapping connection between a metallic conductor and an ITO layer conductor on an insulating plate made of glass |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19873710223 DE3710223C2 (en) | 1987-03-27 | 1987-03-27 | Conductor arrangement with an overlapping connection between a metallic conductor and an ITO layer conductor on an insulating plate made of glass |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3710223A1 DE3710223A1 (en) | 1988-10-06 |
DE3710223C2 true DE3710223C2 (en) | 2002-02-21 |
Family
ID=6324183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19873710223 Expired - Fee Related DE3710223C2 (en) | 1987-03-27 | 1987-03-27 | Conductor arrangement with an overlapping connection between a metallic conductor and an ITO layer conductor on an insulating plate made of glass |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE3710223C2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4033430A1 (en) * | 1990-10-20 | 1992-04-23 | Licentia Gmbh | Solder coating of conductor pattern for attaching TAB-assembled device - consists of placing foil of flux material with a solder pattern on top, over substrate pattern |
DE4035362A1 (en) * | 1990-11-07 | 1992-05-14 | Licentia Gmbh | LCD support panel with improved electrode structure - uses internal electrodes of indium, tin and palladium oxide(s) and an external array strengthened by additional metal deposition |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2321099A1 (en) * | 1972-04-28 | 1973-11-08 | Philips Nv | METHOD OF MAKING AN ARRANGEMENT WITH A TRANSPARENT CONDUCTOR PATTERN AND ARRANGEMENT PRODUCED BY THIS METHOD |
DE3208611A1 (en) * | 1982-03-10 | 1983-09-22 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Liquid-crystal cell |
-
1987
- 1987-03-27 DE DE19873710223 patent/DE3710223C2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2321099A1 (en) * | 1972-04-28 | 1973-11-08 | Philips Nv | METHOD OF MAKING AN ARRANGEMENT WITH A TRANSPARENT CONDUCTOR PATTERN AND ARRANGEMENT PRODUCED BY THIS METHOD |
DE3208611A1 (en) * | 1982-03-10 | 1983-09-22 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Liquid-crystal cell |
Also Published As
Publication number | Publication date |
---|---|
DE3710223A1 (en) | 1988-10-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
8120 | Willingness to grant licenses paragraph 23 | ||
8127 | New person/name/address of the applicant |
Owner name: AEG GESELLSCHAFT FUER MODERNE INFORMATIONSSYSTEME |
|
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |