DE3689879D1 - Arithmetisch-logische Schaltung. - Google Patents
Arithmetisch-logische Schaltung.Info
- Publication number
- DE3689879D1 DE3689879D1 DE3689879T DE3689879T DE3689879D1 DE 3689879 D1 DE3689879 D1 DE 3689879D1 DE 3689879 T DE3689879 T DE 3689879T DE 3689879 T DE3689879 T DE 3689879T DE 3689879 D1 DE3689879 D1 DE 3689879D1
- Authority
- DE
- Germany
- Prior art keywords
- arithmetic
- logic circuit
- logic
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3868—Bypass control, i.e. possibility to transfer an operand unchanged to the output
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Logic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60297011A JPH07113884B2 (ja) | 1985-12-28 | 1985-12-28 | 論理回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3689879D1 true DE3689879D1 (de) | 1994-07-07 |
DE3689879T2 DE3689879T2 (de) | 1994-11-03 |
Family
ID=17841091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3689879T Expired - Lifetime DE3689879T2 (de) | 1985-12-28 | 1986-12-29 | Arithmetisch-logische Schaltung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5165034A (de) |
EP (1) | EP0230668B1 (de) |
JP (1) | JPH07113884B2 (de) |
DE (1) | DE3689879T2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4811214A (en) * | 1986-11-14 | 1989-03-07 | Princeton University | Multinode reconfigurable pipeline computer |
US5572160A (en) * | 1994-12-01 | 1996-11-05 | Teradyne, Inc. | Architecture for RF signal automatic test equipment |
US7139899B2 (en) * | 1999-09-03 | 2006-11-21 | Cisco Technology, Inc. | Selected register decode values for pipeline stage register addressing |
JP3776644B2 (ja) * | 1999-10-05 | 2006-05-17 | 富士通株式会社 | パイプライン演算装置、情報処理装置およびパイプライン演算装置の演算方法 |
US7526595B2 (en) * | 2002-07-25 | 2009-04-28 | International Business Machines Corporation | Data path master/slave data processing device apparatus and method |
US8495122B2 (en) | 2003-12-29 | 2013-07-23 | Xilinx, Inc. | Programmable device with dynamic DSP architecture |
JP5195341B2 (ja) * | 2008-11-19 | 2013-05-08 | Tdk株式会社 | リチウムイオン二次電池用セパレータ及びリチウムイオン二次電池 |
US8543635B2 (en) | 2009-01-27 | 2013-09-24 | Xilinx, Inc. | Digital signal processing block with preadder stage |
US8479133B2 (en) * | 2009-01-27 | 2013-07-02 | Xilinx, Inc. | Method of and circuit for implementing a filter in an integrated circuit |
JP2016099935A (ja) * | 2014-11-26 | 2016-05-30 | 株式会社ジャパンディスプレイ | データ通信装置、データ通信システム |
US11431379B1 (en) | 2021-03-31 | 2022-08-30 | Teradyne, Inc. | Front-end module |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3319228A (en) * | 1964-04-20 | 1967-05-09 | Bunker Ramo | Digital storage register transfer apparatus |
US3751650A (en) * | 1971-06-28 | 1973-08-07 | Burroughs Corp | Variable length arithmetic unit |
US3771141A (en) * | 1971-11-08 | 1973-11-06 | Culler Harrison Inc | Data processor with parallel operations per instruction |
US3919694A (en) * | 1974-05-10 | 1975-11-11 | Hewlett Packard Co | Circulating shift register memory having editing and subroutining capability |
US4133028A (en) * | 1976-10-01 | 1979-01-02 | Data General Corporation | Data processing system having a cpu register file and a memory address register separate therefrom |
US4078251A (en) * | 1976-10-27 | 1978-03-07 | Texas Instruments Incorporated | Electronic calculator or microprocessor with mask logic effective during data exchange operation |
JPS5363944A (en) * | 1976-11-19 | 1978-06-07 | Nec Corp | Diagnosis circuit for digital logic circuit |
FR2443723A1 (fr) * | 1978-12-06 | 1980-07-04 | Cii Honeywell Bull | Dispositif de reduction du temps d'acces aux informations contenues dans une memoire d'un systeme de traitement de l'information |
JPS5693192A (en) * | 1979-12-25 | 1981-07-28 | Fujitsu Ltd | Diagnosis system |
JPS56110160A (en) * | 1980-02-06 | 1981-09-01 | Nec Corp | Test diagnostic system of information processing system |
BG33404A1 (en) * | 1980-07-22 | 1983-02-15 | Kasabov | Registrating arithmetic device |
US4467444A (en) * | 1980-08-01 | 1984-08-21 | Advanced Micro Devices, Inc. | Processor unit for microcomputer systems |
DE3040931C1 (de) * | 1980-10-30 | 1982-04-29 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und Anordnung zur Verknuepfung von Operanden variabler Laenge in Datenverarbeitungsanlagen |
KR860001434B1 (ko) * | 1980-11-21 | 1986-09-24 | 후지쑤 가부시끼가이샤 | 데이타 처리시 스템 |
US4528625A (en) * | 1982-02-11 | 1985-07-09 | Texas Instruments Incorporated | Input/output instruction execution in microcomputer |
US4559608A (en) * | 1983-01-21 | 1985-12-17 | Harris Corporation | Arithmetic logic unit |
JPS6013266A (ja) * | 1983-07-04 | 1985-01-23 | Hitachi Ltd | 診断容易化回路 |
GB8401808D0 (en) * | 1984-01-24 | 1984-02-29 | Int Computers Ltd | Binary multiplication |
US4785393A (en) * | 1984-07-09 | 1988-11-15 | Advanced Micro Devices, Inc. | 32-Bit extended function arithmetic-logic unit on a single chip |
JPS62140137A (ja) * | 1985-12-16 | 1987-06-23 | Toshiba Corp | Aluを用いたデータ保持方法 |
-
1985
- 1985-12-28 JP JP60297011A patent/JPH07113884B2/ja not_active Expired - Lifetime
-
1986
- 1986-12-29 DE DE3689879T patent/DE3689879T2/de not_active Expired - Lifetime
- 1986-12-29 EP EP86118117A patent/EP0230668B1/de not_active Expired - Lifetime
-
1991
- 1991-10-15 US US07/776,728 patent/US5165034A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS62156734A (ja) | 1987-07-11 |
EP0230668B1 (de) | 1994-06-01 |
US5165034A (en) | 1992-11-17 |
EP0230668A2 (de) | 1987-08-05 |
EP0230668A3 (en) | 1990-03-28 |
JPH07113884B2 (ja) | 1995-12-06 |
DE3689879T2 (de) | 1994-11-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |